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fsl/qe: setup clock source for TDM mode

bug report Dan Carpenter 2 participants 2 messages Jan 31, 2018 – Feb 1, 2018

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#0 lore raw

Hello Zhao Qiang,

The patch bb8b2062aff3: "fsl/qe: setup clock source for TDM mode" from Jun 6, 2016, leads to the following static checker warning:

	drivers/soc/fsl/qe/ucc.c:629 ucc_get_tdm_sync_shift()
	warn: both sides of ternary the same: '30' RX_SYNC_SHIFT_BASE RX_SYNC_SHIFT_BASE

drivers/soc/fsl/qe/ucc.c
625 static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num) 626 {
627 u32 shift;
628

   629          shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : RX_SYNC_SHIFT_BASE;
                                                                     ^^^^^^^^^^^^^^^^^^

Maybe this one should have been TX_?

   630          shift -= tdm_num * 2;
   631  
   632          return shift;
   633  }

regards,
dan carpenter

#1 lore raw

T24gMjAxOC8xLzMxIDIzOjMwLCBEYW4gQ2FycGVudGVyIDxkYW4uY2FycGVudGVyQG9yYWNsZS5j b20+IHdyb3RlDQoNCi0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQpGcm9tOiBEYW4gQ2FycGVu dGVyIFttYWlsdG86ZGFuLmNhcnBlbnRlckBvcmFjbGUuY29tXSANClNlbnQ6IDIwMTjE6jHUwjMx yNUgMjM6MzANClRvOiBRaWFuZyBaaGFvIDxxaWFuZy56aGFvQG54cC5jb20+DQpDYzogbGludXhw cGMtZGV2QGxpc3RzLm96bGFicy5vcmcNClN1YmplY3Q6IFtidWcgcmVwb3J0XSBmc2wvcWU6IHNl dHVwIGNsb2NrIHNvdXJjZSBmb3IgVERNIG1vZGUNCg0KSGVsbG8gWmhhbyBRaWFuZywNCg0KVGhl IHBhdGNoIGJiOGIyMDYyYWZmMzogImZzbC9xZTogc2V0dXAgY2xvY2sgc291cmNlIGZvciBURE0g bW9kZSINCmZyb20gSnVuIDYsIDIwMTYsIGxlYWRzIHRvIHRoZSBmb2xsb3dpbmcgc3RhdGljIGNo ZWNrZXIgd2FybmluZzoNCg0KCWRyaXZlcnMvc29jL2ZzbC9xZS91Y2MuYzo2MjkgdWNjX2dldF90 ZG1fc3luY19zaGlmdCgpDQoJd2FybjogYm90aCBzaWRlcyBvZiB0ZXJuYXJ5IHRoZSBzYW1lOiAn MzAnIFJYX1NZTkNfU0hJRlRfQkFTRSBSWF9TWU5DX1NISUZUX0JBU0UNCg0KZHJpdmVycy9zb2Mv ZnNsL3FlL3VjYy5jDQogICA2MjUgIHN0YXRpYyB1MzIgdWNjX2dldF90ZG1fc3luY19zaGlmdChl bnVtIGNvbW1fZGlyIG1vZGUsIHUzMiB0ZG1fbnVtKQ0KICAgNjI2ICB7DQogICA2MjcgICAgICAg ICAgdTMyIHNoaWZ0Ow0KICAgNjI4ICANCiAgIDYyOSAgICAgICAgICBzaGlmdCA9IChtb2RlID09 IENPTU1fRElSX1JYKSA/IFJYX1NZTkNfU0hJRlRfQkFTRSA6IFJYX1NZTkNfU0hJRlRfQkFTRTsN CiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgIF5eXl5eXl5eXl5eXl5eXl5eXg0KDQpNYXliZSB0aGlzIG9uZSBzaG91bGQg aGF2ZSBiZWVuIFRYXz8NCg0KVGhhbmsgeW91IHZlcnkgbXVjaCwgaXQgaXMgYSB0eXBvLCBJIHdp bGwgc2VuZCBhIHBhdGNoIHRvIGZpeCBpdC4NCg0KQlINClFpYW5nIFpoYW8NCg==