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ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes

PATCH New Gregory CLEMENT 1 participant 2 messages Mar 1, 2018 – Mar 9, 2018

Subsystems (2)
Device tree bindings Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support
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Gregory CLEMENT

author maintainer
#0 lore raw

PATCH 1/1 ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes

This extra clock is needed to access the registers of the UARTs used on CP110 component of the Armada 7K/8K SoCs.

Signed-off-by Gregory CLEMENT <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/marvell/armada-cp110.dtsi +12 -4
index d3f422f8f086..355bb295e4d9 100644
@@ -303,7 +303,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 

@@ -313,7 +315,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 

@@ -323,7 +327,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 

@@ -333,7 +339,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
Signature · 1 line
2.16.1
author maintainer
#1 lore raw

PATCH 1/1 ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes

Hi,

Quoted 4 lines · Gregory CLEMENT

This extra clock is needed to access the registers of the UARTs used on CP110 component of the Armada 7K/8K SoCs.

Signed-off-by Gregory CLEMENT <[email protected]>

Applied on mvebu/dt64

Gregory

Quoted 55 lines
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/marvell/armada-cp110.dtsi +12 -4
index d3f422f8f086..355bb295e4d9 100644
@@ -303,7 +303,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 

@@ -313,7 +315,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 

@@ -323,7 +327,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
 

@@ -333,7 +339,9 @@
 			reg-shift = <2>;
 			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <1>;
-			clocks = <&CP110_LABEL(clk) 1 21>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&CP110_LABEL(clk) 1 21>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "disabled";
 		};
Signature · 1 line
2.16.1
Signature · 3 lines
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com