s390x/tcg: fix loading 31bit PSWs with the highest bit set

Let's also put the 31-bit hack in front of the REAL MMU, otherwise right now we get errors when loading a PSW where the highest bit is set (e.g. via s390-netboot.img). The highest bit is not masked away, therefore we inject addressing exceptions into the guest.

The proper fix will later be to do all address wrapping before accessing the MMU - so we won't get any "wrong" entries in there (which makes flushing also easier). But that will require more work (wrapping in load_psw, wrapping when incrementing the PC, wrapping every memory access).

This fixes the tests/pxe-test test.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/excp_helper.c | 4 ++++
 1 file changed, 4 insertions(+)

target/s390x/excp_helper.c +0 -0

index 411051edc3..dfee221111 100644

Let's also put the 31-bit hack in front of the REAL MMU, otherwise right now we get errors when loading a PSW where the highest bit is set (e.g. via s390-netboot.img). The highest bit is not masked away, therefore we inject addressing exceptions into the guest.

The proper fix will later be to do all address wrapping before accessing the MMU - so we won't get any "wrong" entries in there (which makes flushing also easier). But that will require more work (wrapping in load_psw, wrapping when incrementing the PC, wrapping every memory access).

This fixes the tests/pxe-test test.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/excp_helper.c | 4 ++++
 1 file changed, 4 insertions(+)

target/s390x/excp_helper.c +0 -0

index 411051edc3..dfee221111 100644

Quoted 23 lines · David Hildenbrand

Let's also put the 31-bit hack in front of the REAL MMU, otherwise right now we get errors when loading a PSW where the highest bit is set (e.g. via s390-netboot.img). The highest bit is not masked away, therefore we inject addressing exceptions into the guest.

The proper fix will later be to do all address wrapping before accessing the MMU - so we won't get any "wrong" entries in there (which makes flushing also easier). But that will require more work (wrapping in load_psw, wrapping when incrementing the PC, wrapping every memory access).

This fixes the tests/pxe-test test.

Signed-off-by David Hildenbrand <[email protected]>

---
 target/s390x/excp_helper.c | 4 ++++
 1 file changed, 4 insertions(+)

target/s390x/excp_helper.c +0 -0

index 411051edc3..dfee221111 100644

target/s390x/excp_helper.c int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, · line 113

Quoted 7 lines

target/s390x/excp_helper.c +4 -0

@@ -107,6 +107,10 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
             return 1;
         }
     } else if (mmu_idx == MMU_REAL_IDX) {
+        /* 31-Bit mode */
+        if (!(env->psw.mask & PSW_MASK_64)) {
+            vaddr &= 0x7fffffff;
+        }

Since the preceeding if-statement has exactly the same check, I think you could also merge the two checks by putting that in front of the if-statement instead?

Apart from that, patch looks good to me.

Thomas