powercap: intel_rapl: Add support for Cannon Lake

PATCH In review Harry Pan 5 participants 13 messages Mar 9, 2018 – Mar 31, 2018

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x86 perf events Power management core

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Harry Pan

author

2018-03-09 12:15 UTC #0 lore raw

PATCH 1/3 powercap: intel_rapl: Add support for Cannon Lake

Cannon Lake microarchitecture is similar to Kaby Lake in terms of RAPL, this patch enables CNL RAPL support.

Signed-off-by Harry Pan <[email protected]>

---
 drivers/powercap/intel_rapl.c | 1 +
 1 file changed, 1 insertion(+)

drivers/powercap/intel_rapl.c +1 -0

index 35636e1d8a3d..295d8dcba48c 100644
@@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
 	RAPL_CPU(INTEL_FAM6_SKYLAKE_X,		rapl_defaults_hsw_server),
 	RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE,	rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE,	rapl_defaults_core),
 
 	RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1,	rapl_defaults_byt),
 	RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT,	rapl_defaults_cht),

Signature · 1 line

2.13.5

Harry Pan

author

2018-03-09 14:37 UTC #1 lore raw

PATCH 2/3 perf/x86/intel: Add Cannon Lake support of RAPL profiling

This patch enables RAPL counters (energy consumption counters) support for Cannon Lake processors.

ESU and power domains refer to Intel Software Developers' Manual, Vol. 4, Order No. 335592.

Usage example:

$ perf list
$ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10

Signed-off-by Harry Pan <[email protected]>

---
 arch/x86/events/intel/rapl.c | 2 ++
 1 file changed, 2 insertions(+)

arch/x86/events/intel/rapl.c +2 -0

index a2efb490f743..32f3e9423e99 100644
@@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE,  skl_rapl_init),
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
 
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE,  skl_rapl_init),
+
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),

Signature · 1 line

2.13.5

Benson Leung

Reviewed-by on v1 2/3

2018-03-19 23:05 UTC #2 lore raw

Re: [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling

Hi Harry,

Quoted 6 lines · Harry Pan

This patch enables RAPL counters (energy consumption counters) support for Cannon Lake processors.
ESU and power domains refer to Intel Software Developers' Manual, Vol. 4, Order No. 335592.

Quoted 6 lines

Usage example:
$ perf list
$ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10
Signed-off-by Harry Pan <[email protected]>

Reviewed-by Benson Leung <[email protected]>

Quoted 10 lines

---
 arch/x86/events/intel/rapl.c | 2 ++
 1 file changed, 2 insertions(+)

arch/x86/events/intel/rapl.c +0 -0

index a2efb490f743..32f3e9423e99 100644

arch/x86/events/intel/rapl.c static const struct x86_cpu_id rapl_cpu_match[] __initconst = { · line 781

Quoted 8 lines

arch/x86/events/intel/rapl.c +2 -0

@@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE,  skl_rapl_init),
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
 
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE,  skl_rapl_init),
+
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),

Thanks,

Signature · 7 lines

Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

Puthikorn Voravootivat

Tested-by

2018-03-19 23:11 UTC #3 lore raw

Re: [PATCH 2/3] perf/x86/intel: Add Cannon Lake support of RAPL profiling

Quoted 9 lines · Benson Leung

Hi Harry,
Quoted 6 lines · Harry Pan
This patch enables RAPL counters (energy consumption counters) support for Cannon Lake processors.
ESU and power domains refer to Intel Software Developers' Manual, Vol. 4, Order No. 335592.

Quoted 8 lines

Quoted 6 lines
Usage example:
$ perf list
$ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10
Signed-off-by Harry Pan <[email protected]>
Reviewed-by Benson Leung <[email protected]>

Tested-by Puthikorn Voravootivat <[email protected]>

Quoted 9 lines

arch/x86/events/intel/rapl.c static const struct x86_cpu_id rapl_cpu_match[]
Quoted 9 lines
---
 arch/x86/events/intel/rapl.c | 2 ++
 1 file changed, 2 insertions(+)
arch/x86/events/intel/rapl.c +0 -0
index a2efb490f743..32f3e9423e99 100644
@@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[]

__initconst = {

Quoted 4 lines

arch/x86/events/intel/rapl.c static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
Quoted 4 lines
arch/x86/events/intel/rapl.c +1 -0
      X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE,  skl_rapl_init),
      X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
 
+     X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE,

skl_rapl_init),

Quoted 15 lines

arch/x86/events/intel/rapl.c static const struct x86_cpu_id rapl_cpu_match[] __initconst = { · line 781
Quoted 5 lines
arch/x86/events/intel/rapl.c +1 -0
+
      X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
      X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),
 
Thanks,
--
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

tip-bot for Harry Pan

merge bot

2018-03-31 10:20 UTC #4 lore raw

[tip:perf/core] perf/x86/intel: Add Cannon Lake support for RAPL profiling

In reply to Harry Pan

perf/x86/intel: Add Cannon Lake support for RAPL profiling

Commit-ID:  490d03e83da2a5e9d7db84b1ec30a9c95415787e
Gitweb:     https://git.kernel.org/tip/490d03e83da2a5e9d7db84b1ec30a9c95415787e
Author:     Harry Pan <[email protected]>
AuthorDate: Fri, 9 Mar 2018 20:15:47 +0800
Committer:  Ingo Molnar <[email protected]>
CommitDate: Sat, 31 Mar 2018 11:28:36 +0200

perf/x86/intel: Add Cannon Lake support for RAPL profiling

This patch enables RAPL counters (energy consumption counters) support for Cannon Lake processors.

( ESU and power domains refer to Intel Software Developers' Manual,
Vol. 4, Order No. 335592. )

Usage example:

  $ perf list
  $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10

Tested-by Puthikorn Voravootivat <[email protected]>

Signed-off-by Harry Pan <[email protected]>

Reviewed-by Benson Leung <[email protected]>

Cc Alexander Shishkin <[email protected]>

Cc Arnaldo Carvalho de Melo <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Stephane Eranian <[email protected]>

Cc Thomas Gleixner <[email protected]>

Cc Vince Weaver <[email protected]>

Cc [email protected]

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/events/intel/rapl.c | 2 ++
 1 file changed, 2 insertions(+)

arch/x86/events/intel/rapl.c +2 -0

index a2efb490f743..32f3e9423e99 100644
@@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE,  skl_rapl_init),
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
 
+	X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE,  skl_rapl_init),
+
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
 	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),

Harry Pan

author

2018-03-09 14:38 UTC #5 lore raw

PATCH 3/3 perf/x86/intel: Enable C-state residency events for Cannon Lake

In reply to Harry Pan

Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10 state residency counters, this patch enables those counters.

The MSR information is based on Intel Software Developers' Manual, Vol. 4, Order No. 335592.

Signed-off-by Harry Pan <[email protected]>

---
 arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++-------------
 1 file changed, 31 insertions(+), 13 deletions(-)

arch/x86/events/intel/cstate.c +31 ~~-13~~

index 72db0664a53d..9aca448bb8e6 100644
@@ -40,50 +40,51 @@
  * Model specific counters:
  *	MSR_CORE_C1_RES: CORE C1 Residency Counter
  *			 perf code: 0x00
- *			 Available model: SLM,AMT,GLM
+ *			 Available model: SLM,AMT,GLM,CNL
  *			 Scope: Core (each processor core has a MSR)
  *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *			       perf code: 0x01
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
+						CNL
  *			       Scope: Core
  *	MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
  *			       perf code: 0x02
- *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- *						SKL,KNL,GLM
+ *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
+ *						SKL,KNL,GLM,CNL
  *			       Scope: Core
  *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *			       perf code: 0x03
- *			       Available model: SNB,IVB,HSW,BDW,SKL
+ *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL
  *			       Scope: Core
  *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  *			       perf code: 0x00
- *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
+ *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  *			       perf code: 0x01
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
- *						GLM
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
+ *						GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  *			       perf code: 0x02
  *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- *						SKL,KNL,GLM
+ *						SKL,KNL,GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  *			       perf code: 0x03
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.
  *			       perf code: 0x04
- *			       Available model: HSW ULT only
+ *			       Available model: HSW ULT,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.
  *			       perf code: 0x05
- *			       Available model: HSW ULT only
+ *			       Available model: HSW ULT,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  *			       perf code: 0x06
- *			       Available model: HSW ULT, GLM
+ *			       Available model: HSW ULT,GLM,CNL
  *			       Scope: Package (physical package)
  *
  */

@@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = {
 				  BIT(PERF_CSTATE_PKG_C10_RES),
 };
 
+static const struct cstate_model cnl_cstates __initconst = {
+	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |
+				  BIT(PERF_CSTATE_CORE_C3_RES) |
+				  BIT(PERF_CSTATE_CORE_C6_RES) |
+				  BIT(PERF_CSTATE_CORE_C7_RES),
+
+	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |
+				  BIT(PERF_CSTATE_PKG_C3_RES) |
+				  BIT(PERF_CSTATE_PKG_C6_RES) |
+				  BIT(PERF_CSTATE_PKG_C7_RES) |
+				  BIT(PERF_CSTATE_PKG_C8_RES) |
+				  BIT(PERF_CSTATE_PKG_C9_RES) |
+				  BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
 static const struct cstate_model slm_cstates __initconst = {
 	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |
 				  BIT(PERF_CSTATE_CORE_C6_RES),

@@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
 
+	X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
+
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),

Signature · 1 line

2.13.5

Benson Leung

Reviewed-by on v1 3/3

2018-03-19 23:09 UTC #6 lore raw

Re: [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake

Hi Harry,

Quoted 7 lines · Harry Pan

Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10 state residency counters, this patch enables those counters.
The MSR information is based on Intel Software Developers' Manual, Vol. 4, Order No. 335592.
Signed-off-by Harry Pan <[email protected]>

Reviewed-by Benson Leung <[email protected]>

Quoted 97 lines

---
 arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++-------------
 1 file changed, 31 insertions(+), 13 deletions(-)

arch/x86/events/intel/cstate.c +29 ~~-13~~

index 72db0664a53d..9aca448bb8e6 100644
@@ -40,50 +40,51 @@
  * Model specific counters:
  *	MSR_CORE_C1_RES: CORE C1 Residency Counter
  *			 perf code: 0x00
- *			 Available model: SLM,AMT,GLM
+ *			 Available model: SLM,AMT,GLM,CNL
  *			 Scope: Core (each processor core has a MSR)
  *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *			       perf code: 0x01
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
+						CNL
  *			       Scope: Core
  *	MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
  *			       perf code: 0x02
- *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- *						SKL,KNL,GLM
+ *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
+ *						SKL,KNL,GLM,CNL
  *			       Scope: Core
  *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *			       perf code: 0x03
- *			       Available model: SNB,IVB,HSW,BDW,SKL
+ *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL
  *			       Scope: Core
  *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  *			       perf code: 0x00
- *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
+ *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  *			       perf code: 0x01
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
- *						GLM
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
+ *						GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  *			       perf code: 0x02
  *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- *						SKL,KNL,GLM
+ *						SKL,KNL,GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  *			       perf code: 0x03
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.
  *			       perf code: 0x04
- *			       Available model: HSW ULT only
+ *			       Available model: HSW ULT,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.
  *			       perf code: 0x05
- *			       Available model: HSW ULT only
+ *			       Available model: HSW ULT,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  *			       perf code: 0x06
- *			       Available model: HSW ULT, GLM
+ *			       Available model: HSW ULT,GLM,CNL
  *			       Scope: Package (physical package)
  *
  */

@@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = {
 				  BIT(PERF_CSTATE_PKG_C10_RES),
 };
 
+static const struct cstate_model cnl_cstates __initconst = {
+	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |
+				  BIT(PERF_CSTATE_CORE_C3_RES) |
+				  BIT(PERF_CSTATE_CORE_C6_RES) |
+				  BIT(PERF_CSTATE_CORE_C7_RES),
+
+	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |
+				  BIT(PERF_CSTATE_PKG_C3_RES) |
+				  BIT(PERF_CSTATE_PKG_C6_RES) |
+				  BIT(PERF_CSTATE_PKG_C7_RES) |
+				  BIT(PERF_CSTATE_PKG_C8_RES) |
+				  BIT(PERF_CSTATE_PKG_C9_RES) |
+				  BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
 static const struct cstate_model slm_cstates __initconst = {
 	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |
 				  BIT(PERF_CSTATE_CORE_C6_RES),

arch/x86/events/intel/cstate.c static const struct x86_cpu_id intel_cstates_match[] __initconst = { · line 580

Quoted 8 lines

arch/x86/events/intel/cstate.c +2 -0

@@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
 
+	X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
+
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),

Thank you!

Signature · 7 lines

Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

Puthikorn Voravootivat

Tested-by

2018-03-19 23:13 UTC #7 lore raw

Re: [PATCH 3/3] perf/x86/intel: Enable C-state residency events for Cannon Lake

Quoted 6 lines · Benson Leung

Hi Harry,
Quoted 3 lines · Harry Pan
Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10 state residency counters, this patch enables those counters.

Quoted 6 lines

Quoted 4 lines
The MSR information is based on Intel Software Developers' Manual, Vol. 4, Order No. 335592.
Signed-off-by Harry Pan <[email protected]>
Reviewed-by Benson Leung <[email protected]>

Tested-by Puthikorn Voravootivat <[email protected]>

Quoted 2 lines

---
 arch/x86/events/intel/cstate.c | 44

+++++++++++++++++++++++++++++-------------

Quoted 3 lines

Review
Quoted 3 lines
 1 file changed, 31 insertions(+), 13 deletions(-)
(quoted diff) +0 -0

b/arch/x86/events/intel/cstate.c

Quoted 5 lines

Quoted 5 lines
index 72db0664a53d..9aca448bb8e6 100644
arch/x86/events/intel/cstate.c +0 -0
@@ -40,50 +40,51 @@
  * Model specific counters:

Quoted 8 lines

arch/x86/events/intel/cstate.c

Quoted 8 lines

arch/x86/events/intel/cstate.c +1 -2

  *   MSR_CORE_C1_RES: CORE C1 Residency Counter
  *                    perf code: 0x00
- *                    Available model: SLM,AMT,GLM
+ *                    Available model: SLM,AMT,GLM,CNL
  *                    Scope: Core (each processor core has a MSR)
  *   MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *                          perf code: 0x01
- *                          Available model:

NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM

Quoted 1 line

arch/x86/events/intel/cstate.c line 47
Quoted 1 line
arch/x86/events/intel/cstate.c +1 -0
+ *                          Available model:

NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,

Quoted 5 lines

arch/x86/events/intel/cstate.c

Quoted 5 lines

arch/x86/events/intel/cstate.c +1 -1

+                                             CNL
  *                          Scope: Core
  *   MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
  *                          perf code: 0x02
- *                          Available model:

SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW

Quoted 2 lines

arch/x86/events/intel/cstate.c line 52
Quoted 2 lines
arch/x86/events/intel/cstate.c +1 -1
- *                                           SKL,KNL,GLM
+ *                          Available model:

SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

Quoted 10 lines

arch/x86/events/intel/cstate.c

Quoted 10 lines

arch/x86/events/intel/cstate.c +2 -2

+ *                                           SKL,KNL,GLM,CNL
  *                          Scope: Core
  *   MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *                          perf code: 0x03
- *                          Available model: SNB,IVB,HSW,BDW,SKL
+ *                          Available model: SNB,IVB,HSW,BDW,SKL,CNL
  *                          Scope: Core
  *   MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  *                          perf code: 0x00
- *                          Available model:

SNB,IVB,HSW,BDW,SKL,KNL,GLM

Quoted 1 line

arch/x86/events/intel/cstate.c line 61
Quoted 1 line
arch/x86/events/intel/cstate.c +1 -0
+ *                          Available model:

SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL

Quoted 4 lines

arch/x86/events/intel/cstate.c

Quoted 4 lines

arch/x86/events/intel/cstate.c +0 -1

  *                          Scope: Package (physical package)
  *   MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  *                          perf code: 0x01
- *                          Available model:

NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL

Quoted 2 lines

arch/x86/events/intel/cstate.c line 65
Quoted 2 lines
arch/x86/events/intel/cstate.c +1 -1
- *                                           GLM
+ *                          Available model:

NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,

Quoted 5 lines

arch/x86/events/intel/cstate.c

Quoted 5 lines

arch/x86/events/intel/cstate.c +1 -0

+ *                                           GLM,CNL
  *                          Scope: Package (physical package)
  *   MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  *                          perf code: 0x02
  *                          Available model:

SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW

Quoted 6 lines

arch/x86/events/intel/cstate.c

Quoted 6 lines

arch/x86/events/intel/cstate.c +1 -2

- *                                           SKL,KNL,GLM
+ *                                           SKL,KNL,GLM,CNL
  *                          Scope: Package (physical package)
  *   MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  *                          perf code: 0x03
- *                          Available model:

NHM,WSM,SNB,IVB,HSW,BDW,SKL

Quoted 1 line

arch/x86/events/intel/cstate.c line 75
Quoted 1 line
arch/x86/events/intel/cstate.c +1 -0
+ *                          Available model:

NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL

Quoted 11 lines

arch/x86/events/intel/cstate.c +2 -2

  *                          Scope: Package (physical package)
  *   MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.
  *                          perf code: 0x04
- *                          Available model: HSW ULT only
+ *                          Available model: HSW ULT,CNL
  *                          Scope: Package (physical package)
  *   MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.
  *                          perf code: 0x05
- *                          Available model: HSW ULT only
+ *                          Available model: HSW ULT,CNL
  *                          Scope: Package (physical package)

Quoted 8 lines

arch/x86/events/intel/cstate.c static const struct cstate_model hswult_cstates

Quoted 8 lines

arch/x86/events/intel/cstate.c +1 -1

  *   MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  *                          perf code: 0x06
- *                          Available model: HSW ULT, GLM
+ *                          Available model: HSW ULT,GLM,CNL
  *                          Scope: Package (physical package)
  *
  */

@@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates

__initconst = {

Quoted 14 lines

arch/x86/events/intel/cstate.c +11 -0

                                BIT(PERF_CSTATE_PKG_C10_RES),
 };
 
+static const struct cstate_model cnl_cstates __initconst = {
+     .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
+                               BIT(PERF_CSTATE_CORE_C3_RES) |
+                               BIT(PERF_CSTATE_CORE_C6_RES) |
+                               BIT(PERF_CSTATE_CORE_C7_RES),
+
+     .pkg_events             = BIT(PERF_CSTATE_PKG_C2_RES) |
+                               BIT(PERF_CSTATE_PKG_C3_RES) |
+                               BIT(PERF_CSTATE_PKG_C6_RES) |
+                               BIT(PERF_CSTATE_PKG_C7_RES) |
+                               BIT(PERF_CSTATE_PKG_C8_RES) |

Quoted 8 lines

arch/x86/events/intel/cstate.c static const struct x86_cpu_id

Quoted 8 lines

arch/x86/events/intel/cstate.c +4 -0

+                               BIT(PERF_CSTATE_PKG_C9_RES) |
+                               BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
 static const struct cstate_model slm_cstates __initconst = {
      .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
                                BIT(PERF_CSTATE_CORE_C6_RES),

@@ -557,6 +573,8 @@ static const struct x86_cpu_id

intel_cstates_match[] __initconst = {

Quoted 19 lines

arch/x86/events/intel/cstate.c static const struct x86_cpu_id intel_cstates_match[] __initconst = { · line 580
Quoted 9 lines
arch/x86/events/intel/cstate.c +2 -0
      X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  snb_cstates),
      X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
 
+     X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
+
      X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
      X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
 
Thank you!
--
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

tip-bot for Harry Pan

merge bot

2018-03-31 10:20 UTC #8 lore raw

[tip:perf/core] perf/x86/intel: Enable C-state residency events for Cannon Lake

In reply to Harry Pan

perf/x86/intel: Enable C-state residency events for Cannon Lake

Commit-ID:  1159e09476536250c2a0173d4298d15114df7a89
Gitweb:     https://git.kernel.org/tip/1159e09476536250c2a0173d4298d15114df7a89
Author:     Harry Pan <[email protected]>
AuthorDate: Fri, 9 Mar 2018 20:15:48 +0800
Committer:  Ingo Molnar <[email protected]>
CommitDate: Sat, 31 Mar 2018 11:28:36 +0200

perf/x86/intel: Enable C-state residency events for Cannon Lake

Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10 state residency counters, this patch enables those counters.

( The MSR information is based on Intel Software Developers' Manual,
Vol. 4, Order No. 335592. )

Tested-by Puthikorn Voravootivat <[email protected]>

Signed-off-by Harry Pan <[email protected]>

Reviewed-by Benson Leung <[email protected]>

Cc Alexander Shishkin <[email protected]>

Cc Arnaldo Carvalho de Melo <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc [email protected]

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Stephane Eranian <[email protected]>

Cc Thomas Gleixner <[email protected]>

Cc Vince Weaver <[email protected]>

Cc [email protected]

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/events/intel/cstate.c | 44 +++++++++++++++++++++++++++++-------------
 1 file changed, 31 insertions(+), 13 deletions(-)

arch/x86/events/intel/cstate.c +31 ~~-13~~

index 72db0664a53d..9aca448bb8e6 100644
@@ -40,50 +40,51 @@
  * Model specific counters:
  *	MSR_CORE_C1_RES: CORE C1 Residency Counter
  *			 perf code: 0x00
- *			 Available model: SLM,AMT,GLM
+ *			 Available model: SLM,AMT,GLM,CNL
  *			 Scope: Core (each processor core has a MSR)
  *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *			       perf code: 0x01
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
+						CNL
  *			       Scope: Core
  *	MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
  *			       perf code: 0x02
- *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- *						SKL,KNL,GLM
+ *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
+ *						SKL,KNL,GLM,CNL
  *			       Scope: Core
  *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *			       perf code: 0x03
- *			       Available model: SNB,IVB,HSW,BDW,SKL
+ *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL
  *			       Scope: Core
  *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  *			       perf code: 0x00
- *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
+ *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  *			       perf code: 0x01
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
- *						GLM
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
+ *						GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
  *			       perf code: 0x02
  *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- *						SKL,KNL,GLM
+ *						SKL,KNL,GLM,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  *			       perf code: 0x03
- *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
+ *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.
  *			       perf code: 0x04
- *			       Available model: HSW ULT only
+ *			       Available model: HSW ULT,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.
  *			       perf code: 0x05
- *			       Available model: HSW ULT only
+ *			       Available model: HSW ULT,CNL
  *			       Scope: Package (physical package)
  *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  *			       perf code: 0x06
- *			       Available model: HSW ULT, GLM
+ *			       Available model: HSW ULT,GLM,CNL
  *			       Scope: Package (physical package)
  *
  */

@@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = {
 				  BIT(PERF_CSTATE_PKG_C10_RES),
 };
 
+static const struct cstate_model cnl_cstates __initconst = {
+	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |
+				  BIT(PERF_CSTATE_CORE_C3_RES) |
+				  BIT(PERF_CSTATE_CORE_C6_RES) |
+				  BIT(PERF_CSTATE_CORE_C7_RES),
+
+	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |
+				  BIT(PERF_CSTATE_PKG_C3_RES) |
+				  BIT(PERF_CSTATE_PKG_C6_RES) |
+				  BIT(PERF_CSTATE_PKG_C7_RES) |
+				  BIT(PERF_CSTATE_PKG_C8_RES) |
+				  BIT(PERF_CSTATE_PKG_C9_RES) |
+				  BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
 static const struct cstate_model slm_cstates __initconst = {
 	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |
 				  BIT(PERF_CSTATE_CORE_C6_RES),

@@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  snb_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
 
+	X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
+
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
 	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),

Benson Leung

Reviewed-by on v1 1/3

2018-03-19 23:03 UTC #9 lore raw

In reply to Harry Pan

Hi Harry,

Quoted 4 lines · Harry Pan

Cannon Lake microarchitecture is similar to Kaby Lake in terms of RAPL, this patch enables CNL RAPL support.
Signed-off-by Harry Pan <[email protected]>

Reviewed-by Benson Leung <[email protected]>

Quoted 10 lines

---
 drivers/powercap/intel_rapl.c | 1 +
 1 file changed, 1 insertion(+)

drivers/powercap/intel_rapl.c +0 -0

index 35636e1d8a3d..295d8dcba48c 100644

drivers/powercap/intel_rapl.c static const struct x86_cpu_id rapl_ids[] __initconst = { · line 1168

Quoted 7 lines

drivers/powercap/intel_rapl.c +1 -0

@@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
 	RAPL_CPU(INTEL_FAM6_SKYLAKE_X,		rapl_defaults_hsw_server),
 	RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE,	rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE,	rapl_defaults_core),
 
 	RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1,	rapl_defaults_byt),
 	RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT,	rapl_defaults_cht),

Thanks!

Signature · 7 lines

Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

Benson Leung

2018-03-19 23:14 UTC #10 lore raw

In reply to Harry Pan

[email protected]

Quoted 21 lines · Harry Pan

Cannon Lake microarchitecture is similar to Kaby Lake in terms of RAPL, this patch enables CNL RAPL support.

Signed-off-by Harry Pan <[email protected]>

---
 drivers/powercap/intel_rapl.c | 1 +
 1 file changed, 1 insertion(+)

drivers/powercap/intel_rapl.c +1 -0

index 35636e1d8a3d..295d8dcba48c 100644
@@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
 	RAPL_CPU(INTEL_FAM6_SKYLAKE_X,		rapl_defaults_hsw_server),
 	RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE,	rapl_defaults_core),
 	RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP,	rapl_defaults_core),
+	RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE,	rapl_defaults_core),
 
 	RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1,	rapl_defaults_byt),
 	RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT,	rapl_defaults_cht),

Signature · 7 lines

Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

Puthikorn Voravootivat

Tested-by

2018-03-19 23:19 UTC #11 lore raw

Quoted 7 lines · Benson Leung

[email protected]
Quoted 4 lines · Harry Pan
Cannon Lake microarchitecture is similar to Kaby Lake in terms of RAPL, this patch enables CNL RAPL support.
Signed-off-by Harry Pan <[email protected]>

Tested-by Puthikorn Voravootivat <[email protected]>

Quoted 5 lines

Review
Quoted 5 lines
---
 drivers/powercap/intel_rapl.c | 1 +
 1 file changed, 1 insertion(+)
(quoted diff) +0 -0

b/drivers/powercap/intel_rapl.c

Quoted 4 lines

drivers/powercap/intel_rapl.c static const struct x86_cpu_id rapl_ids[]
Quoted 4 lines
index 35636e1d8a3d..295d8dcba48c 100644
drivers/powercap/intel_rapl.c +0 -0
@@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[]

__initconst = {

Quoted 17 lines

drivers/powercap/intel_rapl.c static const struct x86_cpu_id rapl_ids[] __initconst = { · line 1168
Quoted 8 lines
drivers/powercap/intel_rapl.c +1 -0
      RAPL_CPU(INTEL_FAM6_SKYLAKE_X,          rapl_defaults_hsw_server),
      RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE,    rapl_defaults_core),
      RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP,   rapl_defaults_core),
+     RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE,  rapl_defaults_core),
 
      RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1,   rapl_defaults_byt),
      RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT,       rapl_defaults_cht),
--
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
[email protected]
Chromium OS Project
[email protected]

Rafael J. Wysocki

maintainer

2018-03-20 09:58 UTC #12 lore raw

In reply to Harry Pan

Quoted 4 lines · Harry Pan

Cannon Lake microarchitecture is similar to Kaby Lake in terms of RAPL, this patch enables CNL RAPL support.
Signed-off-by Harry Pan <[email protected]>

I have applied an analogous patch from Joe Konno that was posted earlier.

Thanks!

Quoted 19 lines

---
 drivers/powercap/intel_rapl.c | 1 +
 1 file changed, 1 insertion(+)

drivers/powercap/intel_rapl.c +1 -1

index 35636e1d8a3d..295d8dcba48c 100644
@@ -1162,6 +1162,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
        RAPL_CPU(INTEL_FAM6_SKYLAKE_X,          rapl_defaults_hsw_server),
        RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE,    rapl_defaults_core),
        RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP,   rapl_defaults_core),
+       RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE,  rapl_defaults_core),
 
        RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1,   rapl_defaults_byt),
        RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT,       rapl_defaults_cht),
--

2.13.5