perf/core improvements and fixes
Subsystems (3)
Arnaldo Carvalho de Melo
maintainerHi Ingo,
Please consider pulling,
- Arnaldo
Test results at the end of this message, as usual.
The following changes since commit 33801b94741d6c3be9713c10aa627477216c21e2:
perf/core: Fix installing cgroup events on CPU (2018-03-12 15:28:51 +0100)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.17-20180313
for you to fetch changes up to 1b442ed71f0b32d07db03efba150d4592875f988:
perf test: Fix exit code for record+probe_libc_inet_pton.sh (2018-03-12 15:25:20 -0300)
----------------------------------------------------------------
perf/core improvements and fixes:
- Add support for pmu events vendor subdirectories, move vendor event files (JSON format) to "arm" and "cavium" subdirectories (John Garry)
- Enable ThunderX2 B0 events in the "cavium" vendor event files (Ganapatrao Kulkarni)
- Show zero counters as well in 'perf report --stat' (Ingo Molnar)
- Record physical addresses in samples in 'perf c2c record', so that the NUMA node can be displayed for cacheline addresses (Jiri Olsa)
- Fix kernel MMAP name setup when --vmlinux is used (Jiri Olsa)
- Display llvm eBPF compiling command in debug output (Jiri Olsa)
- Add libdw DWARF post unwind support for ARM64 (Jean Pihet, Kim Phillips)
- Unwind with libdw doesn't take symfs into account (Martin Vuille)
- Fix exit code for record+probe_libc_inet_pton.sh 'perf test' entry (Sandipan Das)
- Fix code dump when using transaction events with 'perf stat -T' (Thomas Richter)
- Do not call perf_dafault_config() twice in 'perf record' (Yisheng Xie)
- Fix top.call-graph config variable processing in 'perf top' (Yisheng Xie)
----------------------------------------------------------------
Ganapatrao Kulkarni (1):
perf vendor events arm64: Enable JSON events for ThunderX2 B0
Ingo Molnar (1):
perf report: Show zero counters as well in 'perf report --stat'
Jiri Olsa (11):
perf env: Free memory nodes data
perf tools: Add mem2node object
perf tests: Add mem2node object test
perf c2c record: Record physical addresses in samples perf c2c report: Make calc_width work with struct c2c_hist_entry perf c2c report: Call calc_width() only for displayed entries perf c2c report: Display node for cacheline address perf c2c report: Add span header over cacheline data perf c2c report: Add cacheline address count column perf llvm: Display eBPF compiling command in debug output perf machine: Fix mmap name setup
John Garry (11):
perf vendor events: Drop incomplete multiple mapfile support perf vendor events: Fix error code in json_events()
perf vendor events: Drop support for unused topic directories perf vendor events: Add support for pmu events vendor subdirectory perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory perf vendor events: Add support for arch standard events perf vendor events arm64: Add armv8-recommended.json
perf vendor events arm64: Fixup ThunderX2 to use recommended events perf vendor events arm64: fixup A53 to use recommended events perf vendor events arm64: add HiSilicon hip08 JSON file
Kim Phillips (1):
perf tools arm64: Add libdw DWARF post unwind support for ARM64
Martin Vuille (1):
perf unwind: Unwind with libdw doesn't take symfs into account
Sandipan Das (1):
perf test: Fix exit code for record+probe_libc_inet_pton.sh
Thomas Richter (2):
perf stat: Fix core dump when flag T is used perf stat: Make function perf_stat_evsel_id_init static
Yisheng Xie (2):
perf record: Avoid duplicate call of perf_default_config() perf top: Fix top.call-graph config option reading
tools/perf/Documentation/perf-c2c.txt | 2 +-
tools/perf/Makefile.config | 2 +-
tools/perf/arch/arm64/include/arch-tests.h | 12 +
tools/perf/arch/arm64/tests/Build | 2 +
tools/perf/arch/arm64/tests/arch-tests.c | 16 +
tools/perf/arch/arm64/util/Build | 1 +
tools/perf/arch/arm64/util/unwind-libdw.c | 60 +++
tools/perf/builtin-c2c.c | 223 +++++++++-
tools/perf/builtin-record.c | 8 +-
tools/perf/builtin-stat.c | 9 +-
tools/perf/builtin-top.c | 6 +-
tools/perf/pmu-events/Build | 2 +
tools/perf/pmu-events/README | 15 +-
.../arch/arm64/{ => arm}/cortex-a53/branch.json | 14 +-
.../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 8 +
.../arch/arm64/arm/cortex-a53/cache.json | 27 ++
.../arch/arm64/{ => arm}/cortex-a53/memory.json | 14 +-
.../arch/arm64/arm/cortex-a53/other.json | 28 ++
.../arch/arm64/{ => arm}/cortex-a53/pipeline.json | 20 +-
.../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++
.../arch/arm64/cavium/thunderx2-imp-def.json | 62 ---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 32 ++
.../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 -
.../pmu-events/arch/arm64/cortex-a53/cache.json | 27 --
.../pmu-events/arch/arm64/cortex-a53/other.json | 32 --
.../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 ++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 6 +-
tools/perf/pmu-events/jevents.c | 288 ++++++++++---
tools/perf/tests/Build | 1 +
tools/perf/tests/builtin-test.c | 4 +
tools/perf/tests/mem2node.c | 75 ++++
.../tests/shell/record+probe_libc_inet_pton.sh | 5 +-
tools/perf/tests/tests.h | 1 +
tools/perf/ui/stdio/hist.c | 6 +-
tools/perf/util/Build | 1 +
tools/perf/util/env.c | 4 +
tools/perf/util/llvm-utils.c | 14 +
tools/perf/util/machine.c | 28 +-
tools/perf/util/mem2node.c | 134 ++++++
tools/perf/util/mem2node.h | 19 +
tools/perf/util/stat.c | 2 +-
tools/perf/util/stat.h | 2 -
tools/perf/util/unwind-libdw.c | 2 +-
43 files changed, 1533 insertions(+), 277 deletions(-)
create mode 100644 tools/perf/arch/arm64/include/arch-tests.h
create mode 100644 tools/perf/arch/arm64/tests/arch-tests.c
create mode 100644 tools/perf/arch/arm64/util/unwind-libdw.c
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json (76%)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json (50%)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json (97%)
create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
delete mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
create mode 100644 tools/perf/tests/mem2node.c
create mode 100644 tools/perf/util/mem2node.c
create mode 100644 tools/perf/util/mem2node.hTest results:
The first ones are container (docker) based builds of tools/perf with and without libelf support. Where clang is available, it is also used to build perf with/without libelf.
The objtool and samples/bpf/ builds are disabled now that I'm switching from using the sources in a local volume to fetching them from a http server to build it inside the container, to make it easier to build in a container cluster. Those will come back later.
Several are cross builds, the ones with -x-ARCH and the android one, and those may not have all the features built, due to lack of multi-arch devel packages, available and being used so far on just a few, like debian:experimental-x-{arm64,mipsel}.
The 'perf test' one will perform a variety of tests exercising tools/perf/util/, tools/lib/{bpf,traceevent,etc}, as well as run perf commands with a variety of command line event specifications to then intercept the sys_perf_event syscall to check that the perf_event_attr fields are set up as expected, among a variety of other unit tests.
Then there is the 'make -C tools/perf build-test' ones, that build tools/perf/ with a variety of feature sets, exercising the build with an incomplete set of features as well as with a complete one. It is planned to have it run on each of the containers mentioned above, using some container orchestration infrastructure. Get in contact if interested in helping having this in place.
# dm 1 alpine:3.4 : Ok gcc (Alpine 5.3.0) 5.3.0 2 alpine:3.5 : Ok gcc (Alpine 6.2.1) 6.2.1 20160822 3 alpine:3.6 : Ok gcc (Alpine 6.3.0) 6.3.0 4 alpine:3.7 : Ok gcc (Alpine 6.4.0) 6.4.0 5 alpine:edge : Ok gcc (Alpine 6.4.0) 6.4.0 6 amazonlinux:1 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-11) 7 amazonlinux:2 : Ok gcc (GCC) 7.2.1 20170915 (Red Hat 7.2.1-2) 8 android-ndk:r12b-arm : Ok arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease) 9 android-ndk:r15c-arm : Ok arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease) 10 centos:5 : Ok gcc (GCC) 4.1.2 20080704 (Red Hat 4.1.2-55) 11 centos:6 : Ok gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18) 12 centos:7 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16) 13 debian:7 : Ok gcc (Debian 4.7.2-5) 4.7.2 14 debian:8 : Ok gcc (Debian 4.9.2-10+deb8u1) 4.9.2 15 debian:9 : Ok gcc (Debian 6.3.0-18) 6.3.0 20170516 16 debian:experimental : Ok gcc (Debian 7.2.0-17) 7.2.1 20171205 17 debian:experimental-x-arm64 : Ok aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 18 debian:experimental-x-mips : Ok mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 19 debian:experimental-x-mips64 : Ok mips64-linux-gnuabi64-gcc (Debian 7.2.0-11) 7.2.0 20 debian:experimental-x-mipsel : Ok mipsel-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 21 fedora:20 : Ok gcc (GCC) 4.8.3 20140911 (Red Hat 4.8.3-7) 22 fedora:21 : Ok gcc (GCC) 4.9.2 20150212 (Red Hat 4.9.2-6) 23 fedora:22 : Ok gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6) 24 fedora:23 : Ok gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6) 25 fedora:24 : Ok gcc (GCC) 6.3.1 20161221 (Red Hat 6.3.1-1) 26 fedora:24-x-ARC-uClibc : Ok arc-linux-gcc (ARCompact ISA Linux uClibc toolchain 2017.09-rc2) 7.1.1 20170710 27 fedora:25 : Ok gcc (GCC) 6.4.1 20170727 (Red Hat 6.4.1-1) 28 fedora:26 : Ok gcc (GCC) 7.2.1 20170915 (Red Hat 7.2.1-2) 29 fedora:27 : Ok gcc (GCC) 7.3.1 20180303 (Red Hat 7.3.1-5) 30 fedora:rawhide : Ok gcc (GCC) 7.2.1 20170829 (Red Hat 7.2.1-1) 31 gentoo-stage3-amd64:latest : Ok gcc (Gentoo 6.4.0-r1 p1.3) 6.4.0 32 mageia:5 : Ok gcc (GCC) 4.9.2 33 mageia:6 : Ok gcc (Mageia 5.4.0-5.mga6) 5.4.0 34 opensuse:42.1 : Ok gcc (SUSE Linux) 4.8.5 35 opensuse:42.2 : Ok gcc (SUSE Linux) 4.8.5 36 opensuse:42.3 : Ok gcc (SUSE Linux) 4.8.5 37 opensuse:tumbleweed : Ok gcc (SUSE Linux) 7.3.0 38 oraclelinux:6 : Ok gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18) 39 oraclelinux:7 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16) 40 ubuntu:12.04.5 : Ok gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3 41 ubuntu:14.04.4 : Ok gcc (Ubuntu 4.8.4-2ubuntu1~14.04.3) 4.8.4 42 ubuntu:14.04.4-x-linaro-arm64 : Ok aarch64-linux-gnu-gcc (Linaro GCC 5.4-2017.05) 5.4.1 20170404 43 ubuntu:15.04 : Ok gcc (Ubuntu 4.9.2-10ubuntu13) 4.9.2 44 ubuntu:16.04 : Ok gcc (Ubuntu 5.4.0-6ubuntu1~16.04.5) 5.4.0 20160609 45 ubuntu:16.04-x-arm : Ok arm-linux-gnueabihf-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609 46 ubuntu:16.04-x-arm64 : Ok aarch64-linux-gnu-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609 47 ubuntu:16.04-x-powerpc : Ok powerpc-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609 48 ubuntu:16.04-x-powerpc64 : Ok powerpc64-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.1) 5.4.0 20160609 49 ubuntu:16.04-x-powerpc64el : Ok powerpc64le-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609 50 ubuntu:16.04-x-s390 : Ok s390x-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609 51 ubuntu:16.10 : Ok gcc (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 52 ubuntu:17.04 : Ok gcc (Ubuntu 6.3.0-12ubuntu2) 6.3.0 20170406 53 ubuntu:17.10 : Ok gcc (Ubuntu 7.2.0-8ubuntu3) 7.2.0 54 ubuntu:18.04 : Ok gcc (Ubuntu 7.2.0-16ubuntu1) 7.2.0
# uname -a Linux jouet 4.16.0-rc4 #1 SMP Mon Mar 5 12:18:05 -03 2018 x86_64 x86_64 x86_64 GNU/Linux # perf test 1: vmlinux symtab matches kallsyms : Ok 2: Detect openat syscall event : Ok 3: Detect openat syscall event on all cpus : Ok 4: Read samples using the mmap interface : Ok 5: Test data source output : Ok 6: Parse event definition strings : Ok 7: Simple expression parser : Ok 8: PERF_RECORD_* events & perf_sample fields : Ok 9: Parse perf pmu format : Ok 10: DSO data read : Ok 11: DSO data cache : Ok 12: DSO data reopen : Ok 13: Roundtrip evsel->name : Ok 14: Parse sched tracepoints fields : Ok 15: syscalls:sys_enter_openat event fields : Ok 16: Setup struct perf_event_attr : Ok 17: Match and link multiple hists : Ok 18: 'import perf' in python : Ok 19: Breakpoint overflow signal handler : Ok 20: Breakpoint overflow sampling : Ok 21: Number of exit events of a simple workload : Ok 22: Software clock events period values : Ok 23: Object code reading : Ok 24: Sample parsing : Ok 25: Use a dummy software event to keep tracking : Ok 26: Parse with no sample_id_all bit set : Ok 27: Filter hist entries : Ok 28: Lookup mmap thread : Ok 29: Share thread mg : Ok 30: Sort output of hist entries : Ok 31: Cumulate child hist entries : Ok 32: Track with sched_switch : Ok 33: Filter fds with revents mask in a fdarray : Ok 34: Add fd to a fdarray, making it autogrow : Ok 35: kmod_path__parse : Ok 36: Thread map : Ok 37: LLVM search and compile : 37.1: Basic BPF llvm compile : Ok 37.2: kbuild searching : Ok 37.3: Compile source for BPF prologue generation : Ok 37.4: Compile source for BPF relocation : Ok 38: Session topology : Ok 39: BPF filter : 39.1: Basic BPF filtering : Ok 39.2: BPF pinning : Ok 39.3: BPF prologue generation : Ok 39.4: BPF relocation checker : Ok 40: Synthesize thread map : Ok 41: Remove thread map : Ok 42: Synthesize cpu map : Ok 43: Synthesize stat config : Ok 44: Synthesize stat : Ok 45: Synthesize stat round : Ok 46: Synthesize attr update : Ok 47: Event times : Ok 48: Read backward ring buffer : Ok 49: Print cpu map : Ok 50: Probe SDT events : Ok 51: is_printable_array : Ok 52: Print bitmap : Ok 53: perf hooks : Ok 54: builtin clang support : Skip (not compiled in) 55: unit_number__scnprintf : Ok 56: mem2node : Ok 57: x86 rdpmc : Ok 58: Convert perf time to TSC : Ok 59: DWARF unwind : Ok 60: x86 instruction decoder - new instructions : Ok 61: Use vfs_getname probe to get syscall args filenames : Ok 62: Check open filename arg using perf trace + vfs_getname: Ok 63: probe libc's inet_pton & backtrace it with ping : Ok 64: Add vfs_getname probe to get syscall args filenames : Ok #
$ make -C tools/perf build-test
make: Entering directory '/home/acme/git/perf/tools/perf'
- tarpkg: ./tests/perf-targz-src-pkg .
make_no_libperl_O: make NO_LIBPERL=1
make_no_newt_O: make NO_NEWT=1
make_debug_O: make DEBUG=1
make_with_clangllvm_O: make LIBCLANGLLVM=1
make_no_demangle_O: make NO_DEMANGLE=1
make_no_libelf_O: make NO_LIBELF=1
make_with_babeltrace_O: make LIBBABELTRACE=1
make_pure_O: make
make_no_libaudit_O: make NO_LIBAUDIT=1
make_no_libdw_dwarf_unwind_O: make NO_LIBDW_DWARF_UNWIND=1
make_no_ui_O: make NO_NEWT=1 NO_SLANG=1 NO_GTK2=1
make_perf_o_O: make perf.o
make_tags_O: make tags
make_no_libnuma_O: make NO_LIBNUMA=1
make_util_pmu_bison_o_O: make util/pmu-bison.o
make_install_prefix_O: make install prefix=/tmp/krava
make_no_libpython_O: make NO_LIBPYTHON=1
make_no_libunwind_O: make NO_LIBUNWIND=1
make_doc_O: make doc
make_minimal_O: make NO_LIBPERL=1 NO_LIBPYTHON=1 NO_NEWT=1 NO_GTK2=1 NO_DEMANGLE=1 NO_LIBELF=1 NO_LIBUNWIND=1 NO_BACKTRACE=1 NO_LIBNUMA=1 NO_LIBAUDIT=1 NO_LIBBIONIC=1 NO_LIBDW_DWARF_UNWIND=1 NO_AUXTRACE=1 NO_LIBBPF=1 NO_LIBCRYPTO=1 NO_SDT=1 NO_JVMTI=1
make_no_gtk2_O: make NO_GTK2=1
make_install_O: make install
make_install_bin_O: make install-bin
make_help_O: make help
make_static_O: make LDFLAGS=-static
make_no_auxtrace_O: make NO_AUXTRACE=1
make_no_backtrace_O: make NO_BACKTRACE=1
make_install_prefix_slash_O: make install prefix=/tmp/krava/
make_no_scripts_O: make NO_LIBPYTHON=1 NO_LIBPERL=1
make_no_slang_O: make NO_SLANG=1
make_util_map_o_O: make util/map.o
make_no_libbionic_O: make NO_LIBBIONIC=1
make_no_libbpf_O: make NO_LIBBPF=1
make_clean_all_O: make clean all
OK
make: Leaving directory '/home/acme/git/perf/tools/perf'
$ Arnaldo Carvalho de Melo
maintainerPATCH 1/31 perf env: Free memory nodes data
From: Jiri Olsa <[email protected]>
Forgot to free env's memory nodes, adding needed code to perf_env__exit.
--- tools/perf/util/env.c | 4 ++++ 1 file changed, 4 insertions(+)
tools/perf/util/env.c +4 -0
@@ -32,6 +32,10 @@ void perf_env__exit(struct perf_env *env)for (i =0 ; i < env->caches_cnt; i++)cpu_cache_level__free (&env->caches[i]);zfree (&env->caches); + +for (i =0 ; i < env->nr_memory_nodes; i++) +free (env->memory_nodes[i].set); +zfree (&env->memory_nodes); }int perf_env__set_cmdline (struct perf_env *env,int argc,const char *argv[])
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 2/31 perf tools: Add mem2node object
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
Adding mem2node object to allow the easy lookup of the node for the physical address.
It has following interface:
int mem2node__init(struct mem2node *map, struct perf_env *env); void mem2node__exit(struct mem2node *map); int mem2node__node(struct mem2node *map, u64 addr);
The mem2node__toolsinit initialize object from the perf data file MEM_TOPOLOGY feature data. Following calls to mem2node__node will return node number for given physical address. The mem2node__exit function frees the object.
--- tools/perf/util/Build | 1 + tools/perf/util/mem2node.c | 134 +++++++++++++++++++++++++++++++++++++++++++++ tools/perf/util/mem2node.h | 19 +++++++ 3 files changed, 154 insertions(+) create mode 100644 tools/perf/util/mem2node.c create mode 100644 tools/perf/util/mem2node.h
tools/perf/util/Build +1 -0
@@ -106,6 +106,7 @@ libperf-y += units.o libperf-y += time-utils.o libperf-y += expr-bison.o libperf-y += branch.o +libperf-y += mem2node.o libperf-$(CONFIG_LIBBPF) += bpf-loader.o libperf-$(CONFIG_BPF_PROLOGUE) += bpf-prologue.o
tools/perf/util/mem2node.c new file +134 -0
134 lines not on this page · raw message
tools/perf/util/mem2node.h new file +19 -0
@@ -0,0 +1,19 @@ +#ifndef __MEM2NODE_H +#define __MEM2NODE_H + +#include <linux/rbtree.h> +#include "env.h" + +struct phys_entry ; + +struct mem2node { +struct rb_root root; +struct phys_entry *entries; +int cnt; +}; + +int mem2node__init (struct mem2node *map,struct perf_env *env); +void mem2node__exit (struct mem2node *map); +int mem2node__node (struct mem2node *map,u64 addr); + +#endif /* __MEM2NODE_H */
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 3/31 perf tests: Add mem2node object test
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
Adding mem2node object automated test.
The test prepares few artificial nodes - memory maps and verifies the mem2node object returns proper node values to given addresses.
--- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test.c | 4 +++ tools/perf/tests/mem2node.c | 75 +++++++++++++++++++++++++++++++++++++++++ tools/perf/tests/tests.h | 1 + 4 files changed, 81 insertions(+) create mode 100644 tools/perf/tests/mem2node.c
tools/perf/tests/Build +1 -0
@@ -47,6 +47,7 @@ perf-y += bitmap.o perf-y += perf-hooks.o perf-y += clang.o perf-y += unit_number__scnprintf.o +perf-y += mem2node.o $(OUTPUT)tests/llvm-src-base.c: tests/bpf-script-example.c tests/Build $(call rule_mkdir)
tools/perf/tests/builtin-test.c +4 -0
@@ -270,6 +270,10 @@ static struct test generic_tests[] = { .desc = "unit_number__scnprintf", .func = test__unit_number__scnprint, }, + { + .desc = "mem2node", + .func = test__mem2node, + }, { .func = NULL, },
tools/perf/tests/mem2node.c new file +75 -0
75 lines not on this page · raw message
tools/perf/tests/tests.h +1 -0
@@ -102,6 +102,7 @@ int test__clang(struct test *test, int subtest);const char *test__clang_subtest_get_desc (int subtest);int test__clang_subtest_get_nr (void );int test__unit_number__scnprint (struct test *test,int subtest); +int test__mem2node (struct test *t,int subtest);bool test__bp_signal_is_supported (void );
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 4/31 perf c2c record: Record physical addresses in samples
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
We are going to display NUMA node information in following patches. For this we need to have physical address data in the sample.
Adding --phys-data as a default option for perf c2c record.
--- tools/perf/Documentation/perf-c2c.txt | 2 +- tools/perf/builtin-c2c.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)
tools/perf/Documentation/perf-c2c.txt +1 -1
@@ -116,7 +116,7 @@ and calls standard perf record command. Following perf record options are configured by default: (check perf record man page for details) - -W,-d,--sample-cpu + -W,-d,--phys-data,--sample-cpu Unless specified otherwise with '-e' option, following events are monitored by default:
tools/perf/builtin-c2c.c +2 -1
@@ -2704,7 +2704,7 @@ static int perf_c2c__record(int argc, const char **argv) argc =parse_options (argc, argv, options, record_mem_usage,PARSE_OPT_KEEP_UNKNOWN ); - rec_argc = argc +10 ;/* max number of arguments */ + rec_argc = argc +11 ;/* max number of arguments */ rec_argv =calloc (rec_argc +1 ,sizeof (char *));if (!rec_argv)return -1 ;
@@ -2720,6 +2720,7 @@ static int perf_c2c__record(int argc, const char **argv) rec_argv[i++] ="-W" ; rec_argv[i++] ="-d" ; + rec_argv[i++] ="--phys-data" ; rec_argv[i++] ="--sample-cpu" ;for (j =0 ; j <PERF_MEM_EVENTS__MAX ; j++) {
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 5/31 perf c2c report: Make calc_width work with struct c2c_hist_entry
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
We are going to calculate tje column width based on the struct c2c_hist_entry data, so making calc_width to work with struct c2c_hist_entry.
--- tools/perf/builtin-c2c.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
tools/perf/builtin-c2c.c +9 -5
@@ -1839,20 +1839,24 @@ static inline int valid_hitm_or_store(struct hist_entry *he)return has_hitm || c2c_he->stats.store; } -static void calc_width (struct hist_entry *he) +static void calc_width (struct c2c_hist_entry *c2c_he) {struct c2c_hists *c2c_hists; - c2c_hists = container_of(he->hists, struct c2c_hists, hists); -hists__calc_col_len (&c2c_hists->hists, he); + c2c_hists = container_of(c2c_he->he.hists, struct c2c_hists, hists); +hists__calc_col_len (&c2c_hists->hists, &c2c_he->he); }static int filter_cb (struct hist_entry *he) { +struct c2c_hist_entry *c2c_he; + + c2c_he = container_of(he, struct c2c_hist_entry, he); +if (c2c.show_src && !he->srcline) he->srcline =hist_entry__get_srcline (he); -calc_width (he); +calc_width (c2c_he);if (!valid_hitm_or_store (he)) he->filtered =HIST_FILTER__C2C ;
@@ -1869,7 +1873,7 @@ static int resort_cl_cb(struct hist_entry *he) c2c_he = container_of(he, struct c2c_hist_entry, he); c2c_hists = c2c_he->hists; -calc_width (he); +calc_width (c2c_he);if (display && c2c_hists) {static unsigned int idx;
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 6/31 perf c2c report: Call calc_width() only for displayed entries
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
There's no need to calculate column widths for entries that are not going to be displayed.
--- tools/perf/builtin-c2c.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
tools/perf/builtin-c2c.c +1 -2
@@ -1873,12 +1873,11 @@ static int resort_cl_cb(struct hist_entry *he) c2c_he = container_of(he, struct c2c_hist_entry, he); c2c_hists = c2c_he->hists; -calc_width (c2c_he); -if (display && c2c_hists) {static unsigned int idx; c2c_he->cacheline_idx = idx++; +calc_width (c2c_he);c2c_hists__reinit (c2c_hists, c2c.cl_output, c2c.cl_resort);
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 7/31 perf c2c report: Display node for cacheline address
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
Adding the NUMA node info for the data cacheline. Adding the new column to both "Shared Data Cache Line Table" and "Shared Cache Line Distribution Pareto".
Note the new 'Node' column next to the 'Cacheline'.
$ perf c2c report --stdio
=================================================
Shared Data Cache Line Table
=================================================
#
# Total Tot ----- LLC Load Hitm -----
# Index Cacheline Node records Hitm Total Lcl Rmt
# ..... .................. .... ....... ....... ....... ....... .......
#
0 0x7f0830100000 0 84 10.53% 8 8 0
1 0xffff922a93154200 0 3 2.63% 2 2 0
2 0xffff922a93154500 0 4 2.63% 2 2 0
...Note the new 'Node' column next to the 'Offset'.
=================================================
Shared Cache Line Distribution Pareto
=================================================
#
# ----- HITM ----- -- Store Refs -- Data address
# Num Rmt Lcl L1 Hit L1 Miss Offset Node Pid
# ..... ....... ....... ....... ....... .................. .... .......
#
-------------------------------------------------------------
0 0 8 32 2 0x7f0830100000
-------------------------------------------------------------
0.00% 75.00% 21.88% 0.00% 0x18 0 1791
0.00% 12.50% 37.50% 0.00% 0x18 0 1791
0.00% 0.00% 34.38% 0.00% 0x18 0 1791Using the mem2node object to get the NUMA node data.
--- tools/perf/builtin-c2c.c | 119 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 114 insertions(+), 5 deletions(-)
tools/perf/builtin-c2c.c +114 -5
@@ -32,6 +32,7 @@#include "evsel.h" #include "ui/browsers/hists.h" #include "thread.h" +#include "mem2node.h" struct c2c_hists {struct hists hists;
@@ -49,6 +50,7 @@ struct c2c_hist_entry {struct c2c_hists *hists;struct c2c_stats stats;unsigned long *cpuset; +unsigned long *nodeset;struct c2c_stats *node_stats;unsigned int cacheline_idx;
@@ -59,6 +61,11 @@ struct c2c_hist_entry {* because of its callchain dynamic entry */ struct hist_entry he; + +unsigned long paddr; +unsigned long paddr_cnt; +bool paddr_zero; +char *nodestr; };static char const *coalesce_default ="pid,iaddr" ;
@@ -66,6 +73,7 @@ static char const *coalesce_default = "pid,iaddr";struct perf_c2c {struct perf_tool tool;struct c2c_hists hists; +struct mem2node mem2node;unsigned long **nodes;int nodes_cnt;
@@ -123,6 +131,10 @@ static void *c2c_he_zalloc(size_t size)if (!c2c_he->cpuset)return NULL ; + c2c_he->nodeset =bitmap_alloc (c2c.nodes_cnt); +if (!c2c_he->nodeset) +return NULL ; + c2c_he->node_stats =zalloc (c2c.nodes_cnt *sizeof (*c2c_he->node_stats));if (!c2c_he->node_stats)return NULL ;
@@ -145,6 +157,8 @@ static void c2c_he_free(void *he) }free (c2c_he->cpuset); +free (c2c_he->nodeset); +free (c2c_he->nodestr);free (c2c_he->node_stats);free (c2c_he); }
@@ -194,6 +208,28 @@ static void c2c_he__set_cpu(struct c2c_hist_entry *c2c_he,set_bit (sample->cpu, c2c_he->cpuset); } +static void c2c_he__set_node (struct c2c_hist_entry *c2c_he, +struct perf_sample *sample) +{ +int node; + +if (!sample->phys_addr) { + c2c_he->paddr_zero = true; +return ; + } + + node =mem2node__node (&c2c.mem2node, sample->phys_addr); +if (WARN_ONCE (node <0 ,"WARNING: failed to find node\n" )) +return ; + +set_bit (node, c2c_he->nodeset); + +if (c2c_he->paddr != sample->phys_addr) { + c2c_he->paddr_cnt++; + c2c_he->paddr = sample->phys_addr; + } +} +static void compute_stats (struct c2c_hist_entry *c2c_he,struct c2c_stats *stats,u64 weight)
@@ -257,6 +293,7 @@ static int process_sample_event(struct perf_tool *tool __maybe_unused,c2c_add_stats (&c2c_hists->stats, &stats);c2c_he__set_cpu (c2c_he, sample); +c2c_he__set_node (c2c_he, sample);hists__inc_nr_samples (&c2c_hists->hists, he->filtered); ret =hist_entry__append_callchain (he, sample);
@@ -293,6 +330,7 @@ static int process_sample_event(struct perf_tool *tool __maybe_unused,compute_stats (c2c_he, &stats, sample->weight);c2c_he__set_cpu (c2c_he, sample); +c2c_he__set_node (c2c_he, sample);hists__inc_nr_samples (&c2c_hists->hists, he->filtered); ret =hist_entry__append_callchain (he, sample);
@@ -455,6 +493,20 @@ static int dcacheline_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,return scnprintf (hpp->buf, hpp->size,"%*s" , width,HEX_STR (buf, addr)); } +static int +dcacheline_node_entry (struct perf_hpp_fmt *fmt,struct perf_hpp *hpp, +struct hist_entry *he) +{ +struct c2c_hist_entry *c2c_he; +int width =c2c_width (fmt, hpp, he->hists); + + c2c_he = container_of(he, struct c2c_hist_entry, he); +if (WARN_ON_ONCE (!c2c_he->nodestr)) +return 0 ; + +return scnprintf (hpp->buf, hpp->size,"%*s" , width, c2c_he->nodestr); +} +static int offset_entry (struct perf_hpp_fmt *fmt,struct perf_hpp *hpp,struct hist_entry *he) {
@@ -1207,6 +1259,14 @@ static struct c2c_dimension dim_dcacheline = { .width = 18, }; +static struct c2c_dimension dim_dcacheline_node = { + .header =HEADER_LOW ("Node" ), + .name ="dcacheline_node" , + .cmp = empty_cmp, + .entry = dcacheline_node_entry, + .width =4 , +}; +static struct c2c_header header_offset_tui =HEADER_LOW ("Off" );static struct c2c_dimension dim_offset = {
@@ -1217,6 +1277,14 @@ static struct c2c_dimension dim_offset = { .width = 18, }; +static struct c2c_dimension dim_offset_node = { + .header =HEADER_LOW ("Node" ), + .name ="offset_node" , + .cmp = empty_cmp, + .entry = dcacheline_node_entry, + .width =4 , +}; +static struct c2c_dimension dim_iaddr = { .header =HEADER_LOW ("Code address" ), .name ="iaddr" ,
@@ -1536,7 +1604,9 @@ static struct c2c_dimension dim_dcacheline_num_empty = {static struct c2c_dimension *dimensions[] = { &dim_dcacheline, + &dim_dcacheline_node, &dim_offset, + &dim_offset_node, &dim_iaddr, &dim_tot_hitm, &dim_lcl_hitm,
@@ -1839,12 +1909,44 @@ static inline int valid_hitm_or_store(struct hist_entry *he)return has_hitm || c2c_he->stats.store; } +static void set_node_width (struct c2c_hist_entry *c2c_he,int len) +{ +struct c2c_dimension *dim; + + dim = &c2c.hists == c2c_he->hists ? + &dim_dcacheline_node : &dim_offset_node; + +if (len > dim->width) + dim->width = len; +} + +static int set_nodestr (struct c2c_hist_entry *c2c_he) +{ +char buf[30 ]; +int len; + +if (c2c_he->nodestr) +return 0 ; + +if (bitmap_weight (c2c_he->nodeset, c2c.nodes_cnt)) { + len =bitmap_scnprintf (c2c_he->nodeset, c2c.nodes_cnt, + buf,sizeof (buf)); + }else { + len =scnprintf (buf,sizeof (buf),"N/A" ); + } + +set_node_width (c2c_he, len); + c2c_he->nodestr =strdup (buf); +return c2c_he->nodestr ?0 : -ENOMEM ; +} +static void calc_width (struct c2c_hist_entry *c2c_he) {struct c2c_hists *c2c_hists; c2c_hists = container_of(c2c_he->he.hists, struct c2c_hists, hists);hists__calc_col_len (&c2c_hists->hists, &c2c_he->he); +set_nodestr (c2c_he); }static int filter_cb (struct hist_entry *he)
@@ -2474,7 +2576,7 @@ static int build_cl_output(char *cl_sort, bool no_source)"percent_lcl_hitm," "percent_stores_l1hit," "percent_stores_l1miss," -"offset," , +"offset,offset_node," , add_pid ?"pid," :"" , add_tid ?"tid," :"" , add_iaddr ? "iaddr," : "",
@@ -2603,17 +2705,21 @@ static int perf_c2c__report(int argc, const char **argv) goto out; } - err =setup_callchain (session->evlist); + err =mem2node__init (&c2c.mem2node, &session->header.env);if (err) goto out_session; + err =setup_callchain (session->evlist); +if (err) + goto out_mem2node; +if (symbol__init (&session->header.env) <0 ) - goto out_session; + goto out_mem2node;/* No pipe support at the moment. */ if (perf_data__is_pipe (session->data)) {pr_debug ("No pipe support at the moment.\n" ); - goto out_session; + goto out_mem2node; }if (c2c.use_stdio)
@@ -2626,12 +2732,13 @@ static int perf_c2c__report(int argc, const char **argv) err =perf_session__process_events (session);if (err) {pr_err ("failed to process sample\n" ); - goto out_session; + goto out_mem2node; }c2c_hists__reinit (&c2c.hists,"cl_idx," "dcacheline," +"dcacheline_node," "tot_recs," "percent_hitm," "tot_hitm,lcl_hitm,rmt_hitm,"
@@ -2657,6 +2764,8 @@ static int perf_c2c__report(int argc, const char **argv)perf_c2c_display (session); +out_mem2node: +mem2node__exit (&c2c.mem2node); out_session:perf_session__delete (session); out:
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 8/31 perf c2c report: Add span header over cacheline data
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
Forcing the NUMA node output to be grouped with the "Cacheline" column in both "Shared Data Cache Line Table" and "Shared Cache Line Distribution Pareto" tables.
Before:
# Total Tot ----- LLC Load Hitm -----
# Index Cacheline Node records Hitm Total Lcl Rmt
# ..... .................. .... ....... ....... ....... ....... .......
#
0 0x7f0830100000 0 84 10.53% 8 8 0
1 0xffff922a93154200 0 3 2.63% 2 2 0
2 0xffff922a93154500 0 4 2.63% 2 2 0After:
# ------- Cacheline ------ Total Tot ----- LLC Load Hitm -----
# Index Address Node records Hitm Total Lcl Rmt
# ..... .................. .... ....... ....... ....... ....... .......
#
0 0x7f0830100000 0 84 10.53% 8 8 0
1 0xffff922a93154200 0 3 2.63% 2 2 0
2 0xffff922a93154500 0 4 2.63% 2 2 0Before:
# ----- HITM ----- -- Store Refs -- Data address
# Num Rmt Lcl L1 Hit L1 Miss Offset Node Pid
# ..... ....... ....... ....... ....... .................. .... .......
#
-------------------------------------------------------------
0 0 8 32 2 0x7f0830100000
-------------------------------------------------------------
0.00% 75.00% 21.88% 0.00% 0x18 0 1791
0.00% 12.50% 37.50% 0.00% 0x18 0 1791
0.00% 0.00% 34.38% 0.00% 0x18 0 1791After:
# ----- HITM ----- -- Store Refs -- ----- Data address -----
# Num Rmt Lcl L1 Hit L1 Miss Offset Node Pid
# ..... ....... ....... ....... ....... .................. .... .......
#
-------------------------------------------------------------
0 0 8 32 2 0x7f0830100000
-------------------------------------------------------------
0.00% 75.00% 21.88% 0.00% 0x18 0 1791
0.00% 12.50% 37.50% 0.00% 0x18 0 1791
0.00% 0.00% 34.38% 0.00% 0x18 0 1791--- tools/perf/builtin-c2c.c | 63 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 58 insertions(+), 5 deletions(-)
tools/perf/builtin-c2c.c +58 -5
@@ -1252,7 +1252,7 @@ cl_idx_empty_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, }static struct c2c_dimension dim_dcacheline = { - .header =HEADER_LOW ("Cacheline" ), + .header =HEADER_SPAN ("--- Cacheline ----" ,"Address" ,1 ), .name ="dcacheline" , .cmp = dcacheline_cmp, .entry = dcacheline_entry,
@@ -1267,10 +1267,10 @@ static struct c2c_dimension dim_dcacheline_node = { .width = 4, }; -static struct c2c_header header_offset_tui =HEADER_LOW ("Off" ); +static struct c2c_header header_offset_tui =HEADER_SPAN ("-----" ,"Off" ,1 );static struct c2c_dimension dim_offset = { - .header =HEADER_BOTH ("Data address" ,"Offset" ), + .header =HEADER_SPAN ("--- Data address -" ,"Offset" ,1 ), .name ="offset" , .cmp = offset_cmp, .entry = offset_entry,
@@ -2453,14 +2453,64 @@ static void perf_c2c_display(struct perf_session *session) }#endif /* HAVE_SLANG_SUPPORT */ -static void ui_quirks (void ) +static char *fill_line (const char *orig,int len) { +int i, j, olen =strlen (orig); +char *buf; + + buf =zalloc (len +1 ); +if (!buf) +return NULL ; + + j = len /2 - olen /2 ; + +for (i =0 ; i < j -1 ; i++) + buf[i] ='-' ; + + buf[i++] =' ' ; + +strcpy (buf + i, orig); + + i += olen; + + buf[i++] =' ' ; + +for (; i < len; i++) + buf[i] ='-' ; + +return buf; +} + +static int ui_quirks (void ) +{ +const char *nodestr ="Data address" ; +char *buf; +if (!c2c.use_stdio) { dim_offset.width =5 ; dim_offset.header = header_offset_tui; + nodestr ="CL" ; } dim_percent_hitm.header = percent_hitm_header[c2c.display]; + +/* Fix the zero line for dcacheline column. */ + buf =fill_line ("Cacheline" , dim_dcacheline.width + + dim_dcacheline_node.width +2 ); +if (!buf) +return -ENOMEM ; + + dim_dcacheline.header.line[0 ].text = buf; + +/* Fix the zero line for offset column. */ + buf =fill_line (nodestr, dim_offset.width + + dim_offset_node.width +2 ); +if (!buf) +return -ENOMEM ; + + dim_offset.header.line[0 ].text = buf; + +return 0 ; }#define CALLCHAIN_DEFAULT_OPT "graph,0.5,caller,function,percent"
@@ -2760,7 +2810,10 @@ static int perf_c2c__report(int argc, const char **argv)ui_progress__finish (); -ui_quirks (); +if (ui_quirks ()) { +pr_err ("failed to setup UI\n" ); + goto out_mem2node; + }perf_c2c_display (session);
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 9/31 perf c2c report: Add cacheline address count column
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
Adding the 'PA cnt' column grouped under data cacheline address.
It shows how many times the physical addresses changed for the hist entry. It does not show the number of different physical addresses for entry, because we don't store those. We only track the number of times we got different address than we currently hold, which is not expensive and gives similar info.
$ perf c2c report --stdio
# ----------- Cacheline ---------- Total Tot ----- LLC Load Hitm -----
# Index Address Node PA cnt records Hitm Total Lcl Rmt
# ..... .................. .... ...... ....... ....... ....... ....... .......
#
0 0xffff9ad56dca0a80 0 9 10 7.69% 2 2 0
1 0xffff9ad56dce0a80 0 9 9 7.69% 2 2 0
2 0xffff9ad37659ad80 0 1 2 3.85% 1 1 0...
# ----- HITM ----- -- Store Refs -- --------- Data address ---------
# Num Rmt Lcl L1 Hit L1 Miss Offset Node PA cnt Pid
# ..... ....... ....... ....... ....... .................. .... ...... .......
#
-------------------------------------------------------------
0 0 2 3 0 0xffff9ad56dca0a80
-------------------------------------------------------------
0.00% 0.00% 33.33% 0.00% 0x0 0 1 2510
0.00% 0.00% 33.33% 0.00% 0x4 0 1 2476
0.00% 0.00% 33.33% 0.00% 0x20 0 1 0
0.00% 100.00% 0.00% 0.00% 0x38 0 1 0--- tools/perf/builtin-c2c.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-)
tools/perf/builtin-c2c.c +29 -6
@@ -507,6 +507,17 @@ dcacheline_node_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,return scnprintf (hpp->buf, hpp->size,"%*s" , width, c2c_he->nodestr); } +static int +dcacheline_node_count (struct perf_hpp_fmt *fmt,struct perf_hpp *hpp, +struct hist_entry *he) +{ +struct c2c_hist_entry *c2c_he; +int width =c2c_width (fmt, hpp, he->hists); + + c2c_he = container_of(he, struct c2c_hist_entry, he); +return scnprintf (hpp->buf, hpp->size,"%*lu" , width, c2c_he->paddr_cnt); +} +static int offset_entry (struct perf_hpp_fmt *fmt,struct perf_hpp *hpp,struct hist_entry *he) {
@@ -1252,7 +1263,7 @@ cl_idx_empty_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, }static struct c2c_dimension dim_dcacheline = { - .header =HEADER_SPAN ("--- Cacheline ----" ,"Address" ,1 ), + .header =HEADER_SPAN ("--- Cacheline ----" ,"Address" ,2 ), .name ="dcacheline" , .cmp = dcacheline_cmp, .entry = dcacheline_entry,
@@ -1267,10 +1278,18 @@ static struct c2c_dimension dim_dcacheline_node = { .width = 4, }; -static struct c2c_header header_offset_tui =HEADER_SPAN ("-----" ,"Off" ,1 ); +static struct c2c_dimension dim_dcacheline_count = { + .header =HEADER_LOW ("PA cnt" ), + .name ="dcacheline_count" , + .cmp = empty_cmp, + .entry = dcacheline_node_count, + .width =6 , +}; + +static struct c2c_header header_offset_tui =HEADER_SPAN ("-----" ,"Off" ,2 );static struct c2c_dimension dim_offset = { - .header =HEADER_SPAN ("--- Data address -" ,"Offset" ,1 ), + .header =HEADER_SPAN ("--- Data address -" ,"Offset" ,2 ), .name ="offset" , .cmp = offset_cmp, .entry = offset_entry,
@@ -1605,6 +1624,7 @@ static struct c2c_dimension dim_dcacheline_num_empty = {static struct c2c_dimension *dimensions[] = { &dim_dcacheline, &dim_dcacheline_node, + &dim_dcacheline_count, &dim_offset, &dim_offset_node, &dim_iaddr,
@@ -2496,7 +2516,8 @@ static int ui_quirks(void)/* Fix the zero line for dcacheline column. */ buf =fill_line ("Cacheline" , dim_dcacheline.width + - dim_dcacheline_node.width +2 ); + dim_dcacheline_node.width + + dim_dcacheline_count.width +4 );if (!buf)return -ENOMEM ;
@@ -2504,7 +2525,8 @@ static int ui_quirks(void)/* Fix the zero line for offset column. */ buf =fill_line (nodestr, dim_offset.width + - dim_offset_node.width +2 ); + dim_offset_node.width + + dim_dcacheline_count.width +4 );if (!buf)return -ENOMEM ;
@@ -2626,7 +2648,7 @@ static int build_cl_output(char *cl_sort, bool no_source)"percent_lcl_hitm," "percent_stores_l1hit," "percent_stores_l1miss," -"offset,offset_node," , +"offset,offset_node,dcacheline_count," , add_pid ?"pid," :"" , add_tid ?"tid," :"" , add_iaddr ? "iaddr," : "",
@@ -2789,6 +2811,7 @@ static int perf_c2c__report(int argc, const char **argv)"cl_idx," "dcacheline," "dcacheline_node," +"dcacheline_count," "tot_recs," "percent_hitm," "tot_hitm,lcl_hitm,rmt_hitm,"
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 10/31 perf tools arm64: Add libdw DWARF post unwind support for ARM64
In reply to Arnaldo Carvalho de MeloFrom: Kim Phillips <[email protected]>
Based on prior work:
https://lkml.org/lkml/2014/5/6/395
and on how other arches add libdw unwind support. Includes support for running the unwind test, e.g., on a system with only elfutils' libdw 0.170, the test now runs, and successfully:
$ ./perf test unwind 56: Test dwarf unwind : Ok
--- tools/perf/Makefile.config | 2 +- tools/perf/arch/arm64/include/arch-tests.h | 12 ++++++ tools/perf/arch/arm64/tests/Build | 2 + tools/perf/arch/arm64/tests/arch-tests.c | 16 ++++++++ tools/perf/arch/arm64/util/Build | 1 + tools/perf/arch/arm64/util/unwind-libdw.c | 60 ++++++++++++++++++++++++++++++ 6 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 tools/perf/arch/arm64/include/arch-tests.h create mode 100644 tools/perf/arch/arm64/tests/arch-tests.c create mode 100644 tools/perf/arch/arm64/util/unwind-libdw.c
tools/perf/Makefile.config +1 -1
@@ -75,7 +75,7 @@ endif # Disable it on all other architectures in case libdw unwind # support is detected in system. Add supported architectures # to the check. -ifneq ($(SRCARCH),$(filter $(SRCARCH),x86 arm powerpc s390)) +ifneq ($(SRCARCH),$(filter $(SRCARCH),x86 arm arm64 powerpc s390)) NO_LIBDW_DWARF_UNWIND := 1 endif
tools/perf/arch/arm64/include/arch-tests.h new file +12 -0
@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef ARCH_TESTS_H +#define ARCH_TESTS_H + +#ifdef HAVE_DWARF_UNWIND_SUPPORT +struct thread ; +struct perf_sample ; +#endif + +extern struct test arch_tests[]; + +#endif
tools/perf/arch/arm64/tests/Build +2 -0
@@ -1,2 +1,4 @@ libperf-y += regs_load.o libperf-y += dwarf-unwind.o + +libperf-y += arch-tests.o
tools/perf/arch/arm64/tests/arch-tests.c new file +16 -0
@@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <string.h> +#include "tests/tests.h" +#include "arch-tests.h" + +struct test arch_tests[] = { +#ifdef HAVE_DWARF_UNWIND_SUPPORT + { + .desc = "DWARF unwind", + .func = test__dwarf_unwind, + }, +#endif + { + .func = NULL, + }, +};
tools/perf/arch/arm64/util/Build +1 -0
@@ -2,6 +2,7 @@ libperf-y += header.o libperf-y += sym-handling.o libperf-$(CONFIG_DWARF) += dwarf-regs.o libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o +libperf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o libperf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o \ ../../arm/util/auxtrace.o \
tools/perf/arch/arm64/util/unwind-libdw.c new file +60 -0
60 lines not on this page · raw message
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 11/31 perf vendor events: Drop incomplete multiple mapfile support
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
Currently jevents supports multiple mapfiles, but this is only in the form where mapfile basename starts with 'mapfile.csv'
At the moment, no architectures actually use multiple mapfiles, so drop the support for now.
This patch also solves a nuisance where, when the mapfile is edited and the text editor may create a backup, jevents may use the backup, as shown:
jevents: Many mapfiles? Using pmu-events/arch/arm64/mapfile.csv~, ignoring pmu-events/arch/arm64/mapfile.csv
--- tools/perf/pmu-events/README | 5 ++--- tools/perf/pmu-events/jevents.c | 10 ++-------- 2 files changed, 4 insertions(+), 11 deletions(-)
tools/perf/pmu-events/README +2 -3
@@ -11,9 +11,8 @@ tree tools/perf/pmu-events/arch/foo. - Regular files with '.json' extension in the name are assumed to be JSON files, each of which describes a set of PMU events. - - Regular files with basename starting with 'mapfile.csv' are assumed - to be a CSV file that maps a specific CPU to its set of PMU events. - (see below for mapfile format) + - The CSV file that maps a specific CPU to its set of PMU events is to + be named 'mapfile.csv' (see below for mapfile format). - Directories are traversed, but all other files are ignored.
tools/perf/pmu-events/jevents.c +2 -8
@@ -798,16 +798,10 @@ static int process_one_file(const char *fpath, const struct stat *sb,* after processing all JSON files (so we can write out the * mapping table after all PMU events tables). * -* TODO: Allow for multiple mapfiles? Punt for now. */ if (level ==1 && is_file) { -if (!strncmp (bname,"mapfile.csv" ,11 )) { -if (mapfile) { -pr_info ("%s: Many mapfiles? Using %s, ignoring %s\n" , - prog, mapfile, fpath); - }else { - mapfile =strdup (fpath); - } +if (!strcmp (bname,"mapfile.csv" )) { + mapfile =strdup (fpath);return 0 ; }
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 12/31 perf vendor events: Fix error code in json_events()
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
When EXPECT macro fails an assertion, the error code is not properly set after the first loop of tokens in function json_events().
This is because err is set to the return value from func function pointer call, which must be 0 to continue to loop, yet it is not reset for for each loop. I assume that this was not the intention, so change the code so err is set appropriately in EXPECT macro itself.
In addition to this, the indention in EXPECT macro is tidied. The current indention alludes that the 2 statements following the if statement are in the body, which is not true.
--- tools/perf/pmu-events/jevents.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
tools/perf/pmu-events/jevents.c +5 -4
@@ -249,9 +249,10 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val)jsmntok_t *loc = (t); \if (!(t)->start && (t) > tokens) \ loc = (t) -1 ; \ -pr_err ("%s:%d: " m", got %s\n" , fn, \ -json_line (map, loc), \ -json_name (t)); \ +pr_err ("%s:%d: " m", got %s\n" , fn, \ +json_line (map, loc), \ +json_name (t)); \ + err = -EIO ; \ goto out_free; \ } }while (0 )
@@ -416,7 +417,7 @@ int json_events(const char *fn, char *metric_name, char *metric_group), void *data) { - int err = -EIO; + int err;size_t size;jsmntok_t *tokens, *tok;int i, j, len;
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 13/31 perf vendor events: Drop support for unused topic directories
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
Currently a topic subdirectory is supported in the pmu-events dir, in the following sample structure: /arch/platform/subtopic/mysubtopic.json
Upto 256 levels of topic subdirectories are supported. So this means that JSONs may be located in a topic dir as well as the platform dir.
This topic subdirectory causes problems if we want to add support for a vendor dir in the pmu-events structure (in the form arch/platform/vendor), in that we cannot differentiate between a vendor dir and a topic dir.
Since the topic dir feature is not used, drop it so it does not block adding vendor subdirectory support.
--- tools/perf/pmu-events/jevents.c | 37 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 27 deletions(-)
tools/perf/pmu-events/jevents.c +10 -27
@@ -256,25 +256,18 @@ static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val) goto out_free; \ } }while (0 ) -#define TOPIC_DEPTH 256 -static char *topic_array[TOPIC_DEPTH ]; -static int topic_level; +static char *topic;static char *get_topic (void ) { -char *tp_old, *tp =NULL ; +char *tp;int i; -for (i =0 ; i < topic_level +1 ; i++) { -int n; - - tp_old = tp; - n =asprintf (&tp,"%s%s" , tp ?:"" , topic_array[i]); -if (n <0 ) { -pr_info ("%s: asprintf() error %s\n" , prog); -return NULL ; - } -free (tp_old); +/* tp is free'd in process_one_file() */ + i =asprintf (&tp,"%s" , topic); +if (i <0 ) { +pr_info ("%s: asprintf() error %s\n" , prog); +return NULL ; }for (i =0 ; i < (int )strlen (tp); i++) {
@@ -291,25 +284,15 @@ static char *get_topic(void)return tp; } -static int add_topic (int level,char *bname) +static int add_topic (char *bname) { -char *topic; - - level -=2 ; - -if (level >=TOPIC_DEPTH ) -return -EINVAL ; - +free (topic); topic =strdup (bname);if (!topic) {pr_info ("%s: strdup() error %s for file %s\n" , prog,strerror (errno), bname);return -ENOMEM ; } - -free (topic_array[topic_level]); - topic_array[topic_level] = topic; - topic_level = level;return 0 ; }
@@ -824,7 +807,7 @@ static int process_one_file(const char *fpath, const struct stat *sb, } } -if (level >1 &&add_topic (level, bname)) +if (level >1 &&add_topic (bname))return -ENOMEM ;/*
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 14/31 perf vendor events: Add support for pmu events vendor subdirectory
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
For some architectures (like arm), it is required to support a vendor subdirectory and not locate all the JSONs for a specific vendor in the same folder.
This is because all the events for the same vendor will be placed in the same pmu events table, which may cause conflict. This conflict would be in the instance that a vendor's custom implemented events do have the same meaning on different platforms, so events in the pmu table would conflict. In addition, per list command may show events which are not even supported for a given platform.
This patch adds support for a arch/vendor/platform directory hierarchy, while maintaining backwards-compatibility for existing arch/platform structure. In this, each platform would always have its own pmu events table.
In generated file pmu_events.c, each platform table name is in the format pme{_vendor}_platform, like this:
struct pmu_events_map pmu_events_map[] = {
{
.cpuid = "0x00000000420f5160",
.version = "v1",
.type = "core",
.table = pme_cavium_thunderx2
},
{
.cpuid = 0,
.version = 0,
.type = 0,
.table = 0,
},};
--- tools/perf/pmu-events/README | 4 +++ tools/perf/pmu-events/jevents.c | 65 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 63 insertions(+), 6 deletions(-)
tools/perf/pmu-events/README +4 -0
@@ -28,6 +28,10 @@ sub directory. Thus for the Silvermont X86 CPU: Cache.json Memory.json Virtual-Memory.json Frontend.json Pipeline.json +The JSONs folder for a CPU model/family may be placed in the root arch +folder, or may be placed in a vendor sub-folder under the arch folder +for instances where the arch and vendor are not the same. + Using the JSON files and the mapfile, 'jevents' generates the C source file, 'pmu-events.c', which encodes the two sets of tables:
tools/perf/pmu-events/jevents.c +59 -6
104 lines not on this page · raw message
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 15/31 perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectory
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
Since jevents now supports vendor subdirectory, relocate the ThunderX2 JSON to Cavium subdirectory.
---
.../cavium/{thunderx2-imp-def.json => thunderx2/core-imp-def.json} | 0
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename tools/perf/pmu-events/arch/arm64/cavium/{thunderx2-imp-def.json => thunderx2/core-imp-def.json} (100%)tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json renamed from tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json +0 -0
tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -1
@@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType -0x00000000420f5160,v1,cavium,core +0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 16/31 perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectory
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
Since jevents now supports vendor subdirectory, relocate the Cortex-A53 JSONs to arm subdirectory.
---
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/bus.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/cache.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/other.json | 0
tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json | 0
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
7 files changed, 1 insertion(+), 1 deletion(-)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/branch.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/bus.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/cache.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/memory.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/other.json (100%)
rename tools/perf/pmu-events/arch/arm64/{ => arm}/cortex-a53/pipeline.json (100%)tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json renamed from tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json +0 -0
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json renamed from tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json +0 -0
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json renamed from tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json +0 -0
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json renamed from tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json +0 -0
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json renamed from tools/perf/pmu-events/arch/arm64/cortex-a53/other.json +0 -0
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json renamed from tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json +0 -0
tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -1
@@ -12,5 +12,5 @@ # # #Family-model,Version,Filename,EventType +0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core -0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 17/31 perf vendor events: Add support for arch standard events
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
For some architectures (like arm), there are architecture- defined events. Sometimes these events may be "recommended" according to the architecture standard, in that the implementer is free ignore the "recommendation" and create its custom event.
This patch adds support for parsing standard events from arch-defined JSONs, and fixing up vendor events when they have implemented these events as standard.
Support is also ensured that the vendor may implement their own custom events.
A new step is added to the pmu events parsing to fix up the vendor events with the arch-standard events.
The arch-defined JSONs must be placed in the arch root folder for preprocessing prior to tree JSON processing.
In the vendor JSON, to specify that the arch event is supported, the keyword "ArchStdEvent" should be used, like this:
[
{
"ArchStdEvent": "L1D_CACHE_WR",
},]
Matching is based on the "EventName" field in the architecture JSON.
No other JSON objects are strictly required. However, for other objects added, these take precedence over architecture defined standard events, thus supporting separate events which have the same event code.
--- tools/perf/pmu-events/Build | 2 + tools/perf/pmu-events/README | 6 ++ tools/perf/pmu-events/jevents.c | 167 +++++++++++++++++++++++++++++++++++++++- 3 files changed, 172 insertions(+), 3 deletions(-)
tools/perf/pmu-events/Build +2 -0
@@ -1,10 +1,12 @@ hostprogs := jevents jevents-y += json.o jsmn.o jevents.o +CHOSTFLAGS_jevents.o = -I$(srctree)/tools/include pmu-events-y += pmu-events.o JDIR = pmu-events/arch/$(SRCARCH) JSON = $(shell [ -d $(JDIR) ] && \ find $(JDIR) -name '*.json' -o -name 'mapfile.csv') + # # Locate/process JSON files in pmu-events/arch/ # directory and create tables in pmu-events.c.
tools/perf/pmu-events/README +6 -0
@@ -16,6 +16,12 @@ tree tools/perf/pmu-events/arch/foo. - Directories are traversed, but all other files are ignored. + - To reduce JSON event duplication per architecture, platform JSONs may + use "ArchStdEvent" keyword to dereference an "Architecture standard + events", defined in architecture standard JSONs. + Architecture standard JSONs must be located in the architecture root + folder. Matching is based on the "EventName" field. + The PMU events supported by a CPU model are expected to grouped into topics such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic should be placed in a separate JSON file - where the file name identifies
tools/perf/pmu-events/jevents.c +164 -3
240 lines not on this page · raw message
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 18/31 perf vendor events arm64: Add armv8-recommended.json
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
--- .../pmu-events/arch/arm64/armv8-recommended.json | 452 +++++++++++++++++++++ 1 file changed, 452 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/armv8-recommended.json
tools/perf/pmu-events/arch/arm64/armv8-recommended.json new file +452 -0
@@ -0,0 +1,452 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "L1D_CACHE_RD", + "BriefDescription": "L1D cache access, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write", + "EventCode": "0x41", + "EventName": "L1D_CACHE_WR", + "BriefDescription": "L1D cache access, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "L1D_CACHE_REFILL_RD", + "BriefDescription": "L1D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "L1D_CACHE_REFILL_WR", + "BriefDescription": "L1D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, inner", + "EventCode": "0x44", + "EventName": "L1D_CACHE_REFILL_INNER", + "BriefDescription": "L1D cache refill, inner" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, outer", + "EventCode": "0x45", + "EventName": "L1D_CACHE_REFILL_OUTER", + "BriefDescription": "L1D cache refill, outer" + }, + { + "PublicDescription": "Attributable Level 1 data cache Write-Back, victim", + "EventCode": "0x46", + "EventName": "L1D_CACHE_WB_VICTIM", + "BriefDescription": "L1D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency", + "EventCode": "0x47", + "EventName": "L1D_CACHE_WB_CLEAN", + "BriefDescription": "L1D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 1 data cache invalidate", + "EventCode": "0x48", + "EventName": "L1D_CACHE_INVAL", + "BriefDescription": "L1D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "L1D_TLB_REFILL_RD", + "BriefDescription": "L1D tlb refill, read" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "L1D_TLB_REFILL_WR", + "BriefDescription": "L1D tlb refill, write" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "L1D_TLB_RD", + "BriefDescription": "L1D tlb access, read" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "L1D_TLB_WR", + "BriefDescription": "L1D tlb access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, read", + "EventCode": "0x50", + "EventName": "L2D_CACHE_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache access, write", + "EventCode": "0x51", + "EventName": "L2D_CACHE_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, read", + "EventCode": "0x52", + "EventName": "L2D_CACHE_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data cache refill, write", + "EventCode": "0x53", + "EventName": "L2D_CACHE_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data cache Write-Back, victim", + "EventCode": "0x56", + "EventName": "L2D_CACHE_WB_VICTIM", + "BriefDescription": "L2D cache Write-Back, victim" + }, + { + "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency", + "EventCode": "0x57", + "EventName": "L2D_CACHE_WB_CLEAN", + "BriefDescription": "L2D cache Write-Back, cleaning and coherency" + }, + { + "PublicDescription": "Attributable Level 2 data cache invalidate", + "EventCode": "0x58", + "EventName": "L2D_CACHE_INVAL", + "BriefDescription": "L2D cache invalidate" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, read", + "EventCode": "0x5c", + "EventName": "L2D_TLB_REFILL_RD", + "BriefDescription": "L2D cache refill, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB refill, write", + "EventCode": "0x5d", + "EventName": "L2D_TLB_REFILL_WR", + "BriefDescription": "L2D cache refill, write" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, read", + "EventCode": "0x5e", + "EventName": "L2D_TLB_RD", + "BriefDescription": "L2D cache access, read" + }, + { + "PublicDescription": "Attributable Level 2 data or unified TLB access, write", + "EventCode": "0x5f", + "EventName": "L2D_TLB_WR", + "BriefDescription": "L2D cache access, write" + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "BUS_ACCESS_RD", + "BriefDescription": "Bus access read" + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "BUS_ACCESS_WR", + "BriefDescription": "Bus access write" + } + { + "PublicDescription": "Bus access, Normal, Cacheable, Shareable", + "EventCode": "0x62", + "EventName": "BUS_ACCESS_SHARED", + "BriefDescription": "Bus access, Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, not Normal, Cacheable, Shareable", + "EventCode": "0x63", + "EventName": "BUS_ACCESS_NOT_SHARED", + "BriefDescription": "Bus access, not Normal, Cacheable, Shareable" + } + { + "PublicDescription": "Bus access, Normal", + "EventCode": "0x64", + "EventName": "BUS_ACCESS_NORMAL", + "BriefDescription": "Bus access, Normal" + } + { + "PublicDescription": "Bus access, peripheral", + "EventCode": "0x65", + "EventName": "BUS_ACCESS_PERIPH", + "BriefDescription": "Bus access, peripheral" + } + { + "PublicDescription": "Data memory access, read", + "EventCode": "0x66", + "EventName": "MEM_ACCESS_RD", + "BriefDescription": "Data memory access, read" + } + { + "PublicDescription": "Data memory access, write", + "EventCode": "0x67", + "EventName": "MEM_ACCESS_WR", + "BriefDescription": "Data memory access, write" + } + { + "PublicDescription": "Unaligned access, read", + "EventCode": "0x68", + "EventName": "UNALIGNED_LD_SPEC", + "BriefDescription": "Unaligned access, read" + } + { + "PublicDescription": "Unaligned access, write", + "EventCode": "0x69", + "EventName": "UNALIGNED_ST_SPEC", + "BriefDescription": "Unaligned access, write" + } + { + "PublicDescription": "Unaligned access", + "EventCode": "0x6a", + "EventName": "UNALIGNED_LDST_SPEC", + "BriefDescription": "Unaligned access" + } + { + "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX", + "EventCode": "0x6c", + "EventName": "LDREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass", + "EventCode": "0x6d", + "EventName": "STREX_PASS_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail", + "EventCode": "0x6e", + "EventName": "STREX_FAIL_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail" + } + { + "PublicDescription": "Exclusive operation speculatively executed, STREX or STX", + "EventCode": "0x6f", + "EventName": "STREX_SPEC", + "BriefDescription": "Exclusive operation speculatively executed, STREX or STX" + } + { + "PublicDescription": "Operation speculatively executed, load", + "EventCode": "0x70", + "EventName": "LD_SPEC", + "BriefDescription": "Operation speculatively executed, load" + } + { + "PublicDescription": "Operation speculatively executed, store" + "EventCode": "0x71", + "EventName": "ST_SPEC", + "BriefDescription": "Operation speculatively executed, store" + } + { + "PublicDescription": "Operation speculatively executed, load or store", + "EventCode": "0x72", + "EventName": "LDST_SPEC", + "BriefDescription": "Operation speculatively executed, load or store" + } + { + "PublicDescription": "Operation speculatively executed, integer data processing", + "EventCode": "0x73", + "EventName": "DP_SPEC", + "BriefDescription": "Operation speculatively executed, integer data processing" + } + { + "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction", + "EventCode": "0x74", + "EventName": "ASE_SPEC", + "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction", + } + { + "PublicDescription": "Operation speculatively executed, floating-point instruction", + "EventCode": "0x75", + "EventName": "VFP_SPEC", + "BriefDescription": "Operation speculatively executed, floating-point instruction" + } + { + "PublicDescription": "Operation speculatively executed, software change of the PC", + "EventCode": "0x76", + "EventName": "PC_WRITE_SPEC", + "BriefDescription": "Operation speculatively executed, software change of the PC" + } + { + "PublicDescription": "Operation speculatively executed, Cryptographic instruction", + "EventCode": "0x77", + "EventName": "CRYPTO_SPEC", + "BriefDescription": "Operation speculatively executed, Cryptographic instruction" + } + { + "PublicDescription": "Branch speculatively executed, immediate branch" + "EventCode": "0x78", + "EventName": "BR_IMMED_SPEC", + "BriefDescription": "Branch speculatively executed, immediate branch" + } + { + "PublicDescription": "Branch speculatively executed, procedure return" + "EventCode": "0x79", + "EventName": "BR_RETURN_SPEC", + "BriefDescription": "Branch speculatively executed, procedure return" + } + { + "PublicDescription": "Branch speculatively executed, indirect branch" + "EventCode": "0x7a", + "EventName": "BR_INDIRECT_SPEC", + "BriefDescription": "Branch speculatively executed, indirect branch" + } + { + "PublicDescription": "Barrier speculatively executed, ISB" + "EventCode": "0x7c", + "EventName": "ISB_SPEC", + "BriefDescription": "Barrier speculatively executed, ISB" + } + { + "PublicDescription": "Barrier speculatively executed, DSB" + "EventCode": "0x7d", + "EventName": "DSB_SPEC", + "BriefDescription": "Barrier speculatively executed, DSB" + } + { + "PublicDescription": "Barrier speculatively executed, DMB" + "EventCode": "0x7e", + "EventName": "DMB_SPEC", + "BriefDescription": "Barrier speculatively executed, DMB" + } + { + "PublicDescription": "Exception taken, Other synchronous" + "EventCode": "0x81", + "EventName": "EXC_UNDEF", + "BriefDescription": "Exception taken, Other synchronous" + } + { + "PublicDescription": "Exception taken, Supervisor Call" + "EventCode": "0x82", + "EventName": "EXC_SVC", + "BriefDescription": "Exception taken, Supervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort" + "EventCode": "0x83", + "EventName": "EXC_PABORT", + "BriefDescription": "Exception taken, Instruction Abort" + } + { + "PublicDescription": "Exception taken, Data Abort and SError" + "EventCode": "0x84", + "EventName": "EXC_DABORT", + "BriefDescription": "Exception taken, Data Abort and SError" + } + { + "PublicDescription": "Exception taken, IRQ" + "EventCode": "0x86", + "EventName": "EXC_IRQ", + "BriefDescription": "Exception taken, IRQ" + } + { + "PublicDescription": "Exception taken, FIQ" + "EventCode": "0x87", + "EventName": "EXC_FIQ", + "BriefDescription": "Exception taken, FIQ" + } + { + "PublicDescription": "Exception taken, Secure Monitor Call" + "EventCode": "0x88", + "EventName": "EXC_SMC", + "BriefDescription": "Exception taken, Secure Monitor Call" + } + { + "PublicDescription": "Exception taken, Hypervisor Call" + "EventCode": "0x8a", + "EventName": "EXC_HVC", + "BriefDescription": "Exception taken, Hypervisor Call" + } + { + "PublicDescription": "Exception taken, Instruction Abort not taken locally" + "EventCode": "0x8b", + "EventName": "EXC_TRAP_PABORT", + "BriefDescription": "Exception taken, Instruction Abort not taken locally" + } + { + "PublicDescription": "Exception taken, Data Abort or SError not taken locally" + "EventCode": "0x8c", + "EventName": "EXC_TRAP_DABORT", + "BriefDescription": "Exception taken, Data Abort or SError not taken locally" + } + { + "PublicDescription": "Exception taken, Other traps not taken locally" + "EventCode": "0x8d", + "EventName": "EXC_TRAP_OTHER", + "BriefDescription": "Exception taken, Other traps not taken locally" + } + { + "PublicDescription": "Exception taken, IRQ not taken locally" + "EventCode": "0x8e", + "EventName": "EXC_TRAP_IRQ", + "BriefDescription": "Exception taken, IRQ not taken locally" + } + { + "PublicDescription": "Exception taken, FIQ not taken locally" + "EventCode": "0x8f", + "EventName": "EXC_TRAP_FIQ", + "BriefDescription": "Exception taken, FIQ not taken locally" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Load-Acquire" + "EventCode": "0x90", + "EventName": "RC_LD_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Load-Acquire" + } + { + "PublicDescription": "Release consistency operation speculatively executed, Store-Release" + "EventCode": "0x91", + "EventName": "RC_ST_SPEC", + "BriefDescription": "Release consistency operation speculatively executed, Store-Release" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, read" + "EventCode": "0xa0", + "EventName": "L3D_CACHE_RD", + "BriefDescription": "Attributable Level 3 data or unified cache access, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, write" + "EventCode": "0xa1", + "EventName": "L3D_CACHE_WR", + "BriefDescription": "Attributable Level 3 data or unified cache access, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, read" + "EventCode": "0xa2", + "EventName": "L3D_CACHE_REFILL_RD", + "BriefDescription": "Attributable Level 3 data or unified cache refill, read" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache refill, write" + "EventCode": "0xa3", + "EventName": "L3D_CACHE_REFILL_WR", + "BriefDescription": "Attributable Level 3 data or unified cache refill, write" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, victim" + "EventCode": "0xa6", + "EventName": "L3D_CACHE_WB_VICTIM", + "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, victim" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean" + "EventCode": "0xa7", + "EventName": "L3D_CACHE_WB_CLEAN", + "BriefDescription": "Attributable Level 3 data or unified cache Write-Back, cache clean" + } + { + "PublicDescription": "Attributable Level 3 data or unified cache access, invalidate" + "EventCode": "0xa8", + "EventName": "L3D_CACHE_INVAL", + "BriefDescription": "Attributable Level 3 data or unified cache access, invalidate" + } +]
Signature · 1 line
2.14.3
Re: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
Quoted 9 lines · Arnaldo Carvalho de Melo
From: John Garry <[email protected]>
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf
Quoted 15 lines
Signed-off-by Shaokun Zhang <[email protected]>Cc Alexander Shishkin <[email protected]>Cc Andi Kleen <[email protected]>Cc Ganapatrao Kulkarni <[email protected]>Cc Jiri Olsa <[email protected]>Cc Namhyung Kim <[email protected]>Cc Peter Zijlstra <[email protected]>Cc Shaokun Zhang <[email protected]>Cc Will Deacon <[email protected]>Cc William Cohen <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc linuxarm at huawei.comLink http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.comSigned-off-by John Garry <[email protected]>Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
That's not a valid SOB chain, author != first-Signed-off-by.
Thanks,
Ingo
Re: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
Quoted 28 lines · Ingo Molnar
Quoted 9 lines · Arnaldo Carvalho de Melo
From: John Garry <[email protected]>
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdfQuoted 15 lines
Signed-off-by Shaokun Zhang <[email protected]>Cc Alexander Shishkin <[email protected]>Cc Andi Kleen <[email protected]>Cc Ganapatrao Kulkarni <[email protected]>Cc Jiri Olsa <[email protected]>Cc Namhyung Kim <[email protected]>Cc Peter Zijlstra <[email protected]>Cc Shaokun Zhang <[email protected]>Cc Will Deacon <[email protected]>Cc William Cohen <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc linuxarm at huawei.comLink http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.comSigned-off-by John Garry <[email protected]>Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
Quoted 2 lines
That's not a valid SOB chain, author != first-Signed-off-by.
Right, so my SOB can go first.
Let me know how to help remedy.
Thanks,
John
Quoted 6 lines
Thanks,
Ingo
.
Re: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
Quoted 29 lines · John Garry
Quoted 28 lines · Ingo Molnar
Quoted 24 lines · Arnaldo Carvalho de Melo
From: John Garry <[email protected]>
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdfSigned-off-by Shaokun Zhang <[email protected]>Cc Alexander Shishkin <[email protected]>Cc Andi Kleen <[email protected]>Cc Ganapatrao Kulkarni <[email protected]>Cc Jiri Olsa <[email protected]>Cc Namhyung Kim <[email protected]>Cc Peter Zijlstra <[email protected]>Cc Shaokun Zhang <[email protected]>Cc Will Deacon <[email protected]>Cc William Cohen <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc linuxarm at huawei.comLink http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.comSigned-off-by John Garry <[email protected]>Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
Quoted 6 lines
Quoted 2 lines
That's not a valid SOB chain, author != first-Signed-off-by.
Right, so my SOB can go first.
Let me know how to help remedy.
Well, it depends on what role Shaokun Zhang had in the creation of the patch: if he co-authored the patch and you finished it then you can add him as:
Originally-from: Shaokun Zhang <[email protected]>
or if he tested/reviewed the patch then his entry should be Reviewed-by/Acked-by or Tested-by.
Thanks,
Ingo
Arnaldo Carvalho de Melo
maintainerRe: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
Em Tue, Mar 13, 2018 at 04:08:38PM +0100, Ingo Molnar escreveu:
Quoted 39 lines · John Garry
Quoted 30 lines · Ingo Molnar
Quoted 28 lines · Arnaldo Carvalho de Melo
Quoted 25 lines
From: John Garry <[email protected]>
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdfSigned-off-by Shaokun Zhang <[email protected]>Cc Alexander Shishkin <[email protected]>Cc Andi Kleen <[email protected]>Cc Ganapatrao Kulkarni <[email protected]>Cc Jiri Olsa <[email protected]>Cc Namhyung Kim <[email protected]>Cc Peter Zijlstra <[email protected]>Cc Shaokun Zhang <[email protected]>Cc Will Deacon <[email protected]>Cc William Cohen <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc linuxarm at huawei.comLink http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.comSigned-off-by John Garry <[email protected]>Signed-off-by Arnaldo Carvalho de Melo <[email protected]>Quoted 6 lines
Quoted 2 lines
That's not a valid SOB chain, author != first-Signed-off-by.
Right, so my SOB can go first.
Let me know how to help remedy.
Quoted 7 lines
Well, it depends on what role Shaokun Zhang had in the creation of the patch: if he co-authored the patch and you finished it then you can add him as:
Originally-from: Shaokun Zhang <[email protected]>
or if he tested/reviewed the patch then his entry should be Reviewed-by/Acked-by or Tested-by.
yeah, please clarify what his role was and I'll do the necessary changes, in addition to adding more code to my pre-commit scripts, something long overdue...
- Arnaldo
Re: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
In reply to Ingo MolnarQuoted 9 lines · Ingo Molnar
Quoted 6 lines · John Garry
Quoted 5 lines · Ingo Molnar
Quoted 2 lines · Arnaldo Carvalho de Melo
From: John Garry <[email protected]>
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdfSigned-off-by Shaokun Zhang <[email protected]>
Originally-from: Shaokun Zhang <[email protected]>
Quoted 22 lines
Quoted 15 lines
Quoted 15 lines
Quoted 14 lines
Cc Alexander Shishkin <[email protected]>Cc Andi Kleen <[email protected]>Cc Ganapatrao Kulkarni <[email protected]>Cc Jiri Olsa <[email protected]>Cc Namhyung Kim <[email protected]>Cc Peter Zijlstra <[email protected]>Cc Shaokun Zhang <[email protected]>Cc Will Deacon <[email protected]>Cc William Cohen <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc linuxarm at huawei.comLink http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.comSigned-off-by John Garry <[email protected]>Signed-off-by Arnaldo Carvalho de Melo <[email protected]>Quoted 6 lines
Quoted 2 lines
That's not a valid SOB chain, author != first-Signed-off-by.
Right, so my SOB can go first.
Let me know how to help remedy.
Quoted 8 lines
Well, it depends on what role Shaokun Zhang had in the creation of the patch: if he co-authored the patch and you finished it then you can add him as:
Originally-from: Shaokun Zhang <[email protected]>
or if he tested/reviewed the patch then his entry should be Reviewed-by/Acked-by or Tested-by.
Hi Ingo, Arnaldo,
I think it would be fair to say the former, that is: "he co-authored the patch and you finished it".
Thanks,
John
Quoted 10 lines
Thanks,
Ingo
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Arnaldo Carvalho de Melo
maintainerRe: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
In reply to Ingo MolnarEm Tue, Mar 13, 2018 at 03:26:18PM +0100, Ingo Molnar escreveu:
Quoted 28 lines · Arnaldo Carvalho de Melo
Quoted 10 lines
From: John Garry <[email protected]>
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdfQuoted 15 lines
Signed-off-by Shaokun Zhang <[email protected]>Cc Alexander Shishkin <[email protected]>Cc Andi Kleen <[email protected]>Cc Ganapatrao Kulkarni <[email protected]>Cc Jiri Olsa <[email protected]>Cc Namhyung Kim <[email protected]>Cc Peter Zijlstra <[email protected]>Cc Shaokun Zhang <[email protected]>Cc Will Deacon <[email protected]>Cc William Cohen <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc linuxarm at huawei.comLink http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.comSigned-off-by John Garry <[email protected]>Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
Quoted 1 line
That's not a valid SOB chain, author != first-Signed-off-by.
Ok, I'll fix that.
- Arnaldo
Arnaldo Carvalho de Melo
maintainerRe: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
In reply to Ingo MolnarEm Tue, Mar 13, 2018 at 03:26:18PM +0100, Ingo Molnar escreveu:
Quoted 26 lines · Arnaldo Carvalho de Melo
Quoted 9 lines
From: John Garry <[email protected]>
Add JSON for ARMv8 IMPLEMENTATION DEFINED recommended events.
The JSON is copied from ARMv8 architecture reference manual, available here:
https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdfQuoted 15 lines
Signed-off-by Shaokun Zhang <[email protected]>Cc Alexander Shishkin <[email protected]>Cc Andi Kleen <[email protected]>Cc Ganapatrao Kulkarni <[email protected]>Cc Jiri Olsa <[email protected]>Cc Namhyung Kim <[email protected]>Cc Peter Zijlstra <[email protected]>Cc Shaokun Zhang <[email protected]>Cc Will Deacon <[email protected]>Cc William Cohen <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc linuxarm at huawei.comLink http://lkml.kernel.org/r/1520506716-197429-9-git-send-email-john.garry at huawei.comSigned-off-by John Garry <[email protected]>Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
Quoted 1 line
That's not a valid SOB chain, author != first-Signed-off-by.
I removed that cset for now, can you please check if the perf-core-for-mingo-4.17-20180313-2 tag is allright?
- Arnaldo
Arnaldo Carvalho de Melo
maintainerRe: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
Em Tue, Mar 13, 2018 at 03:27:30PM -0300, Arnaldo Carvalho de Melo escreveu:
Quoted 5 lines
Em Tue, Mar 13, 2018 at 03:26:18PM +0100, Ingo Molnar escreveu:
Quoted 1 line
That's not a valid SOB chain, author != first-Signed-off-by.
I removed that cset for now, can you please check if the perf-core-for-mingo-4.17-20180313-2 tag is allright?
So, since there is this problem with powerpc and jevents, Ingo, please hold on a bit more... Hopefully tomorrow things will be in a better shape.
- Arnaldo
Re: [PATCH 18/31] perf vendor events arm64: Add armv8-recommended.json
Quoted 10 lines · Arnaldo Carvalho de Melo
Em Tue, Mar 13, 2018 at 03:27:30PM -0300, Arnaldo Carvalho de Melo escreveu:
Quoted 5 lines
Em Tue, Mar 13, 2018 at 03:26:18PM +0100, Ingo Molnar escreveu:
Quoted 1 line
That's not a valid SOB chain, author != first-Signed-off-by.
I removed that cset for now, can you please check if the perf-core-for-mingo-4.17-20180313-2 tag is allright?
So, since there is this problem with powerpc and jevents, Ingo, please hold on a bit more... Hopefully tomorrow things will be in a better shape.
Sure, no problem!
Thanks,
Ingo
Arnaldo Carvalho de Melo
maintainerPATCH 19/31 perf vendor events arm64: Fixup ThunderX2 to use recommended events
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
This patch fixes the Cavium ThunderX2 JSON to use event definitions from the ARMv8 recommended events.
--- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++----------------- 1 file changed, 10 insertions(+), 40 deletions(-)
tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +10 -40
@@ -1,62 +1,32 @@ [ { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", + "ArchStdEvent": "L1D_CACHE_RD", }, { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", + "ArchStdEvent": "L1D_CACHE_WR", }, { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", + "ArchStdEvent": "L1D_CACHE_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", + "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", + "ArchStdEvent": "L1D_TLB_REFILL_RD", }, { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", + "ArchStdEvent": "L1D_TLB_REFILL_WR", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", + "ArchStdEvent": "L1D_TLB_RD", }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", + "ArchStdEvent": "L1D_TLB_WR", }, { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", + "ArchStdEvent": "BUS_ACCESS_RD", }, { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", + "ArchStdEvent": "BUS_ACCESS_WR", } ]
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 20/31 perf vendor events arm64: fixup A53 to use recommended events
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
This patch fixes the ARM Cortex-A53 json to use event definition from the ARMv8 recommended events.
In addition to this change, other changes were made:
- remove stray ','
- remove mirrored events in memory.json and bus.json
- fixed indentation to be consistent with other ARM JSONs
--- .../arch/arm64/arm/cortex-a53/branch.json | 14 +++---- .../pmu-events/arch/arm64/arm/cortex-a53/bus.json | 22 ++--------- .../arch/arm64/arm/cortex-a53/cache.json | 40 ++++++++++---------- .../arch/arm64/arm/cortex-a53/memory.json | 14 +------ .../arch/arm64/arm/cortex-a53/other.json | 44 ++++++++++------------ .../arch/arm64/arm/cortex-a53/pipeline.json | 20 +++++----- 6 files changed, 62 insertions(+), 92 deletions(-)
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json +6 -8
@@ -1,25 +1,23 @@ [ - {, - "EventCode": "0x7A", - "EventName": "BR_INDIRECT_SPEC", - "BriefDescription": "Branch speculatively executed - Indirect branch" + { + "ArchStdEvent": "BR_INDIRECT_SPEC", }, - {, + { "EventCode": "0xC9", "EventName": "BR_COND", "BriefDescription": "Conditional branch executed" }, - {, + { "EventCode": "0xCA", "EventName": "BR_INDIRECT_MISPRED", "BriefDescription": "Indirect branch mispredicted" }, - {, + { "EventCode": "0xCB", "EventName": "BR_INDIRECT_MISPRED_ADDR", "BriefDescription": "Indirect branch mispredicted because of address miscompare" }, - {, + { "EventCode": "0xCC", "EventName": "BR_COND_MISPRED", "BriefDescription": "Conditional branch mispredicted"
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json +4 -18
@@ -1,22 +1,8 @@ [ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" + { + "ArchStdEvent": "BUS_ACCESS_RD", }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, - "EventCode": "0xC0", - "EventName": "EXT_MEM_REQ", - "BriefDescription": "External memory request" - }, - {, - "EventCode": "0xC1", - "EventName": "EXT_MEM_REQ_NC", - "BriefDescription": "Non-cacheable external memory request" + { + "ArchStdEvent": "BUS_ACCESS_WR", } ]
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json +20 -20
@@ -1,27 +1,27 @@ [ - {, - "EventCode": "0xC2", - "EventName": "PREFETCH_LINEFILL", - "BriefDescription": "Linefill because of prefetch" + { + "EventCode": "0xC2", + "EventName": "PREFETCH_LINEFILL", + "BriefDescription": "Linefill because of prefetch" }, - {, - "EventCode": "0xC3", - "EventName": "PREFETCH_LINEFILL_DROP", - "BriefDescription": "Instruction Cache Throttle occurred" + { + "EventCode": "0xC3", + "EventName": "PREFETCH_LINEFILL_DROP", + "BriefDescription": "Instruction Cache Throttle occurred" }, - {, - "EventCode": "0xC4", - "EventName": "READ_ALLOC_ENTER", - "BriefDescription": "Entering read allocate mode" + { + "EventCode": "0xC4", + "EventName": "READ_ALLOC_ENTER", + "BriefDescription": "Entering read allocate mode" }, - {, - "EventCode": "0xC5", - "EventName": "READ_ALLOC", - "BriefDescription": "Read allocate mode" + { + "EventCode": "0xC5", + "EventName": "READ_ALLOC", + "BriefDescription": "Read allocate mode" }, - {, - "EventCode": "0xC8", - "EventName": "EXT_SNOOP", - "BriefDescription": "SCU Snooped data from another CPU for this CPU" + { + "EventCode": "0xC8", + "EventName": "EXT_SNOOP", + "BriefDescription": "SCU Snooped data from another CPU for this CPU" } ]
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json +2 -12
@@ -1,20 +1,10 @@ [ - {, - "EventCode": "0x60", - "EventName": "BUS_ACCESS_LD", - "BriefDescription": "Bus access - Read" - }, - {, - "EventCode": "0x61", - "EventName": "BUS_ACCESS_ST", - "BriefDescription": "Bus access - Write" - }, - {, + { "EventCode": "0xC0", "EventName": "EXT_MEM_REQ", "BriefDescription": "External memory request" }, - {, + { "EventCode": "0xC1", "EventName": "EXT_MEM_REQ_NC", "BriefDescription": "Non-cacheable external memory request"
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json +20 -24
52 lines not on this page · raw message
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json +10 -10
@@ -1,50 +1,50 @@ [ - {, + { "EventCode": "0xC7", "EventName": "STALL_SB_FULL", "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full" }, - {, + { "EventCode": "0xE0", "EventName": "OTHER_IQ_DEP_STALL", "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error" }, - {, + { "EventCode": "0xE1", "EventName": "IC_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed" }, - {, + { "EventCode": "0xE2", "EventName": "IUTLB_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed" }, - {, + { "EventCode": "0xE3", "EventName": "DECODE_DEP_STALL", "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" }, - {, + { "EventCode": "0xE4", "EventName": "OTHER_INTERLOCK_STALL", "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction" }, - {, + { "EventCode": "0xE5", "EventName": "AGU_DEP_STALL", "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU" }, - {, + { "EventCode": "0xE6", "EventName": "SIMD_DEP_STALL", "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation." }, - {, + { "EventCode": "0xE7", "EventName": "LD_DEP_STALL", "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss" }, - {, + { "EventCode": "0xE8", "EventName": "ST_DEP_STALL", "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 21/31 perf vendor events arm64: add HiSilicon hip08 JSON file
In reply to Arnaldo Carvalho de MeloFrom: John Garry <[email protected]>
This patch adds the HiSilicon hip08 JSON file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable.
--- .../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 +++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 123 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json new file +122 -0
@@ -0,0 +1,122 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_TLB_RD", + }, + { + "ArchStdEvent": "L1D_TLB_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_RD", + }, + { + "ArchStdEvent": "L2D_CACHE_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD", + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL", + }, + { + "PublicDescription": "Level 1 instruction cache prefetch access count", + "EventCode": "0x102e", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "L1I cache prefetch access count", + }, + { + "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", + "EventCode": "0x102f", + "EventName": "L1I_CACHE_PRF_REFILL", + "BriefDescription": "L1I cache miss due to prefetch access count", + }, + { + "PublicDescription": "Instruction queue is empty", + "EventCode": "0x1043", + "EventName": "IQ_IS_EMPTY", + "BriefDescription": "Instruction queue is empty", + }, + { + "PublicDescription": "Instruction fetch stall cycles", + "EventCode": "0x1044", + "EventName": "IF_IS_STALL", + "BriefDescription": "Instruction fetch stall cycles", + }, + { + "PublicDescription": "Instructions can receive, but not send", + "EventCode": "0x2014", + "EventName": "FETCH_BUBBLE", + "BriefDescription": "Instructions can receive, but not send", + }, + { + "PublicDescription": "Prefetch request from LSU", + "EventCode": "0x6013", + "EventName": "PRF_REQ", + "BriefDescription": "Prefetch request from LSU", + }, + { + "PublicDescription": "Hit on prefetched data", + "EventCode": "0x6014", + "EventName": "HIT_ON_PRF", + "BriefDescription": "Hit on prefetched data", + }, + { + "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", + "EventCode": "0x7001", + "EventName": "EXE_STALL_CYCLE", + "BriefDescription": "Cycles of that the number of issue ups are less than 4", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + "EventCode": "0x7004", + "EventName": "MEM_STALL_ANYLOAD", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + "EventCode": "0x7006", + "EventName": "MEM_STALL_L1MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + "EventCode": "0x7007", + "EventName": "MEM_STALL_L2MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + }, +]
tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -0
@@ -14,3 +14,4 @@ #Family-model,Version,Filename,EventType 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core +0x00000000480fd010,v1,hisilicon/hip08,core
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 22/31 perf stat: Fix core dump when flag T is used
In reply to Arnaldo Carvalho de MeloFrom: Thomas Richter <[email protected]>
Executing command 'perf stat -T -- ls' dumps core on x86 and s390.
Here is the call back chain (done on x86):
# gdb ./perf
....
(gdb) r stat -T -- ls
...
Program received signal SIGSEGV, Segmentation fault.
0x00007ffff56d1963 in vasprintf () from /lib64/libc.so.6
(gdb) where
#0 0x00007ffff56d1963 in vasprintf () from /lib64/libc.so.6
#1 0x00007ffff56ae484 in asprintf () from /lib64/libc.so.6
#2 0x00000000004f1982 in __parse_events_add_pmu (parse_state=0x7fffffffd580,
list=0xbfb970, name=0xbf3ef0 "cpu",
head_config=0xbfb930, auto_merge_stats=false) at util/parse-events.c:1233
#3 0x00000000004f1c8e in parse_events_add_pmu (parse_state=0x7fffffffd580,
list=0xbfb970, name=0xbf3ef0 "cpu",
head_config=0xbfb930) at util/parse-events.c:1288
#4 0x0000000000537ce3 in parse_events_parse (_parse_state=0x7fffffffd580,
scanner=0xbf4210) at util/parse-events.y:234
#5 0x00000000004f2c7a in parse_events__scanner (str=0x6b66c0
"task-clock,{instructions,cycles,cpu/cycles-t/,cpu/tx-start/}",
parse_state=0x7fffffffd580, start_token=258) at util/parse-events.c:1673
#6 0x00000000004f2e23 in parse_events (evlist=0xbe9990, str=0x6b66c0
"task-clock,{instructions,cycles,cpu/cycles-t/,cpu/tx-start/}", err=0x0)
at util/parse-events.c:1713
#7 0x000000000044e137 in add_default_attributes () at builtin-stat.c:2281
#8 0x000000000044f7b5 in cmd_stat (argc=1, argv=0x7fffffffe3b0) at
builtin-stat.c:2828
#9 0x00000000004c8b0f in run_builtin (p=0xab01a0 <commands+288>, argc=4,
argv=0x7fffffffe3b0) at perf.c:297
#10 0x00000000004c8d7c in handle_internal_command (argc=4,
argv=0x7fffffffe3b0) at perf.c:349
#11 0x00000000004c8ece in run_argv (argcp=0x7fffffffe20c,
argv=0x7fffffffe200) at perf.c:393
#12 0x00000000004c929c in main (argc=4, argv=0x7fffffffe3b0) at perf.c:537
(gdb)It turns out that a NULL pointer is referenced. Here are the function calls:
...
cmd_stat()
+---> add_default_attributes() +---> parse_events(evsel_list, transaction_attrs, NULL);
3rd parameter set to NULL
Function parse_events(xx, xx, struct parse_events_error *err) dives into a bison generated scanner and creates
parser state information for it first:
struct parse_events_state parse_state = {
.list = LIST_HEAD_INIT(parse_state.list),
.idx = evlist->nr_entries,
.error = err, <--- NULL POINTER !!!
.evlist = evlist,
};Now various functions inside the bison scanner are called to end up in __parse_events_add_pmu(struct parse_events_state *parse_state, ..) with first parameter being a pointer to above structure definition.
Now the PMU event name is not found (because being executed in a VM) and this function tries to create an error message with
asprintf(&parse_state->error.str, ....)
which references a NULL pointer and dumps core.
Fix this by providing a pointer to the necessary error information instead of NULL. Technically only the else part is needed to avoid the core dump, just lets be safe...
--- tools/perf/builtin-stat.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
tools/perf/builtin-stat.c +7 -2
@@ -2331,11 +2331,16 @@ static int add_default_attributes(void)return 0 ;if (transaction_run) { +struct parse_events_error errinfo; +if (pmu_have_event ("cpu" ,"cycles-ct" ) &&pmu_have_event ("cpu" ,"el-start" )) - err =parse_events (evsel_list, transaction_attrs,NULL ); + err =parse_events (evsel_list, transaction_attrs, + &errinfo);else - err =parse_events (evsel_list, transaction_limited_attrs,NULL ); + err =parse_events (evsel_list, + transaction_limited_attrs, + &errinfo);if (err) {fprintf (stderr,"Cannot set up transaction events\n" );return -1 ;
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 23/31 perf report: Show zero counters as well in 'perf report --stat'
In reply to Arnaldo Carvalho de MeloFrom: Ingo Molnar <[email protected]>
When recently using 'perf report --stat' it was not clear to me from the output whether a particular statistics field (LOST_SAMPLES) was not present, or just zero:
fomalhaut:~> perf report --stat
Aggregated stats:
TOTAL events: 495984
MMAP events: 85
COMM events: 3389
EXIT events: 1605
THROTTLE events: 2
UNTHROTTLE events: 2
FORK events: 3377
SAMPLE events: 472629
MMAP2 events: 14753
FINISHED_ROUND events: 139
THREAD_MAP events: 1
CPU_MAP events: 1
TIME_CONV events: 1I had to check the output several times to ascertain that I'm not misreading the output, that the field didn't change and that I didn't misremember the name. In fact I had to look into the perf source to make sure that zero fields are indeed not shown.
With the patch applied:
fomalhaut:~> perf report --stat
Aggregated stats:
TOTAL events: 495984
MMAP events: 85
LOST events: 0
COMM events: 3389
EXIT events: 1605
THROTTLE events: 2
UNTHROTTLE events: 2
FORK events: 3377
READ events: 0
SAMPLE events: 472629
MMAP2 events: 14753
AUX events: 0
ITRACE_START events: 0
LOST_SAMPLES events: 0
SWITCH events: 0
SWITCH_CPU_WIDE events: 0
NAMESPACES events: 0
ATTR events: 0
EVENT_TYPE events: 0
TRACING_DATA events: 0
BUILD_ID events: 0
FINISHED_ROUND events: 139
ID_INDEX events: 0
AUXTRACE_INFO events: 0
AUXTRACE events: 0
AUXTRACE_ERROR events: 0
THREAD_MAP events: 1
CPU_MAP events: 1
STAT_CONFIG events: 0
STAT events: 0
STAT_ROUND events: 0
EVENT_UPDATE events: 0
TIME_CONV events: 1
FEATURE events: 0It's pretty clear at a glance that LOST_SAMPLES is present but zero.
The original output can still be gotten via:
fomalhaut:~> perf report --stat | grep -vw 0
Aggregated stats:
TOTAL events: 495984
MMAP events: 85
COMM events: 3389
EXIT events: 1605
THROTTLE events: 2
UNTHROTTLE events: 2
FORK events: 3377
SAMPLE events: 472629
MMAP2 events: 14753
FINISHED_ROUND events: 139
THREAD_MAP events: 1
CPU_MAP events: 1
TIME_CONV events: 1So I don't think there's any real loss in functionality.
--- tools/perf/ui/stdio/hist.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)
tools/perf/ui/stdio/hist.c +1 -5
@@ -840,15 +840,11 @@ size_t events_stats__fprintf(struct events_stats *stats, FILE *fp)for (i =0 ; i <PERF_RECORD_HEADER_MAX ; ++i) {const char *name; -if (stats->nr_events[i] ==0 ) -continue ; - name =perf_event__name (i);if (!strcmp (name,"UNKNOWN" ))continue ; - ret +=fprintf (fp,"%16s events: %10d\n" , name, - stats->nr_events[i]); + ret +=fprintf (fp,"%16s events: %10d\n" , name, stats->nr_events[i]); }return ret;
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 24/31 perf vendor events arm64: Enable JSON events for ThunderX2 B0
In reply to Arnaldo Carvalho de MeloFrom: Ganapatrao Kulkarni <[email protected]>
There is MIDR change on ThunderX2 B0, adding an entry to mapfile to enable JSON events for B0.
--- tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 1 file changed, 1 insertion(+)
tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -0
@@ -14,4 +14,5 @@ #Family-model,Version,Filename,EventType 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core +0x00000000430f0af0,v1,cavium/thunderx2,core 0x00000000480fd010,v1,hisilicon/hip08,core
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 25/31 perf unwind: Unwind with libdw doesn't take symfs into account
In reply to Arnaldo Carvalho de MeloFrom: Martin Vuille <[email protected]>
Path passed to libdw for unwinding doesn't include symfs path if specified, so unwinding fails because ELF file is not found.
Similar to unwinding with libunwind, pass symsrc_filename instead of long_name. If there is no symsrc_filename, fallback to long_name.
--- tools/perf/util/unwind-libdw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
tools/perf/util/unwind-libdw.c +1 -1
@@ -50,7 +50,7 @@ static int __report_module(struct addr_location *al, u64 ip,if (!mod) mod =dwfl_report_elf (ui->dwfl, dso->short_name, - dso->long_name,-1 , al->map->start, + (dso->symsrc_filename ? dso->symsrc_filename : dso->long_name),-1 , al->map->start, false);return mod &&dwfl_addrmodule (ui->dwfl, ip) == mod ?0 :-1 ;
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 26/31 perf record: Avoid duplicate call of perf_default_config()
In reply to Arnaldo Carvalho de MeloFrom: Yisheng Xie <[email protected]>
We have brought perf_default_config to the very beginning at main(), so it no need to call perf_default_config() once more for most of config in perf-record but only for record.call-graph.
--- tools/perf/builtin-record.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
tools/perf/builtin-record.c +5 -3
@@ -1279,10 +1279,12 @@ static int perf_record_config(const char *var, const char *value, void *cb)return -1 ;return 0 ; } -if (!strcmp (var,"record.call-graph" )) - var ="call-graph.record-mode" ;/* fall-through */ +if (!strcmp (var,"record.call-graph" )) { + var ="call-graph.record-mode" ; +return perf_default_config (var, value, cb); + } -return perf_default_config (var, value, cb); +return 0 ; }struct clockid_map {
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 27/31 perf top: Fix top.call-graph config option reading
In reply to Arnaldo Carvalho de MeloFrom: Yisheng Xie <[email protected]>
When trying to add the "call-graph" variable for top into the .perfconfig file, like:
[top]
call-graph = fp
I that perf_top_config() do not parse this variable.
Fix it by calling perf_default_config() when the top.call-graph variable is set.
--- tools/perf/builtin-top.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
tools/perf/builtin-top.c +4 -2
@@ -1223,8 +1223,10 @@ parse_callchain_opt(const struct option *opt, const char *arg, int unset)static int perf_top_config (const char *var,const char *value,void *cb__maybe_unused ) { -if (!strcmp (var,"top.call-graph" )) - var ="call-graph.record-mode" ;/* fall-through */ +if (!strcmp (var,"top.call-graph" )) { + var ="call-graph.record-mode" ; +return perf_default_config (var, value, cb); + }if (!strcmp (var,"top.children" )) { symbol_conf.cumulate_callchain =perf_config_bool (var, value);return 0 ;
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 28/31 perf llvm: Display eBPF compiling command in debug output
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
In addition to template, display also the real compile command line with all the variables substituted.
llvm compiling command template: $CLANG_EXEC -D__KERNEL__ -D__NR_CPUS__=$NR_CPUS ... llvm compiling command : /usr/bin/clang -D__KERNEL__ -D__NR_CPUS__=24 -DLINUX_VERSION_CODE=0x41000 ...
--- tools/perf/util/llvm-utils.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
tools/perf/util/llvm-utils.c +14 -0
@@ -433,6 +433,7 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf,char serr[STRERR_BUFSIZE ];char *kbuild_dir =NULL , *kbuild_include_opts =NULL ;const char *template = llvm_param.clang_bpf_cmd_template; +char *command_echo, *command_out;if (path[0 ] !='-' &&realpath (path, abspath) ==NULL ) { err = errno;
@@ -487,6 +488,16 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf, (path[0] == '-') ? path : abspath);pr_debug ("llvm compiling command template: %s\n" , template); + +if (asprintf (&command_echo,"echo -n \"%s\"" , template) <0 ) + goto errout; + + err =read_from_pipe (command_echo, (void **) &command_out,NULL ); +if (err) + goto errout; + +pr_debug ("llvm compiling command : %s\n" , command_out); + err =read_from_pipe (template, &obj_buf, &obj_buf_sz);if (err) {pr_err ("ERROR:\tunable to compile %s\n" , path);
@@ -497,6 +508,8 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf, goto errout; } +free (command_echo); +free (command_out);free (kbuild_dir);free (kbuild_include_opts);
@@ -509,6 +522,7 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf, *p_obj_buf_sz = obj_buf_sz;return 0 ; errout: +free (command_echo);free (kbuild_dir);free (kbuild_include_opts);free (obj_buf);
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 29/31 perf stat: Make function perf_stat_evsel_id_init static
In reply to Arnaldo Carvalho de MeloFrom: Thomas Richter <[email protected]>
Function perf_stat_evsel_id_init() has global linkage but is only used in util/stat.c. Make it static.
--- tools/perf/util/stat.c | 2 +- tools/perf/util/stat.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-)
tools/perf/util/stat.c +1 -1
@@ -92,7 +92,7 @@ static const char *id_str[PERF_STAT_EVSEL_ID__MAX] = { };#undef ID -void perf_stat_evsel_id_init (struct perf_evsel *evsel) +static void perf_stat_evsel_id_init (struct perf_evsel *evsel) {struct perf_stat_evsel *ps = evsel->stats;int i;
tools/perf/util/stat.h +0 -2
@@ -128,8 +128,6 @@ bool __perf_evsel_stat__is(struct perf_evsel *evsel,#define perf_stat_evsel__is (evsel, id) \ __perf_evsel_stat__is(evsel, PERF_STAT_EVSEL_ID__ ## id) -void perf_stat_evsel_id_init (struct perf_evsel *evsel); -extern struct runtime_stat rt_stat;extern struct stats walltime_nsecs_stats;
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 30/31 perf machine: Fix mmap name setup
In reply to Arnaldo Carvalho de MeloFrom: Jiri Olsa <[email protected]>
Leo reported broken -k option behavior. The reason is that we used symbol_conf.vmlinux_name as a source for mmap event name, but in fact it's a vmlinux path.
Moving the symbol_conf.vmlinux_name check for both host and guest to the proper place and out of the machine__set_mmap_name function.
--- tools/perf/util/machine.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-)
tools/perf/util/machine.c +13 -15
@@ -50,21 +50,13 @@ static void machine__threads_init(struct machine *machine)static int machine__set_mmap_name (struct machine *machine) { -if (machine__is_host (machine)) { -if (symbol_conf.vmlinux_name) - machine->mmap_name =strdup (symbol_conf.vmlinux_name); -else - machine->mmap_name =strdup ("[kernel.kallsyms]" ); - }else if (machine__is_default_guest (machine)) { -if (symbol_conf.default_guest_vmlinux_name) - machine->mmap_name =strdup (symbol_conf.default_guest_vmlinux_name); -else - machine->mmap_name =strdup ("[guest.kernel.kallsyms]" ); - }else { -if (asprintf (&machine->mmap_name,"[guest.kernel.kallsyms.%d]" , - machine->pid) <0 ) - machine->mmap_name =NULL ; - } +if (machine__is_host (machine)) + machine->mmap_name =strdup ("[kernel.kallsyms]" ); +else if (machine__is_default_guest (machine)) + machine->mmap_name =strdup ("[guest.kernel.kallsyms]" ); +else if (asprintf (&machine->mmap_name,"[guest.kernel.kallsyms.%d]" , + machine->pid) <0 ) + machine->mmap_name =NULL ;return machine->mmap_name ?0 : -ENOMEM ; }
@@ -794,9 +786,15 @@ static struct dso *machine__get_kernel(struct machine *machine)struct dso *kernel;if (machine__is_host (machine)) { +if (symbol_conf.vmlinux_name) + vmlinux_name = symbol_conf.vmlinux_name; + kernel =machine__findnew_kernel (machine, vmlinux_name,"[kernel]" ,DSO_TYPE_KERNEL ); }else { +if (symbol_conf.default_guest_vmlinux_name) + vmlinux_name = symbol_conf.default_guest_vmlinux_name; + kernel =machine__findnew_kernel (machine, vmlinux_name,"[guest.kernel]" ,DSO_TYPE_GUEST_KERNEL );
Signature · 1 line
2.14.3
Arnaldo Carvalho de Melo
maintainerPATCH 31/31 perf test: Fix exit code for record+probe_libc_inet_pton.sh
In reply to Arnaldo Carvalho de MeloFrom: Sandipan Das <[email protected]>
This fixes record+probe_libc_inet_pton.sh from always exiting with code 0 and making the test pass even if the perf script output does not match the expected pattern.
The issue can be observed if this test is run with the verbose flags as shown below:
60: probe libc's inet_pton & backtrace it with ping :
...
ping 19602 [006] 16988.413767: probe_libc:inet_pton: (7fff9a2c42e8) 1842e8 __GI___inet_pton (/usr/lib64/libc-2.26.so)
130db4 getaddrinfo (/usr/lib64/libc-2.26.so)
FAIL: expected backtrace entry 3 ".*\(.*/bin/ping.*\)$" got "" test child finished with 0
...
probe libc's inet_pton & backtrace it with ping: Ok
--- tools/perf/tests/shell/record+probe_libc_inet_pton.sh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
tools/perf/tests/shell/record+probe_libc_inet_pton.sh +4 -1
@@ -47,7 +47,10 @@ trace_libc_inet_pton_backtrace() { [ -z "${expected[$idx]}" ] && break done - rm -f $file + # If any statements are executed from this point onwards, + # the exit code of the last among these will be reflected + # in err below. If the exit code is 0, the test will pass + # even if the perf script output does not match. } # Check for IPv6 interface existence
Signature · 1 line
2.14.3