Add the registers clock for most of the peripherals

PATCH New Gregory CLEMENT 1 participant 9 messages Mar 14, 2018 – Mar 19, 2018

Subsystems (2)

Device tree bindings Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support

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Gregory CLEMENT

author maintainer

2018-03-14 16:19 UTC #0 lore raw

cover Add the registers clock for most of the peripherals

Hi,

Thanks to new documentation, we have a better view of the clock tree. It made us realized that most of the peripherals needs a second clock to enable their registers.

Now that most of the binding change had been applied or are in the way to be applied, we can update the device tree.

Gregory

Gregory CLEMENT (6):
ARM64: dts: marvell: armada-cp110: Add registers clock for USB host
nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine
nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for the trng
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe
nodes

 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 37 +++++++++++++++++++--------
 1 file changed, 27 insertions(+), 10 deletions(-)

Signature · 1 line

2.16.1

Gregory CLEMENT

author maintainer

2018-03-14 16:19 UTC #1 lore raw

PATCH 1/6 ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodes

This extra clock is needed to access the registers of the USB host controller used on Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as well as in the driver): "usb: host: xhci-plat: Fix clock resource by adding a register clock"

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110.dtsi +6 -2

index 355bb295e4d9..c35368d2a4cd 100644
@@ -211,7 +211,9 @@
 			reg = <0x500000 0x4000>;
 			dma-coherent;
 			interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&CP110_LABEL(clk) 1 22>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 22>,
+				 <&CP110_LABEL(clk) 1 16>;
 			status = "disabled";
 		};

@@ -221,7 +223,9 @@
 			reg = <0x510000 0x4000>;
 			dma-coherent;
 			interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&CP110_LABEL(clk) 1 23>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 23>,
+				 <&CP110_LABEL(clk) 1 16>;
 			status = "disabled";
 		};

Signature · 1 line

2.16.1

Gregory CLEMENT

author maintainer

2018-03-14 16:19 UTC #2 lore raw

PATCH 2/6 ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes

In reply to Gregory CLEMENT

This extra clock is needed to access the registers of the XOR engine controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by adding a register clock"

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110.dtsi +6 -2

index c35368d2a4cd..a51c553b5120 100644
@@ -244,7 +244,9 @@
 			reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
 			dma-coherent;
 			msi-parent = <&gic_v2m0>;
-			clocks = <&CP110_LABEL(clk) 1 8>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 8>,
+				 <&CP110_LABEL(clk) 1 14>;
 		};
 
 		CP110_LABEL(xor1): xor at 6c0000 {

@@ -252,7 +254,9 @@
 			reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
 			dma-coherent;
 			msi-parent = <&gic_v2m0>;
-			clocks = <&CP110_LABEL(clk) 1 7>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 7>,
+				 <&CP110_LABEL(clk) 1 14>;
 		};
 
 		CP110_LABEL(spi0): spi at 700600 {

Signature · 1 line

2.16.1

Gregory CLEMENT

author maintainer

2018-03-14 16:19 UTC #3 lore raw

PATCH 3/6 ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node

In reply to Gregory CLEMENT

This extra clock is needed to access the registers of the harware RNG used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as well as in the driver): "hwrng: omap - Fix clock resource by adding a register clock"

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

arch/arm64/boot/dts/marvell/armada-cp110.dtsi +3 -1

index a51c553b5120..c491adc90b8c 100644
@@ -375,7 +375,9 @@
 			"inside-secure,safexcel-eip76";
 			reg = <0x760000 0x7d>;
 			interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&CP110_LABEL(clk) 1 25>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 25>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "okay";
 		};

Signature · 1 line

2.16.1

Gregory CLEMENT

author maintainer

2018-03-14 16:19 UTC #4 lore raw

PATCH 4/6 ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node

In reply to Gregory CLEMENT

This extra clock is needed to access the registers of the safexcel EIP97 used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as well as in the driver): "crypto: inside-secure - fix clock resource by adding a register clock"

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

arch/arm64/boot/dts/marvell/armada-cp110.dtsi +3 -1

index c491adc90b8c..b6947fcb8ce6 100644
@@ -402,7 +402,9 @@
 				<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mem", "ring0", "ring1",
 				"ring2", "ring3", "eip";
-			clocks = <&CP110_LABEL(clk) 1 26>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 26>,
+				 <&CP110_LABEL(clk) 1 17>;
 			dma-coherent;
 		};
 	};

Signature · 1 line

2.16.1

Gregory CLEMENT

author maintainer

2018-03-14 16:19 UTC #5 lore raw

PATCH 5/6 ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node

In reply to Gregory CLEMENT

This extra clock is needed to access the registers of the NAND controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as well as in the driver): "mtd: nand: marvell: Fix clock resource by adding a register clock"

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

arch/arm64/boot/dts/marvell/armada-cp110.dtsi +3 -1

index b6947fcb8ce6..9ffb86b9441e 100644
@@ -365,7 +365,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&CP110_LABEL(clk) 1 2>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 2>,
+				 <&CP110_LABEL(clk) 1 17>;
 			marvell,system-controller = <&CP110_LABEL(syscon0)>;
 			status = "disabled";
 		};

Signature · 1 line

2.16.1

Gregory CLEMENT

author maintainer

2018-03-14 16:19 UTC #6 lore raw

PATCH 6/6 ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes

In reply to Gregory CLEMENT

This extra clock is needed to access the registers of the PCIe host controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as well as in the driver): "PCI: armada8k: Fix clock resource by adding a register clock"

Signed-off-by Gregory CLEMENT <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

arch/arm64/boot/dts/marvell/armada-cp110.dtsi +6 -3

index 9ffb86b9441e..48cad7919efa 100644
@@ -433,7 +433,8 @@
 		interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 		interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 		num-lanes = <1>;
-		clocks = <&CP110_LABEL(clk) 1 13>;
+		clock-names = "core", "reg";
+		clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
 		status = "disabled";
 	};

@@ -460,7 +461,8 @@
 		interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 
 		num-lanes = <1>;
-		clocks = <&CP110_LABEL(clk) 1 11>;
+		clock-names = "core", "reg";
+		clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
 		status = "disabled";
 	};

@@ -487,7 +489,8 @@
 		interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 
 		num-lanes = <1>;
-		clocks = <&CP110_LABEL(clk) 1 12>;
+		clock-names = "core", "reg";
+		clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
 		status = "disabled";
 	};
 };

Signature · 1 line

2.16.1

Gregory CLEMENT

author maintainer

2018-03-14 16:22 UTC #7 lore raw

cover Add the registers clock for most of the peripherals

In reply to Gregory CLEMENT

Hi,

Quoted 5 lines · Gregory CLEMENT

Hi,
Thanks to new documentation, we have a better view of the clock tree. It made us realized that most of the peripherals needs a second clock to enable their registers.

I forgot to mention that this series was for the Armada 7K/8K SoCs from Marvell!

Quoted 31 lines

Now that most of the binding change had been applied or are in the way to be applied, we can update the device tree.
Gregory
Gregory CLEMENT (6):
ARM64: dts: marvell: armada-cp110: Add registers clock for USB host
nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine
nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for the trng
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe
nodes
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 37 +++++++++++++++++++--------
 1 file changed, 27 insertions(+), 10 deletions(-)
Signature · 7 lines
2.16.1


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Signature · 3 lines

Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

Gregory CLEMENT

author maintainer

2018-03-19 16:16 UTC #8 lore raw

cover Add the registers clock for most of the peripherals

In reply to Gregory CLEMENT

Hi,

Quoted 9 lines · Gregory CLEMENT

Hi,
Thanks to new documentation, we have a better view of the clock tree. It made us realized that most of the peripherals needs a second clock to enable their registers.
Now that most of the binding change had been applied or are in the way to be applied, we can update the device tree.

All series applied on mvebu/dt64,

Gregory

Quoted 22 lines

Gregory
Gregory CLEMENT (6):
ARM64: dts: marvell: armada-cp110: Add registers clock for USB host
nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine
nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for the trng
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND
node
ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe
nodes
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 37 +++++++++++++++++++--------
 1 file changed, 27 insertions(+), 10 deletions(-)
Signature · 1 line
2.16.1

Signature · 3 lines

Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com