arm: stm32mp1: add initial support for STM32MP157
Subsystems (9)
v2 cover arm: stm32mp1: add initial support for STM32MP157
This patch-set adds initial support of STMicroelectronics STM32MP157 microprocessor (MPU)
- add new arm arch stm32mp1 (based on armv7)
- support for stm32mp157 SOC (based on Cortex-A7)
- add minimal support for board evaluation board STM32MP157C-ED1
Changes in v2:
- prototype for mach_cpu_init() removed for the Serie
- rebase on v2018.03-rc4
- remove include of "config_distro_defaults.h"
Patrick Delaunay (15):
tools/mkimage: add support for STM32 image format
spl: add SPL_RESET_SUPPORT
arm: armv7: solve issue for timer_rate_hz in arch timer
dm: gpio: Convert stm32f7 driver to livetree
gpio: stm32f7_gpio: handle node ngpios
stm32mp: stm32f7_i2c: use calloc instead of kmalloc
arm: stm32: add new architecture for STM32MP family
ram: stm32mp1: add driver
pmic: add stpmu1 support
pinctrl: stm32: update pincontrol for stmp32mp157
reset: stm32: adapt driver for stm32mp1
clk: add driver for stm32mp1
clk: stm32mp1: add clock tree initialization
dts: add device tree for STM32MP157C-ED1 board
board: st: add generic board for STM32MP1 family
MAINTAINERS | 7 + arch/arm/Kconfig | 25 +- arch/arm/Makefile | 1 + arch/arm/cpu/armv7/arch_timer.c | 22 +- arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp15-ddr.dtsi | 155 ++ arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 122 ++ arch/arm/dts/stm32mp157-u-boot.dtsi | 134 ++ arch/arm/dts/stm32mp157.dtsi | 303 ++++ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 133 ++ arch/arm/dts/stm32mp157c-ed1.dts | 167 ++ arch/arm/mach-stm32mp/Kconfig | 43 + arch/arm/mach-stm32mp/Makefile | 10 + arch/arm/mach-stm32mp/config.mk | 14 + arch/arm/mach-stm32mp/cpu.c | 139 ++ arch/arm/mach-stm32mp/dram_init.c | 34 + arch/arm/mach-stm32mp/include/mach/ddr.h | 12 + arch/arm/mach-stm32mp/include/mach/gpio.h | 115 ++ arch/arm/mach-stm32mp/include/mach/stm32.h | 27 + arch/arm/mach-stm32mp/spl.c | 60 + board/st/stm32mp1/Kconfig | 12 + board/st/stm32mp1/MAINTAINERS | 7 + board/st/stm32mp1/Makefile | 13 + board/st/stm32mp1/README | 191 +++ board/st/stm32mp1/board.c | 75 + board/st/stm32mp1/spl.c | 33 + board/st/stm32mp1/stm32mp1.c | 27 + common/image.c | 1 + common/spl/Kconfig | 9 + configs/stm32mp15_basic_defconfig | 36 + doc/device-tree-bindings/clock/st,stm32mp1.txt | 226 +++ doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt | 299 ++++ drivers/Makefile | 1 + drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk_stm32mp1.c | 1733 ++++++++++++++++++++ drivers/gpio/Kconfig | 2 +- drivers/gpio/stm32f7_gpio.c | 15 +- drivers/i2c/Kconfig | 2 +- drivers/i2c/stm32f7_i2c.c | 4 +- drivers/pinctrl/pinctrl_stm32.c | 9 +- drivers/power/pmic/Kconfig | 8 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/stpmu1.c | 62 + drivers/ram/Kconfig | 2 + drivers/ram/Makefile | 1 + drivers/ram/stm32mp1/Kconfig | 12 + drivers/ram/stm32mp1/Makefile | 8 + drivers/ram/stm32mp1/stm32mp1_ddr.c | 496 ++++++ drivers/ram/stm32mp1/stm32mp1_ddr.h | 210 +++ drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 365 +++++ drivers/ram/stm32mp1/stm32mp1_ram.c | 197 +++ drivers/reset/Kconfig | 2 +- drivers/reset/stm32-reset.c | 36 +- drivers/serial/Kconfig | 6 +- include/configs/stm32mp1.h | 96 ++ include/dt-bindings/clock/stm32mp1-clks.h | 243 +++ include/dt-bindings/clock/stm32mp1-clksrc.h | 284 ++++ .../dt-bindings/reset-controller/stm32mp1-resets.h | 97 ++ include/image.h | 1 + include/power/stpmu1.h | 85 + tools/Makefile | 1 + tools/stm32image.c | 148 ++ 63 files changed, 6544 insertions(+), 47 deletions(-) create mode 100644 arch/arm/dts/stm32mp15-ddr.dtsi create mode 100644 arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi create mode 100644 arch/arm/dts/stm32mp157-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157.dtsi create mode 100644 arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157c-ed1.dts create mode 100644 arch/arm/mach-stm32mp/Kconfig create mode 100644 arch/arm/mach-stm32mp/Makefile create mode 100644 arch/arm/mach-stm32mp/config.mk create mode 100644 arch/arm/mach-stm32mp/cpu.c create mode 100644 arch/arm/mach-stm32mp/dram_init.c create mode 100644 arch/arm/mach-stm32mp/include/mach/ddr.h create mode 100644 arch/arm/mach-stm32mp/include/mach/gpio.h create mode 100644 arch/arm/mach-stm32mp/include/mach/stm32.h create mode 100644 arch/arm/mach-stm32mp/spl.c create mode 100644 board/st/stm32mp1/Kconfig create mode 100644 board/st/stm32mp1/MAINTAINERS create mode 100644 board/st/stm32mp1/Makefile create mode 100644 board/st/stm32mp1/README create mode 100644 board/st/stm32mp1/board.c create mode 100644 board/st/stm32mp1/spl.c create mode 100644 board/st/stm32mp1/stm32mp1.c create mode 100644 configs/stm32mp15_basic_defconfig create mode 100644 doc/device-tree-bindings/clock/st,stm32mp1.txt create mode 100644 doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt create mode 100644 drivers/clk/clk_stm32mp1.c create mode 100644 drivers/power/pmic/stpmu1.c create mode 100644 drivers/ram/stm32mp1/Kconfig create mode 100644 drivers/ram/stm32mp1/Makefile create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr.c create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr.h create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr_regs.h create mode 100644 drivers/ram/stm32mp1/stm32mp1_ram.c create mode 100644 include/configs/stm32mp1.h create mode 100644 include/dt-bindings/clock/stm32mp1-clks.h create mode 100644 include/dt-bindings/clock/stm32mp1-clksrc.h create mode 100644 include/dt-bindings/reset-controller/stm32mp1-resets.h create mode 100644 include/power/stpmu1.h create mode 100644 tools/stm32image.c
Signature · 1 line
2.7.4
PATCH v2 1/15 tools/mkimage: add support for STM32 image format
STM32MP157 bootrom needs a specific header for first boot stage. This patch adds support of this header in mkimage.
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2:
- prototype for mach_cpu_init() removed for the Serie
- rebase on v2018.03-rc4
common/image.c | 1 + include/image.h | 1 + tools/Makefile | 1 + tools/stm32image.c | 148 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 151 insertions(+) create mode 100644 tools/stm32image.c
common/image.c +1 -0
@@ -161,6 +161,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_TEE, "tee", "Trusted Execution Environment Image",}, { IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" }, { IH_TYPE_PMMC, "pmmc", "TI Power Management Micro-Controller Firmware",}, + { IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" }, { -1, "", "", }, };
include/image.h +1 -0
@@ -272,6 +272,7 @@ enum {IH_TYPE_TEE ,/* Trusted Execution Environment OS Image */ IH_TYPE_FIRMWARE_IVT ,/* Firmware Image with HABv4 IVT */ IH_TYPE_PMMC ,/* TI Power Management Micro-Controller Firmware */ +IH_TYPE_STM32IMAGE ,/* STMicroelectronics STM32 Image */ IH_TYPE_COUNT, /* Number of image types */ };
tools/Makefile +1 -0
@@ -103,6 +103,7 @@ dumpimage-mkimage-objs := aisimage.o \ pblimage.o \ pbl_crc32.o \ vybridimage.o \ + stm32image.o \ $(ROCKCHIP_OBS) \ socfpgaimage.o \ lib/sha1.o \
tools/stm32image.c new file +148 -0
148 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v2 1/15 tools/mkimage: add support for STM32 image format
Quoted 4 lines · Patrick Delaunay
STM32MP157 bootrom needs a specific header for first boot stage. This patch adds support of this header in mkimage.
Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 2/15 spl: add SPL_RESET_SUPPORT
In reply to Patrick DelaunayAdd option to include RESET driver and uclass in SPL. That can be useful to handle IP reset with same driver in U-Boot and in SPL.
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)
common/spl/Kconfig +9 -0
@@ -568,6 +568,15 @@ config SPL_POST_MEM_SUPPORT performed before booting. This enables the drivers in post/drivers as part of an SPL build. +config SPL_RESET_SUPPORT + bool "Support reset drivers" + depends on SPL + help + Enable support for reset control in SPL. + That can be useful in SPL to handle IP reset in driver, as in U-Boot, + by using the generic reset API provided by driver model. + This enables the drivers in drivers/reset as part of an SPL build. + config SPL_POWER_SUPPORT bool "Support power drivers" help
drivers/Makefile +1 -0
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ +obj-$(CONFIG_SPL_RESET_SUPPORT) += reset/ obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/ obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/ obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
Signature · 1 line
2.7.4
PATCH v2 2/15 spl: add SPL_RESET_SUPPORT
Quoted 5 lines · Patrick Delaunay
Add option to include RESET driver and uclass in SPL. That can be useful to handle IP reset with same driver in U-Boot and in SPL.
Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 3/15 arm: armv7: solve issue for timer_rate_hz in arch timer
In reply to Patrick DelaunayThe current value timer_rate_hz causes a problem with function timer_get_us() from lib time and then an issue with readx_poll_timeout() function.
With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK the weak functions in lib timer can be used:
- get_timer()
- __udelay()
So the specific function in this file are removed.
Signed-off-by Patrick Delaunay <[email protected]>
---
this patch avoid issue in driver with readl_poll_timeout()
Following source code has been used to demonstrate the issue (with CONFIG_SYS_HZ_CLOCK = 64 MHz)
printf("Tick= %llx us=%lx boot us=%lx\n",
get_ticks(), timer_get_us(), timer_get_boot_us());
mdelay(1000);
printf("Tick= %llx us=%lx boot us=%lx\n",
get_ticks(), timer_get_us(), timer_get_boot_us());Result:
Tick= 36fad40 us=35b0f45f boot us=dbeb8
Tick= 743b21e us=7181c02e boot us=1d0ecb
=> 1000ms : 0x1d0ecb-0xdbeb8 = 0xF5013
for timer_get_boot_us = 1000000 us
=> timer_get_boot_us is OK
=> 1000ms : 0x7181c02e-0x35b0f45f = 0x3BD0CBCF = 1.000.000.000 us
for timer_get_us() which gives a invalid value (based on CONFIG_SYS_HZ and get_tbclk())
This patch resolves the issue.
Changes in v2: None
arch/arm/cpu/armv7/arch_timer.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-)
arch/arm/cpu/armv7/arch_timer.c +2 -20
@@ -17,7 +17,7 @@ int timer_init(void) gd->arch.tbl =0 ; gd->arch.tbu =0 ; - gd->arch.timer_rate_hz =CONFIG_SYS_HZ_CLOCK /CONFIG_SYS_HZ ; + gd->arch.timer_rate_hz =CONFIG_SYS_HZ_CLOCK ;return 0 ; }
@@ -34,27 +34,9 @@ unsigned long long get_ticks(void) } -ulong get_timer (ulong base) -{ -return lldiv (get_ticks (), gd->arch.timer_rate_hz) - base; -} -ulong timer_get_boot_us (void ) { -return lldiv (get_ticks (),CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ *1000 )); -} - -void __udelay (unsigned long usec) -{ -unsigned long long endtime; - - endtime =lldiv ((unsigned long long )usec * gd->arch.timer_rate_hz, -1000UL ); - - endtime +=get_ticks (); - -while (get_ticks () < endtime) - ; +return lldiv (get_ticks (),CONFIG_SYS_HZ_CLOCK /1000000 ); }ulong get_tbclk (void )
Signature · 1 line
2.7.4
PATCH v2 3/15 arm: armv7: solve issue for timer_rate_hz in arch timer
Quoted 11 lines · Patrick Delaunay
The current value
timer_rate_hzcauses a problem with functiontimer_get_us()from lib time and then an issue withreadx_poll_timeout()function.With corrected value for
tbclk()=timer_rate_hz=CONFIG_SYS_HZ_CLOCKthe weak functions in lib timer can be used:
-get_timer()
-__udelay()
So the specific function in this file are removed.Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 4/15 dm: gpio: Convert stm32f7 driver to livetree
In reply to Patrick DelaunayUpdate the GPIO driver to support a live device tree.
Reviewed-by Simon Glass <[email protected]>
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
drivers/gpio/stm32f7_gpio.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-)
drivers/gpio/stm32f7_gpio.c +3 -9
@@ -16,14 +16,11 @@#include <linux/errno.h> #include <linux/io.h> -#define MAX_SIZE_BANK_NAME 5#define STM32_GPIOS_PER_BANK 16#define MODE_BITS (gpio_pin) (gpio_pin * 2)#define MODE_BITS_MASK 3#define IN_OUT_BIT_INDEX (gpio_pin) (1UL << (gpio_pin)) -DECLARE_GLOBAL_DATA_PTR ; -static int stm32_gpio_direction_input (struct udevice *dev,unsigned offset) {struct stm32_gpio_priv *priv =dev_get_priv (dev);
@@ -82,17 +79,14 @@ static int gpio_stm32_probe(struct udevice *dev)struct gpio_dev_priv *uc_priv =dev_get_uclass_priv (dev);struct stm32_gpio_priv *priv =dev_get_priv (dev);fdt_addr_t addr; -char *name; +const char *name; - addr =devfdt_get_addr (dev); + addr =dev_read_addr (dev);if (addr ==FDT_ADDR_T_NONE )return -EINVAL ; priv->regs = (struct stm32_gpio_regs *)addr; - name = (char *)fdtdec_locate_byte_array (gd->fdt_blob, -dev_of_offset (dev), -"st,bank-name" , -MAX_SIZE_BANK_NAME ); + name =dev_read_string (dev,"st,bank-name" );if (!name)return -EINVAL ; uc_priv->bank_name = name;
Signature · 1 line
2.7.4
PATCH v2 4/15 dm: gpio: Convert stm32f7 driver to livetree
Quoted 4 lines · Patrick Delaunay
Update the GPIO driver to support a live device tree.
Reviewed-by Simon Glass <[email protected]>Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 5/15 gpio: stm32f7_gpio: handle node ngpios
In reply to Patrick DelaunaySigned-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
drivers/gpio/stm32f7_gpio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/gpio/stm32f7_gpio.c +2 -1
@@ -90,7 +90,8 @@ static int gpio_stm32_probe(struct udevice *dev)if (!name)return -EINVAL ; uc_priv->bank_name = name; - uc_priv->gpio_count =STM32_GPIOS_PER_BANK ; + uc_priv->gpio_count =dev_read_u32_default (dev,"ngpios" , +STM32_GPIOS_PER_BANK );debug ("%s, addr = 0x%p, bank_name = %s\n" , __func__, (u32 *)priv->regs, uc_priv->bank_name);
Signature · 1 line
2.7.4
PATCH v2 5/15 gpio: stm32f7_gpio: handle node ngpios
Quoted 1 line · Patrick Delaunay
Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 6/15 stm32mp: stm32f7_i2c: use calloc instead of kmalloc
In reply to Patrick DelaunayKmalloc is using memalign allocation function. It is not necessary to align this structure so to save bytes, we move to calloc.
And kmalloc function can't be used in SPL early stage (in board_init_f())
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
drivers/i2c/stm32f7_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/i2c/stm32f7_i2c.c +2 -2
@@ -533,7 +533,7 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,if (((sdadel >= sdadel_min) && (sdadel <= sdadel_max)) && (p != p_prev)) { - v =kmalloc (sizeof (*v),GFP_KERNEL ); + v =calloc (1 ,sizeof (*v));if (!v)return -ENOMEM ;
@@ -689,7 +689,7 @@ exit:/* Release list and memory */ list_for_each_entry_safe (v, _v, &solutions, node) {list_del (&v->node); -kfree (v); +free (v); }return ret;
Signature · 1 line
2.7.4
PATCH v2 6/15 stm32mp: stm32f7_i2c: use calloc instead of kmalloc
Quoted 6 lines · Patrick Delaunay
Kmalloc is using memalign allocation function. It is not necessary to align this structure so to save bytes, we move to calloc.
And kmalloc function can't be used in SPL early stage (in
board_init_f())Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 7/15 arm: stm32: add new architecture for STM32MP family
In reply to Patrick Delaunay- add new arch stm32mp for STM32 MPU/Soc based on Cortex A
- support for stm32mp157 SOC
- SPL is used as first boot stage loader
- using driver model for all the drivers, even in SPL
- all security feature are deactivated (ETZC and TZC)
- reused STM32 MCU drivers when it is possible
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
MAINTAINERS | 5 ++ arch/arm/Kconfig | 25 +++++- arch/arm/Makefile | 1 + arch/arm/mach-stm32mp/Kconfig | 41 +++++++++ arch/arm/mach-stm32mp/Makefile | 10 +++ arch/arm/mach-stm32mp/config.mk | 14 +++ arch/arm/mach-stm32mp/cpu.c | 139 +++++++++++++++++++++++++++++ arch/arm/mach-stm32mp/dram_init.c | 34 +++++++ arch/arm/mach-stm32mp/include/mach/gpio.h | 115 ++++++++++++++++++++++++ arch/arm/mach-stm32mp/include/mach/stm32.h | 27 ++++++ arch/arm/mach-stm32mp/spl.c | 60 +++++++++++++ drivers/gpio/Kconfig | 2 +- drivers/i2c/Kconfig | 2 +- drivers/serial/Kconfig | 6 +- 14 files changed, 475 insertions(+), 6 deletions(-) create mode 100644 arch/arm/mach-stm32mp/Kconfig create mode 100644 arch/arm/mach-stm32mp/Makefile create mode 100644 arch/arm/mach-stm32mp/config.mk create mode 100644 arch/arm/mach-stm32mp/cpu.c create mode 100644 arch/arm/mach-stm32mp/dram_init.c create mode 100644 arch/arm/mach-stm32mp/include/mach/gpio.h create mode 100644 arch/arm/mach-stm32mp/include/mach/stm32.h create mode 100644 arch/arm/mach-stm32mp/spl.c
MAINTAINERS +5 -0
@@ -192,6 +192,11 @@ T: git git://git.denx.de/u-boot-stm.git F: arch/arm/cpu/arm926ejs/spear/ F: arch/arm/include/asm/arch-spear/ +ARM STM STM32MP +M: Patrick Delaunay <[email protected]> +S: Maintained +F: arch/arm/mach-stm32mp + ARM STM STV0991 M: Vikas Manocha <[email protected]> S: Maintained
arch/arm/Kconfig +24 -1
@@ -1130,7 +1130,7 @@ config ARCH_UNIPHIER (formerly, System LSI Business Division of Panasonic Corporation) config STM32 - bool "Support STM32" + bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M select DM select DM_SERIAL
@@ -1148,6 +1148,27 @@ config ARCH_STI Support for STMicroelectronics STiH407/10 SoC family. This SoC is used on Linaro 96Board STiH410-B2260 +config ARCH_STM32MP + bool "Support STMicroelectronics STM32MP Socs with cortex A" + select BOARD_LATE_INIT + select CLK + select DM + select DM_GPIO + select DM_RESET + select DM_SERIAL + select OF_CONTROL + select OF_LIBFDT + select PINCTRL + select REGMAP + select SUPPORT_SPL + select SYSCON + select SYS_THUMB_BUILD + help + Support for STM32MP SoC family developed by STMicroelectronics, + MPUs based on ARM cortex A core + U-BOOT is running in DDR and SPL support is the unsecure First Stage + BootLoader (FSBL) + config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select OF_CONTROL
@@ -1260,6 +1281,8 @@ source "arch/arm/mach-sti/Kconfig" source "arch/arm/mach-stm32/Kconfig" +source "arch/arm/mach-stm32mp/Kconfig" + source "arch/arm/mach-sunxi/Kconfig" source "arch/arm/mach-tegra/Kconfig"
arch/arm/Makefile +1 -0
@@ -72,6 +72,7 @@ machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_RMOBILE) += rmobile machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_STM32) += stm32 +machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq
arch/arm/mach-stm32mp/Kconfig new file +41 -0
41 lines not on this page · raw message
arch/arm/mach-stm32mp/Makefile new file +10 -0
@@ -0,0 +1,10 @@ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +# + +obj-y += cpu.o +obj-y += dram_init.o + +obj-$(CONFIG_SPL_BUILD) += spl.o
arch/arm/mach-stm32mp/config.mk new file +14 -0
@@ -0,0 +1,14 @@ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +# + +ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32 + +MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) + +spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log + +spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage)
arch/arm/mach-stm32mp/cpu.c new file +139 -0
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arch/arm/mach-stm32mp/dram_init.c new file +34 -0
@@ -0,0 +1,34 @@ +/* +* Copyright (C) 2018, STMicroelectronics - All Rights Reserved +* +* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +*/ + +#include <common.h> +#include <dm.h> +#include <ram.h> + +DECLARE_GLOBAL_DATA_PTR ; + +int dram_init (void ) +{ +struct ram_info ram; +struct udevice *dev; +int ret; + + ret =uclass_get_device (UCLASS_RAM ,0 , &dev); +if (ret) { +debug ("RAM init failed: %d\n" , ret); +return ret; + } + ret =ram_get_info (dev, &ram); +if (ret) { +debug ("Cannot get RAM size: %d\n" , ret); +return ret; + } +debug ("RAM init base=%lx, size=%x\n" , ram.base, ram.size); + + gd->ram_size = ram.size; + +return 0 ; +}
arch/arm/mach-stm32mp/include/mach/gpio.h new file +115 -0
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arch/arm/mach-stm32mp/include/mach/stm32.h new file +27 -0
@@ -0,0 +1,27 @@ +/* +* Copyright (C) 2018, STMicroelectronics - All Rights Reserved +* +* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +*/ + +#ifndef _MACH_STM32_H_ +#define _MACH_STM32_H_ + +/* +* Peripheral memory map +* only address used before device tree parsing +*/ +#define STM32_RCC_BASE 0x50000000 +#define STM32_PWR_BASE 0x50001000 +#define STM32_DBGMCU_BASE 0x50081000 +#define STM32_TZC_BASE 0x5C006000 +#define STM32_ETZPC_BASE 0x5C007000 +#define STM32_TAMP_BASE 0x5C00A000 + +#define STM32_SYSRAM_BASE 0x2FFC0000 +#define STM32_SYSRAM_SIZE SZ_256K + +#define STM32_DDR_BASE 0xC0000000 +#define STM32_DDR_SIZE SZ_1G + +#endif /* _MACH_STM32_H_ */
arch/arm/mach-stm32mp/spl.c new file +60 -0
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drivers/gpio/Kconfig +1 -1
@@ -234,7 +234,7 @@ config PIC32_GPIO config STM32F7_GPIO bool "ST STM32 GPIO driver" - depends on DM_GPIO && STM32 + depends on DM_GPIO && (STM32 || ARCH_STM32MP) default y help Device model driver support for STM32 GPIO controller. It should be
drivers/i2c/Kconfig +1 -1
@@ -207,7 +207,7 @@ config SYS_I2C_S3C24X0 config SYS_I2C_STM32F7 bool "STMicroelectronics STM32F7 I2C support" - depends on (STM32F7 || STM32H7) && DM_I2C + depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C help Enable this option to add support for STM32 I2C controller introduced with STM32F7/H7 SoCs. This I2C controller supports :
drivers/serial/Kconfig +3 -3
@@ -577,10 +577,10 @@ config STI_ASC_SERIAL config STM32_SERIAL bool "STMicroelectronics STM32 SoCs on-chip UART" - depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7) + depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7 || ARCH_STM32MP) help - If you have a machine based on a STM32 F4, F7 or H7 SoC you can - enable its onboard serial ports, say Y to this option. + If you have a machine based on a STM32 F4, F7, H7 or MP1 SOC + you can enable its onboard serial ports, say Y to this option. If unsure, say N. config ZYNQ_SERIAL
Signature · 1 line
2.7.4
PATCH v2 7/15 arm: stm32: add new architecture for STM32MP family
Quoted 8 lines · Patrick Delaunay
- add new arch stm32mp for STM32 MPU/Soc based on Cortex A
- support for stm32mp157 SOC
- SPL is used as first boot stage loader
- using driver model for all the drivers, even in SPL
- all security feature are deactivated (ETZC and TZC)
- reused STM32 MCU drivers when it is possibleSigned-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 8/15 ram: stm32mp1: add driver
In reply to Patrick DelaunayAdd driver and binding for stm32mp1 ddr controller and phy
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
MAINTAINERS | 1 + arch/arm/mach-stm32mp/include/mach/ddr.h | 12 + doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt | 299 ++++++++++++++ drivers/ram/Kconfig | 2 + drivers/ram/Makefile | 1 + drivers/ram/stm32mp1/Kconfig | 12 + drivers/ram/stm32mp1/Makefile | 8 + drivers/ram/stm32mp1/stm32mp1_ddr.c | 496 +++++++++++++++++++++++ drivers/ram/stm32mp1/stm32mp1_ddr.h | 210 ++++++++++ drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 365 +++++++++++++++++ drivers/ram/stm32mp1/stm32mp1_ram.c | 197 +++++++++ 11 files changed, 1603 insertions(+) create mode 100644 arch/arm/mach-stm32mp/include/mach/ddr.h create mode 100644 doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt create mode 100644 drivers/ram/stm32mp1/Kconfig create mode 100644 drivers/ram/stm32mp1/Makefile create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr.c create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr.h create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr_regs.h create mode 100644 drivers/ram/stm32mp1/stm32mp1_ram.c
MAINTAINERS +1 -0
@@ -196,6 +196,7 @@ ARM STM STM32MP M: Patrick Delaunay <[email protected]> S: Maintained F: arch/arm/mach-stm32mp +F: ram/stm32mp1 ARM STM STV0991 M: Vikas Manocha <[email protected]>
arch/arm/mach-stm32mp/include/mach/ddr.h new file +12 -0
@@ -0,0 +1,12 @@ +/* +* Copyright (C) 2018, STMicroelectronics - All Rights Reserved +* +* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +*/ + +#ifndef __MACH_STM32MP_DDR_H_ +#define __MACH_STM32MP_DDR_H_ + +int board_ddr_power_init (void ); + +#endif
doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt new file +299 -0
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drivers/ram/Kconfig +2 -0
@@ -33,3 +33,5 @@ config STM32_SDRAM STM32F7 family devices support flexible memory controller(FMC) to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the FMC. + +source "drivers/ram/stm32mp1/Kconfig"
drivers/ram/Makefile +1 -0
@@ -6,6 +6,7 @@ # obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o +obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
drivers/ram/stm32mp1/Kconfig new file +12 -0
@@ -0,0 +1,12 @@ + +config STM32MP1_DDR + bool "STM32MP1 DDR driver" + depends on DM && OF_CONTROL && ARCH_STM32MP + select RAM + select SPL_RAM if SPL + default y + help + activate STM32MP1 DDR controller driver for STM32MP1 soc + family: support for LPDDR2, LPDDR3 and DDR3 + the SDRAM parameters for controleur and phy need to be provided + in device tree (computed by DDR tuning tools)
drivers/ram/stm32mp1/Makefile new file +8 -0
@@ -0,0 +1,8 @@ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +# + +obj-y += stm32mp1_ram.o +obj-y += stm32mp1_ddr.o
drivers/ram/stm32mp1/stm32mp1_ddr.c new file +496 -0
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drivers/ram/stm32mp1/stm32mp1_ddr.h new file +210 -0
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drivers/ram/stm32mp1/stm32mp1_ddr_regs.h new file +365 -0
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drivers/ram/stm32mp1/stm32mp1_ram.c new file +197 -0
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Signature · 1 line
2.7.4
PATCH v2 8/15 ram: stm32mp1: add driver
Quoted 3 lines · Patrick Delaunay
Add driver and binding for stm32mp1 ddr controller and phy
Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 9/15 pmic: add stpmu1 support
In reply to Patrick DelaunayThis driver implements register read/write operations for STPMU1.
The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. It is accessed via an I2C interface. This device is used with STM32MP1 SoCs.
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
drivers/power/pmic/Kconfig | 8 +++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/stpmu1.c | 62 +++++++++++++++++++++++++++++++++ include/power/stpmu1.h | 85 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 156 insertions(+) create mode 100644 drivers/power/pmic/stpmu1.c create mode 100644 include/power/stpmu1.h
drivers/power/pmic/Kconfig +8 -0
@@ -209,3 +209,11 @@ config DM_PMIC_TPS65910 The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO pmic children. + +config PMIC_STPMU1 + bool "Enable support for STMicroelectronics STPMU1 PMIC" + depends on DM_PMIC && DM_I2C + ---help--- + The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. + It is accessed via an I2C interface. The device is used with STM32MP1 + SoCs. This driver implements register read/write operations.
drivers/power/pmic/Makefile +1 -0
@@ -23,6 +23,7 @@ obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o +obj-$(CONFIG_PMIC_STPMU1) += stpmu1.o obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
drivers/power/pmic/stpmu1.c new file +62 -0
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include/power/stpmu1.h new file +85 -0
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Signature · 1 line
2.7.4
PATCH v2 9/15 pmic: add stpmu1 support
Quoted 7 lines · Patrick Delaunay
This driver implements register read/write operations for STPMU1.
The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. It is accessed via an I2C interface. This device is used with STM32MP1 SoCs.
Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 10/15 pinctrl: stm32: update pincontrol for stmp32mp157
In reply to Patrick Delaunay- add the 2 new compatible used by STM32MP157
"st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl"
- update the mask for the port
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
drivers/pinctrl/pinctrl_stm32.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
drivers/pinctrl/pinctrl_stm32.c +7 -2
@@ -41,9 +41,10 @@ static int stm32_gpio_config(struct gpio_desc *desc,return 0 ; } +static int prep_gpio_dsc (struct stm32_gpio_dsc *gpio_dsc,u32 port_pin) { - gpio_dsc->port = (port_pin &0xF000 ) >>12 ; + gpio_dsc->port = (port_pin &0x1F000 ) >>12 ; gpio_dsc->pin = (port_pin &0x0F00 ) >>8 ;debug ("%s: GPIO:port= %d, pin= %d\n" , __func__, gpio_dsc->port, gpio_dsc->pin);
@@ -115,11 +116,13 @@ static int stm32_pinctrl_config(int offset)return -EINVAL ;for (i =0 ; i < len; i++) {struct gpio_desc desc; +debug ("%s: pinmux = %x\n" , __func__, *(pin_mux + i));prep_gpio_dsc (&gpio_dsc, *(pin_mux + i));prep_gpio_ctl (&gpio_ctl, *(pin_mux + i), offset); rv =uclass_get_device_by_seq (UCLASS_GPIO , - gpio_dsc.port, &desc.dev); + gpio_dsc.port, + &desc.dev);if (rv)return rv; desc.offset = gpio_dsc.pin;
@@ -186,6 +189,8 @@ static const struct udevice_id stm32_pinctrl_ids[] = { { .compatible = "st,stm32f469-pinctrl" }, { .compatible = "st,stm32f746-pinctrl" }, { .compatible = "st,stm32h743-pinctrl" }, + { .compatible = "st,stm32mp157-pinctrl" }, + { .compatible = "st,stm32mp157-z-pinctrl" }, { } };
Signature · 1 line
2.7.4
PATCH v2 10/15 pinctrl: stm32: update pincontrol for stmp32mp157
Quoted 6 lines · Patrick Delaunay
- add the 2 new compatible used by STM32MP157
"st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl"- update the mask for the port
Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 11/15 reset: stm32: adapt driver for stm32mp1
In reply to Patrick Delaunay- move to livetree and allow to get address to parent
- add stm32mp1 compatible for probe
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
drivers/reset/Kconfig | 2 +- drivers/reset/stm32-reset.c | 36 ++++++++++++++++++++++++++++++------ 2 files changed, 31 insertions(+), 7 deletions(-)
drivers/reset/Kconfig +1 -1
@@ -30,7 +30,7 @@ config STI_RESET config STM32_RESET bool "Enable the STM32 reset" - depends on STM32 + depends on STM32 || ARCH_STM32MP help Support for reset controllers on STMicroelectronics STM32 family SoCs. This resset driver is compatible with STM32 F4/F7 and H7 SoCs.
drivers/reset/stm32-reset.c +30 -6
@@ -11,7 +11,13 @@#include <reset-uclass.h> #include <asm/io.h> -DECLARE_GLOBAL_DATA_PTR ; +/* reset clear offset for STM32MP RCC */ +#define RCC_CL 0x4 + +enum rcc_type { +RCC_STM32 =0 , +RCC_STM32MP , +};struct stm32_reset_priv {fdt_addr_t base;
@@ -35,7 +41,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl)debug ("%s: reset id = %ld bank = %d offset = %d)\n" , __func__, reset_ctl->id, bank, offset); -setbits_le32 (priv->base + bank,BIT (offset)); +if (dev_get_driver_data (reset_ctl->dev) ==RCC_STM32MP ) +/* reset assert is done in rcc set register */ +writel (BIT (offset), priv->base + bank); +else +setbits_le32 (priv->base + bank,BIT (offset));return 0 ; }
@@ -48,7 +58,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)debug ("%s: reset id = %ld bank = %d offset = %d)\n" , __func__, reset_ctl->id, bank, offset); -clrbits_le32 (priv->base + bank,BIT (offset)); +if (dev_get_driver_data (reset_ctl->dev) ==RCC_STM32MP ) +/* reset deassert is done in rcc clr register */ +writel (BIT (offset), priv->base + bank +RCC_CL ); +else +clrbits_le32 (priv->base + bank,BIT (offset));return 0 ; }
@@ -64,16 +78,26 @@ static int stm32_reset_probe(struct udevice *dev) {struct stm32_reset_priv *priv =dev_get_priv (dev); - priv->base =devfdt_get_addr (dev); -if (priv->base ==FDT_ADDR_T_NONE ) -return -EINVAL ; + priv->base =dev_read_addr (dev); +if (priv->base ==FDT_ADDR_T_NONE ) { +/* for MFD, get address of parent */ + priv->base =dev_read_addr (dev->parent); +if (priv->base ==FDT_ADDR_T_NONE ) +return -EINVAL ; + }return 0 ; } +static const struct udevice_id stm32_reset_ids[] = { + { .compatible ="st,stm32mp1-rcc-rst" , .data =RCC_STM32MP }, + { } +}; +U_BOOT_DRIVER (stm32_rcc_reset) = { .name ="stm32_rcc_reset" , .id =UCLASS_RESET , + .of_match = stm32_reset_ids, .probe = stm32_reset_probe, .priv_auto_alloc_size =sizeof (struct stm32_reset_priv ), .ops = &stm32_reset_ops,
Signature · 1 line
2.7.4
PATCH v2 11/15 reset: stm32: adapt driver for stm32mp1
Quoted 4 lines · Patrick Delaunay
- move to livetree and allow to get address to parent
- add stm32mp1 compatible for probeSigned-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 11/15 reset: stm32: adapt driver for stm32mp1
In reply to Patrick DelaunayQuoted 4 lines · Patrick Delaunay
- move to livetree and allow to get address to parent
- add stm32mp1 compatible for probeSigned-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 12/15 clk: add driver for stm32mp1
In reply to Patrick Delaunayadd RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
of all SOC clock needed by U-Boot
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
MAINTAINERS | 1 + drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk_stm32mp1.c | 1157 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1167 insertions(+) create mode 100644 drivers/clk/clk_stm32mp1.c
MAINTAINERS +1 -0
@@ -196,6 +196,7 @@ ARM STM STM32MP M: Patrick Delaunay <[email protected]> S: Maintained F: arch/arm/mach-stm32mp +F: clk/clk_stm32mp1.c F: ram/stm32mp1 ARM STM STV0991
drivers/clk/Kconfig +8 -0
@@ -75,6 +75,14 @@ config CLK_ZYNQMP This clock driver adds support for clock realted settings for ZynqMP platform. +config CLK_STM32MP1 + bool "Enable RCC clock driver for STM32MP1" + depends on ARCH_STM32MP && CLK + default y + help + Enable the STM32 clock (RCC) driver. Enable support for + manipulating STM32MP1's on-SoC clocks. + source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/exynos/Kconfig"
drivers/clk/Makefile +1 -0
@@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o +obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
drivers/clk/clk_stm32mp1.c new file +1157 -0
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Signature · 1 line
2.7.4
PATCH v2 12/15 clk: add driver for stm32mp1
Quoted 6 lines · Patrick Delaunay
add RCC clock driver for STMP32MP157
- base on driver model =UCLASS_CLK
- support ops to enable, disable and get rate
of all SOC clock needed by U-BootSigned-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 13/15 clk: stm32mp1: add clock tree initialization
In reply to Patrick Delaunayadd binding and code for clock tree initialization from device tree
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
doc/device-tree-bindings/clock/st,stm32mp1.txt | 226 ++++++++++ drivers/clk/clk_stm32mp1.c | 576 +++++++++++++++++++++++++ include/dt-bindings/clock/stm32mp1-clksrc.h | 284 ++++++++++++ 3 files changed, 1086 insertions(+) create mode 100644 doc/device-tree-bindings/clock/st,stm32mp1.txt create mode 100644 include/dt-bindings/clock/stm32mp1-clksrc.h
doc/device-tree-bindings/clock/st,stm32mp1.txt new file +226 -0
@@ -0,0 +1,226 @@ +STMicroelectronics STM32MP1 clock tree initialization +===================================================== + +The STM32MP clock tree initialization is based on device tree information +for RCC IP and on fixed clocks. + +------------------------------- +RCC CLOCK = st,stm32mp1-rcc-clk +------------------------------- + +The RCC IP is both a reset and a clock controller but this documentation only +describes the fields added for clock tree initialization which are not present +in Linux binding. + +Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common +with Linux. + +Required properties: + +- compatible: Should be "st,stm32mp1-rcc-clk" + +- st,clksrc : The clock source in this order + + for STM32MP15x: 9 clock sources are requested + MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2 + + with value equals to RCC clock specifier as defined in + dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE> + +- st,clkdiv : The div parameters in this order + for STM32MP15x: 11 dividers value are requested + MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2 + + with DIV coding defined in RCC associated register RCC_xxxDIVR + + most the case, it is: + 0x0: not divided + 0x1: division by 2 + 0x2: division by 4 + 0x3: division by 8 + ... + + but for RTC MCO1 MCO2, the coding is different: + 0x0: not divided + 0x1: division by 2 + 0x2: division by 3 + 0x3: division by 4 + ... + +Optional Properties: +- st,pll + PLL children node for PLL1 to PLL4 : (see ref manual for details) + with associated index 0 to 3 (st,pll at 0 to st,pll at 4) + PLLx is off when the associated node is absent + + - Sub-nodes: + + - cfg: The parameters for PLL configuration in this order: + DIVM DIVN DIVP DIVQ DIVR Output + + with DIV value as defined in RCC spec: + 0x0: bypass (division by 1) + 0x1: division by 2 + 0x2: division by 3 + 0x3: division by 4 + ... + + and Output = bitfield for each output value = 1:ON/0:OFF + BIT(0) => output P : DIVPEN + BIT(1) => output Q : DIVQEN + BIT(2) => output R : DIVREN + NB : macro PQR(p,q,r) can be used to build this value + with p,p,r = 0 or 1 + + - frac : Fractional part of the multiplication factor + (optional, PLL is in integer mode when absent) + + - csg : Clock Spreading Generator (optional) + with parameters in this order: + MOD_PER INC_STEP SSCG_MODE + + * MOD_PER: Modulation Period Adjustment + * INC_STEP: Modulation Depth Adjustment + * SSCG_MODE: Spread spectrum clock generator mode + you can use associated defines from stm32mp1-clksrc.h + * SSCG_MODE_CENTER_SPREAD = 0 + * SSCG_MODE_DOWN_SPREAD = 1 + + +- st,pkcs : used to configure the peripherals kernel clock selection + containing a list of peripheral kernel clock source identifier as defined + in the file dt-bindings/clock/stm32mp1-clksrc.h + + Example: + + rcc: rcc at 50000000 { + compatible = "syscon", "simple-mfd"; + + reg = <0x50000000 0x1000>; + + rcc_clk: rcc-clk at 50000000 { + #clock-cells = <1>; + compatible = "st,stm32mp1-rcc-clk"; + + st,clksrc = < CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_HSI + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_HSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 5 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pll at 0 { + cfg = < 1 53 0 0 0 1 >; + frac = < 0x810 >; + }; + st,pll at 1 { + cfg = < 1 43 1 0 0 PQR(0,1,1)>; + csg = <10 20 1>; + }; + st,pll at 2 { + cfg = < 2 85 3 13 3 0>; + csg = <10 20 SSCG_MODE_CENTER_SPREAD>; + }; + st,pll at 3 { + cfg = < 2 78 4 7 9 3>; + }; + st,pkcs = < + CLK_STGEN_HSE + CLK_CKPER_HSI + CLK_USBPHY_PLL2P + CLK_DSI_PLL2Q + >; + }; + }; + +-------------------------- +other clocks = fixed-clock +-------------------------- +The clock tree is also based on 5 fixed-clock in clocks node +used to define the state of associated ST32MP1 oscillators: +- clk-lsi +- clk-lse +- clk-hsi +- clk-hse +- clk-csi + +At boot the clock tree initialization will +- enable the oscillator present in device tree +- disable HSI oscillator if the node is absent (always activated by bootrom) + +Optional properties : + +a) for external oscillator: "clk-lse", "clk-hse" + + 3 optional fields are managed + - "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP) + - "st,css" Activate the clock security system (HSECSSON, LSECSSON) + - "st,drive" (only for LSE) value of the drive for the oscillator + (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h) + + Example board file: + + / { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + st,bypass; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + st,css; + st,drive = <LSEDRV_LOWEST>; + }; + }; + +b) for internal oscillator: "clk-hsi" + + internally HSI clock is fixed to 64MHz for STM32MP157 soc + in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc) + So this clock frequency is used to compute the expected HSI_DIV + for the clock tree initialisation + + ex: for HSIDIV = /1 + + / { + clocks { + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + }; + + ex: for HSIDIV = /2 + + / { + clocks { + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000000>; + }; + };
drivers/clk/clk_stm32mp1.c +576 -0
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include/dt-bindings/clock/stm32mp1-clksrc.h new file +284 -0
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Signature · 1 line
2.7.4
PATCH v2 13/15 clk: stm32mp1: add clock tree initialization
Quoted 3 lines · Patrick Delaunay
add binding and code for clock tree initialization from device tree
Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 14/15 dts: add device tree for STM32MP157C-ED1 board
In reply to Patrick DelaunayAdd minimal devicetree for STM32MP157C-ED1 board,
with only the devices to allow boot from SDCARD:
- RCC for clock and reset
- UART4 for console
- I2C and PMIC
- DDR
- SDMMC0 for SDCard
Waiting Kernel upstream for alignment.
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2: None
arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp15-ddr.dtsi | 155 +++++++++++ arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 122 +++++++++ arch/arm/dts/stm32mp157-u-boot.dtsi | 134 +++++++++ arch/arm/dts/stm32mp157.dtsi | 303 +++++++++++++++++++++ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 133 +++++++++ arch/arm/dts/stm32mp157c-ed1.dts | 167 ++++++++++++ include/dt-bindings/clock/stm32mp1-clks.h | 243 +++++++++++++++++ .../dt-bindings/reset-controller/stm32mp1-resets.h | 97 +++++++ 9 files changed, 1357 insertions(+) create mode 100644 arch/arm/dts/stm32mp15-ddr.dtsi create mode 100644 arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi create mode 100644 arch/arm/dts/stm32mp157-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157.dtsi create mode 100644 arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157c-ed1.dts create mode 100644 include/dt-bindings/clock/stm32mp1-clks.h create mode 100644 include/dt-bindings/reset-controller/stm32mp1-resets.h
arch/arm/dts/Makefile +3 -0
@@ -497,6 +497,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb +dtb-$(CONFIG_TARGET_STM32MP1) += \ + stm32mp157c-ed1.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here
arch/arm/dts/stm32mp15-ddr.dtsi new file +155 -0
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arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi new file +122 -0
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arch/arm/dts/stm32mp157-u-boot.dtsi new file +134 -0
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arch/arm/dts/stm32mp157.dtsi new file +303 -0
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arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi new file +133 -0
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arch/arm/dts/stm32mp157c-ed1.dts new file +167 -0
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include/dt-bindings/clock/stm32mp1-clks.h new file +243 -0
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include/dt-bindings/reset-controller/stm32mp1-resets.h new file +97 -0
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Signature · 1 line
2.7.4
PATCH v2 14/15 dts: add device tree for STM32MP157C-ED1 board
Quoted 11 lines · Patrick Delaunay
Add minimal devicetree for STM32MP157C-ED1 board,
with only the devices to allow boot from SDCARD:
- RCC for clock and reset
- UART4 for console
- I2C and PMIC
- DDR
- SDMMC0 for SDCardWaiting Kernel upstream for alignment.
Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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PATCH v2 15/15 board: st: add generic board for STM32MP1 family
In reply to Patrick DelaunayAdd first support for STM32MP157C-ED1 board with "Basic" boot chain 1/ Boot Rom: load SPL with STM32 image header in SYSRAM 2/ SPL: power up and initialize the DDR and load U-Boot image
from SDCARD in DDR
3/ U-Boot: search and load extlinux.conf in SDCARD
(DISTRO activated)
Signed-off-by Patrick Delaunay <[email protected]>
---
Changes in v2:
- remove include of "config_distro_defaults.h"
arch/arm/mach-stm32mp/Kconfig | 2 + board/st/stm32mp1/Kconfig | 12 +++ board/st/stm32mp1/MAINTAINERS | 7 ++ board/st/stm32mp1/Makefile | 13 +++ board/st/stm32mp1/README | 191 ++++++++++++++++++++++++++++++++++++++ board/st/stm32mp1/board.c | 75 +++++++++++++++ board/st/stm32mp1/spl.c | 33 +++++++ board/st/stm32mp1/stm32mp1.c | 27 ++++++ configs/stm32mp15_basic_defconfig | 36 +++++++ include/configs/stm32mp1.h | 96 +++++++++++++++++++ 10 files changed, 492 insertions(+) create mode 100644 board/st/stm32mp1/Kconfig create mode 100644 board/st/stm32mp1/MAINTAINERS create mode 100644 board/st/stm32mp1/Makefile create mode 100644 board/st/stm32mp1/README create mode 100644 board/st/stm32mp1/board.c create mode 100644 board/st/stm32mp1/spl.c create mode 100644 board/st/stm32mp1/stm32mp1.c create mode 100644 configs/stm32mp15_basic_defconfig create mode 100644 include/configs/stm32mp1.h
arch/arm/mach-stm32mp/Kconfig +2 -0
@@ -38,4 +38,6 @@ config SYS_TEXT_BASE when DDR driver is used: DDR + 1MB (0xC0100000) +source "board/st/stm32mp1/Kconfig" + endif
board/st/stm32mp1/Kconfig new file +12 -0
@@ -0,0 +1,12 @@ +if TARGET_STM32MP1 + +config SYS_BOARD + default "stm32mp1" + +config SYS_VENDOR + default "st" + +config SYS_CONFIG_NAME + default "stm32mp1" + +endif
board/st/stm32mp1/MAINTAINERS new file +7 -0
@@ -0,0 +1,7 @@ +STM32MP1 BOARD +M: Patrick Delaunay <[email protected]> +S: Maintained +F: board/st/stm32mp1 +F: include/configs/stm32mp1.h +F: configs/stm32mp15_basic_defconfig +F: arch/arm/dts/stm32mp157*
board/st/stm32mp1/Makefile new file +13 -0
@@ -0,0 +1,13 @@ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += stm32mp1.o +endif + +obj-y += board.o
board/st/stm32mp1/README new file +191 -0
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board/st/stm32mp1/board.c new file +75 -0
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board/st/stm32mp1/spl.c new file +33 -0
@@ -0,0 +1,33 @@ +/* +* Copyright (C) 2018, STMicroelectronics - All Rights Reserved +* +* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +*/ + +#include <config.h> +#include <common.h> +#include <spl.h> +#include <dm.h> +#include <ram.h> +#include <asm/io.h> +#include <post.h> +#include <power/pmic.h> +#include <power/stpmu1.h> +#include <asm/arch/ddr.h> + +void spl_board_init (void ) +{ +/* Keep vdd on during the reset cycle */ +#if defined(CONFIG_PMIC_STPMU1 ) && defined(CONFIG_SPL_POWER_SUPPORT ) +struct udevice *dev; +int ret; + + ret =uclass_get_device_by_driver (UCLASS_PMIC , +DM_GET_DRIVER (pmic_stpmu1), &dev); +if (!ret) +pmic_clrsetbits (dev, +STPMU1_MASK_RESET_BUCK , +STPMU1_MASK_RESET_BUCK3 , +STPMU1_MASK_RESET_BUCK3 ); +#endif +}
board/st/stm32mp1/stm32mp1.c new file +27 -0
@@ -0,0 +1,27 @@ +/* +* Copyright (C) 2018, STMicroelectronics - All Rights Reserved +* +* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +*/ +#include <config.h> +#include <common.h> +#include <asm/arch/stm32.h> + +/* +* Get a global data pointer +*/ +DECLARE_GLOBAL_DATA_PTR ; + +int board_late_init (void ) +{ +return 0 ; +} + +/* board dependent setup after realloc */ +int board_init (void ) +{ +/* address of boot parameters */ + gd->bd->bi_boot_params =STM32_DDR_BASE +0x100 ; + +return 0 ; +}
configs/stm32mp15_basic_defconfig new file +36 -0
@@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL=y +CONFIG_TARGET_STM32MP1=y +CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ed1" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SYS_PROMPT="STM32MP> " +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_DM_MMC=y +CONFIG_STM32_SDMMC2=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_DM_PMIC=y +CONFIG_PMIC_STPMU1=y +CONFIG_STM32_SERIAL=y +# CONFIG_EFI_LOADER is not set
include/configs/stm32mp1.h new file +96 -0
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Signature · 1 line
2.7.4
PATCH v2 15/15 board: st: add generic board for STM32MP1 family
Quoted 8 lines · Patrick Delaunay
Add first support for STM32MP157C-ED1 board with "Basic" boot chain 1/ Boot Rom: load SPL with STM32 image header in SYSRAM 2/ SPL: power up and initialize the DDR and load U-Boot image
from SDCARD in DDR
3/ U-Boot: search and load extlinux.conf in SDCARD
(DISTRO activated)Signed-off-by Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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