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powerpc/mm/radix: Update pte fragment count from 16 to 256 on radix

PATCH Applied Aneesh Kumar K.V 2 participants 2 messages Mar 22, 2018 – Apr 4, 2018 PowerPC

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Aneesh Kumar K.V

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#0 lore raw

PATCH v2 1/1 powerpc/mm/radix: Update pte fragment count from 16 to 256 on radix

Right now we use only 4K out of the 64k page allocated for the level 4 page table. W.r.t the performance impact due to lock contention, with ebizzy

256 threads:
without patch (10 runs of ./ebizzy -m -n 1000 -s 131072 -S 100) median = 15678.5
stdev = 42.1209

with patch:
median = 15354
stdev = 194.743

This is with THP disabled. With THP enabled the impact of the patch will be less.

Signed-off-by Aneesh Kumar K.V <[email protected]>
---
 arch/powerpc/include/asm/book3s/64/hash-64k.h  | 10 ++++------
 arch/powerpc/include/asm/book3s/64/radix-4k.h  |  5 +++++
 arch/powerpc/include/asm/book3s/64/radix-64k.h |  6 ++++++
 arch/powerpc/mm/pgtable-radix.c                |  8 ++------
 4 files changed, 17 insertions(+), 12 deletions(-)
arch/powerpc/include/asm/book3s/64/hash-64k.h +4 -6
index 3bcf269f8f55..0aa4f755b3f6 100644
@@ -24,16 +24,14 @@
 
 /* PTE flags to conserve for HPTE identification */
 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | H_PAGE_COMBO)
-/*
- * we support 16 fragments per PTE page of 64K size.
- */
-#define H_PTE_FRAG_NR	16
 /*
  * We use a 2K PTE page fragment and another 2K for storing
  * real_pte_t hash index
+ * 8 bytes per each pte entry and another 8 bytes for storing
+ * slot details.
  */
-#define H_PTE_FRAG_SIZE_SHIFT  12
-#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
+#define H_PTE_FRAG_SIZE_SHIFT  (H_PTE_INDEX_SIZE + 3 + 1)
+#define H_PTE_FRAG_NR	(PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
 
 #ifndef __ASSEMBLY__
 #include <asm/errno.h>
arch/powerpc/include/asm/book3s/64/radix-4k.h +5 -0
index a61aa9cd63ec..ca366ec86310 100644
@@ -9,5 +9,10 @@
 #define RADIX_PMD_INDEX_SIZE  9  /* 1G huge page */
 #define RADIX_PUD_INDEX_SIZE	 9
 #define RADIX_PGD_INDEX_SIZE  13
+/*
+ * One fragment per per page
+ */
+#define RADIX_PTE_FRAG_SIZE_SHIFT  (RADIX_PTE_INDEX_SIZE + 3)
+#define RADIX_PTE_FRAG_NR	(PAGE_SIZE >> RADIX_PTE_FRAG_SIZE_SHIFT)
 
 #endif /* _ASM_POWERPC_PGTABLE_RADIX_4K_H */
arch/powerpc/include/asm/book3s/64/radix-64k.h +6 -0
index c7e71ba29555..830082496876 100644
@@ -10,4 +10,10 @@
 #define RADIX_PUD_INDEX_SIZE	 9
 #define RADIX_PGD_INDEX_SIZE  13
 
+/*
+ * We use a 256 byte PTE page fragment in radix
+ * 8 bytes per each PTE entry.
+ */
+#define RADIX_PTE_FRAG_SIZE_SHIFT  (RADIX_PTE_INDEX_SIZE + 3)
+#define RADIX_PTE_FRAG_NR	(PAGE_SIZE >> RADIX_PTE_FRAG_SIZE_SHIFT)
 #endif /* _ASM_POWERPC_PGTABLE_RADIX_64K_H */
arch/powerpc/mm/pgtable-radix.c +2 -6
index 2e10a964e290..7fd51549b9e5 100644
@@ -575,12 +575,8 @@ void __init radix__early_init_mmu(void)
 #ifdef CONFIG_PCI
 	pci_io_base = ISA_IO_BASE;
 #endif
-
-	/*
-	 * For now radix also use the same frag size
-	 */
-	__pte_frag_nr = H_PTE_FRAG_NR;
-	__pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
+	__pte_frag_nr = RADIX_PTE_FRAG_NR;
+	__pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
 
 	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 		radix_init_native();
Signature · 1 line
2.14.3
Applied
#1 lore raw
Quoted 8 lines · Aneesh Kumar K.V

Right now we use only 4K out of the 64k page allocated for the level 4 page table. W.r.t the performance impact due to lock contention, with ebizzy

256 threads:
without patch (10 runs of ./ebizzy -m -n 1000 -s 131072 -S 100) median = 15678.5
stdev = 42.1209

Quoted 7 lines

with patch:
median = 15354
stdev = 194.743

This is with THP disabled. With THP enabled the impact of the patch will be less.

Signed-off-by Aneesh Kumar K.V <[email protected]>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/fb4e5dbd44564077fa0267a59b4596

cheers