lib/dummyload: Add pollable spin batch
Subsystems (2)
PATCH 1/3 lib/dummyload: Add pollable spin batch
From: Tvrtko Ursulin <[email protected]>
Pollable spin batch exports a spin->running pointer which can be checked by dereferencing it to see if the spinner is actually executing on the GPU.
This is useful for tests which want to make sure they do not proceed with their next step whilst the spinner is potentially only being processed by the driver and not actually executing.
Pollable spinner can be created with igt_spin_batch_new_poll or __igt_spin_batch_new_poll, after which igt_spin_busywait_until_running can be used to busy wait until it is executing.
v2:
* Move READ_ONCE to igt_core.
* Add igt_spin_busywait_until_running. (Chris Wilson)
--- benchmarks/gem_wsim.c | 2 - lib/igt_core.h | 2 + lib/igt_dummyload.c | 192 ++++++++++++++++++++++++++++++++++++++++---------- lib/igt_dummyload.h | 17 +++++ lib/igt_gt.c | 2 +- lib/ioctl_wrappers.c | 2 +- lib/ioctl_wrappers.h | 1 + 7 files changed, 175 insertions(+), 43 deletions(-)
benchmarks/gem_wsim.c +0 -2
@@ -980,8 +980,6 @@ current_seqno(struct workload *wrk, enum intel_engine_id engine)return wrk->seqno[engine]; } -#define READ_ONCE (x) (*(volatile typeof(x) *)(&(x))) -static uint32_t read_status_page (struct workload *wrk,unsigned int idx) {
lib/igt_core.h +2 -0
@@ -950,4 +950,6 @@ void igt_kmsg(const char *format, ...);#define KMSG_INFO "<6>[IGT] "#define KMSG_DEBUG "<7>[IGT] " +#define READ_ONCE (x) (*(volatile typeof(x) *)(&(x))) +#endif /* IGT_CORE_H */
lib/igt_dummyload.c +153 -39
299 lines not on this page · raw message
lib/igt_dummyload.h +17 -0
@@ -36,6 +36,10 @@ typedef struct igt_spin {struct igt_list link;uint32_t *batch;int out_fence; +struct drm_i915_gem_exec_object2 obj[2 ]; +struct drm_i915_gem_execbuffer2 execbuf; +uint32_t poll_handle; +bool *running; } igt_spin_t; igt_spin_t *__igt_spin_batch_new(int fd,
@@ -55,10 +59,23 @@ igt_spin_t *igt_spin_batch_new_fence(int fd,uint32_t ctx, unsigned engine); +igt_spin_t *__igt_spin_batch_new_poll (int fd, +uint32_t ctx, +unsigned engine); +igt_spin_t *igt_spin_batch_new_poll (int fd, +uint32_t ctx, +unsigned engine); +void igt_spin_batch_set_timeout (igt_spin_t *spin,int64_t ns);void igt_spin_batch_end (igt_spin_t *spin);void igt_spin_batch_free (int fd,igt_spin_t *spin); +static inline void igt_spin_busywait_until_running (igt_spin_t *spin) +{ +while (!READ_ONCE (*spin->running)) + ; +} +void igt_terminate_spin_batches (void );enum igt_cork_type {
lib/igt_gt.c +1 -1
@@ -609,7 +609,7 @@ bool gem_can_store_dword(int fd, unsigned int engine)if (gen ==3 && (info->is_grantsdale || info->is_alviso))return false;/* only supports physical addresses */ -if (gen ==6 && (engine & ~(3 <<13 )) ==I915_EXEC_BSD ) +if (gen ==6 && ((engine &0x3f ) ==I915_EXEC_BSD ))return false;/* kills the machine! */ if (info->is_broadwater)
lib/ioctl_wrappers.c +1 -1
@@ -198,7 +198,7 @@ void gem_set_tiling(int fd, uint32_t handle, uint32_t tiling, uint32_t stride)igt_assert (__gem_set_tiling (fd, handle, tiling, stride) ==0 ); } -static int __gem_set_caching (int fd,uint32_t handle,uint32_t caching) +int __gem_set_caching (int fd,uint32_t handle,uint32_t caching) {struct drm_i915_gem_caching arg;int err;
lib/ioctl_wrappers.h +1 -0
@@ -61,6 +61,7 @@ bool gem_get_tiling(int fd, uint32_t handle, uint32_t *tiling, uint32_t *swizzlevoid gem_set_tiling (int fd,uint32_t handle,uint32_t tiling,uint32_t stride);int __gem_set_tiling (int fd,uint32_t handle,uint32_t tiling,uint32_t stride); +int __gem_set_caching (int fd,uint32_t handle,uint32_t caching);void gem_set_caching (int fd,uint32_t handle,uint32_t caching);uint32_t gem_get_caching (int fd,uint32_t handle);uint32_t gem_flink (int fd,uint32_t handle);
Signature · 6 lines
2.14.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
PATCH 2/3 tests/gem_eio: Speed up test execution
From: Tvrtko Ursulin <[email protected]>
If we stop relying on regular GPU hangs to be detected, but trigger them manually as soon as we know our batch of interest is actually executing on the GPU, we can dramatically speed up various subtests.
This is enabled by the pollable spin batch added in the previous patch.
v2:
* Test gem_wait after reset/wedge and with reset/wedge after a few predefined intervals since gem_wait invocation. (Chris Wilson)
--- lib.tar | Bin 0 -> 102400 bytes tests/gem_eio.c | 214 ++++++++++++++++++++++++++++++++++++++++++-------------- 2 files changed, 160 insertions(+), 54 deletions(-) create mode 100644 lib.tar
lib.tar new file binary +0 -0
tests/gem_eio.c +160 -54
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Signature · 6 lines
2.14.1 _______________________________________________ igt-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/igt-dev
Re: [igt-dev] [PATCH i-g-t 2/3] tests/gem_eio: Speed up test execution
Quoting Tvrtko Ursulin (2018-03-22 17:24:16)
Quoted 110 lines
From: Tvrtko Ursulin <[email protected]>
If we stop relying on regular GPU hangs to be detected, but trigger them manually as soon as we know our batch of interest is actually executing on the GPU, we can dramatically speed up various subtests.
This is enabled by the pollable spin batch added in the previous patch.
v2:
* Testgem_waitafter reset/wedge and with reset/wedge after a few predefined intervals sincegem_waitinvocation. (Chris Wilson)Signed-off-by Tvrtko Ursulin <[email protected]>Suggested-by Chris Wilson <[email protected]>Cc Antonio Argenziano <[email protected]>--- lib.tar | Bin 0 -> 102400 bytes tests/gem_eio.c | 214 ++++++++++++++++++++++++++++++++++++++++++-------------- 2 files changed, 160 insertions(+), 54 deletions(-) create mode 100644 lib.tartests/gem_eio.c +46
-14@@ -35,6 +35,7 @@#include <inttypes.h> #include <errno.h> #include <sys/ioctl.h> +#include <signal.h> #include <drm.h> @@ -71,26 +72,23 @@ static void trigger_reset(int fd)gem_quiescent_gpu (fd); } -static void wedge_gpu (int fd) +static void manual_hang (int drm_fd) { -/* First idle the GPU then disable GPU resets before injecting a hang */ -gem_quiescent_gpu (fd); - -igt_require (i915_reset_control (false)); +int dir =igt_debugfs_dir (drm_fd); -igt_debug ("Wedging GPU by injecting hang\n" ); -igt_post_hang_ring (fd,igt_hang_ring (fd,I915_EXEC_DEFAULT )); +igt_sysfs_set (dir,"i915_wedged" ,"-1" ); -igt_assert (i915_reset_control (true)); +close (dir); } -static void wedgeme (int drm_fd) +static void wedge_gpu (int fd) { -int dir =igt_debugfs_dir (drm_fd); - -igt_sysfs_set (dir,"i915_wedged" ,"-1" ); +/* First idle the GPU then disable GPU resets before injecting a hang */ +gem_quiescent_gpu (fd); -close (dir); +igt_require (i915_reset_control (false)); +manual_hang (fd); +igt_assert (i915_reset_control (true)); }static int __gem_throttle (int fd)@@ -149,26 +147,111 @@ static int __gem_wait(int fd, uint32_t handle, int64_t timeout)return err; } -static void test_wait (int fd) +static igt_spin_t *__spin_poll (int fd,uint32_t ctx,unsigned long flags) +{ +if (gem_can_store_dword (fd, flags)) +return __igt_spin_batch_new_poll (fd, ctx, flags); +else +return __igt_spin_batch_new (fd, ctx, flags,0 ); +} + +static void __spin_wait (int fd,igt_spin_t *spin) +{ +if (spin->running) { +igt_spin_busywait_until_running (spin); + }else { +igt_debug ("__spin_wait - usleep mode\n" ); +usleep (500e3 );/* Better than nothing! */ + } +} + +static igt_spin_t *spin_sync (int fd,uint32_t ctx,unsigned long flags) +{ +igt_spin_t *spin =__spin_poll (fd, ctx, flags); + +__spin_wait (fd, spin); + +return spin; +} + +static int debugfs_dir =-1 ; + +static void hang_handler (int sig) +{ +igt_sysfs_set (debugfs_dir,"i915_wedged" ,"-1" ); +} + +static void hang_after (int fd,unsigned int us)
tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 194
Quoted 10 lines
tests/gem_eio.c +10
-0+{ +struct sigaction sa = { .sa_handler = hang_handler }; +struct itimerval itv = { }; + + debugfs_dir =igt_debugfs_dir (fd); +igt_assert_fd (debugfs_dir); + +igt_assert_eq (sigaction (SIGALRM , &sa,NULL ),0 ); + + itv.it_value.tv_sec = us /1000000 ;
USEC_PER_SEC.
tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 196
Quoted 2 lines
tests/gem_eio.c +2
-0+ itv.it_value.tv_usec = us %1000000 ; +setitimer (ITIMER_REAL , &itv,NULL );
Ok, that gives a single shot signal.
I would have used
struct sigevent sev = {
.sigev_notify = SIGEV_THREAD,
.sigev_value.sigval_int = debugfs_dir
.sigev_notify_function = hang_handler
};timer_create(CLOCK_MONOTONIC, &sec, &timer);timer_settime(timer, 0, &its, NULL);
Then
static void hang_handler(union sigval arg)
{
igt_sysfs_set(arg.sival_int, "i915_wedged", 1);
}No signals, nor globals required :)
The problem with using a signal is that it interrupts the gem_wait() and so we don't actually check that it is being woken by the hang because it is already awake. Gah.
tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 203
Quoted 5 lines
tests/gem_eio.c +5
-0+static void cleanup_hang (void ) +{ +struct itimerval itv = { }; + +igt_assert_eq (setitimer (ITIMER_REAL , &itv,NULL ),0 );
You also need a sleep here as it does not flush inflight signals. (Also timer_destroy :)
Quoted 9 lines
tests/gem_eio.c +9
-0+igt_assert_fd (debugfs_dir); +close (debugfs_dir); + debugfs_dir =-1 ; +} + +static int __check_wait (int fd,uint32_t bo,unsigned int wait) +{ +unsigned long wait_timeout =250e6 ;/* Some margin for actual reset. */ +int ret;
tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 223
Quoted 10 lines
tests/gem_eio.c +10
-0+ +if (wait) { + wait_timeout += wait *2000 ;/* x2 for safety. */ + wait_timeout +=250e6 ;/* Margin for signal delay. */ ; +hang_after (fd, wait); + }else { +manual_hang (fd); + } + + ret =__gem_wait (fd, bo, wait_timeout);
Ok, I understand where the concerned about how long it took to recover from reset came from :)
Quoted 208 lines
tests/gem_eio.c +44
-40+ +if (wait) +cleanup_hang (); + +return ret; +} + +#define TEST_WEDGE (1) + +static void test_wait (int fd,unsigned int flags,unsigned int wait) { -igt_hang_t hang; +igt_spin_t *hang;igt_require_gem (fd); -/* If the request we wait on completes due to a hang (even for +/* +* If the request we wait on completes due to a hang (even for * that request), the user expects the return value to 0 (success). */ - hang =igt_hang_ring (fd,I915_EXEC_DEFAULT ); -igt_assert_eq (__gem_wait (fd, hang.handle,-1 ),0 ); -igt_post_hang_ring (fd, hang); -/* If the GPU is wedged during the wait, again we expect the return -* value to be 0 (success). -*/ -igt_require (i915_reset_control (false)); - hang =igt_hang_ring (fd,I915_EXEC_DEFAULT ); -igt_assert_eq (__gem_wait (fd, hang.handle,-1 ),0 ); -igt_post_hang_ring (fd, hang); +if (flags &TEST_WEDGE ) +igt_require (i915_reset_control (false)); +else +igt_require (i915_reset_control (true)); + + hang =spin_sync (fd,0 ,I915_EXEC_DEFAULT ); + +igt_assert_eq (__check_wait (fd, hang->handle, wait),0 ); + +igt_spin_batch_free (fd, hang); +igt_require (i915_reset_control (true));trigger_reset (fd);@@ -181,7 +264,7 @@ static void test_suspend(int fd, int state)/* Check we can suspend when the driver is already wedged */ igt_require (i915_reset_control (false)); -wedgeme (fd); +manual_hang (fd);igt_system_suspend_autoresume (state,SUSPEND_TEST_DEVICES );@@ -189,7 +272,7 @@ static void test_suspend(int fd, int state)trigger_reset (fd); } -static void test_inflight (int fd) +static void test_inflight (int fd,unsigned int wait) {const uint32_t bbe =MI_BATCH_BUFFER_END ;struct drm_i915_gem_exec_object2 obj[2 ];@@ -209,11 +292,10 @@ static void test_inflight(int fd)int fence[64 ];/* conservative estimate of ring size */ gem_quiescent_gpu (fd); -igt_debug ("Starting %s on engine '%s'\n" , __func__, e__->name);igt_require (i915_reset_control (false)); - hang =__igt_spin_batch_new (fd,0 , engine,0 ); + hang =spin_sync (fd,0 , engine); obj[0 ].handle = hang->handle;memset (&execbuf,0 ,sizeof (execbuf));@@ -227,7 +309,8 @@ static void test_inflight(int fd)igt_assert (fence[n] !=-1 ); } -igt_assert_eq (__gem_wait (fd, obj[1 ].handle,-1 ),0 ); +igt_assert_eq (__check_wait (fd, obj[1 ].handle, wait),0 ); +for (unsigned int n =0 ; n <ARRAY_SIZE (fence); n++) {igt_assert_eq (sync_fence_status (fence[n]), -EIO );close (fence[n]);@@ -256,7 +339,7 @@ static void test_inflight_suspend(int fd) obj[1 ].handle =gem_create (fd,4096 );gem_write (fd, obj[1 ].handle,0 , &bbe,sizeof (bbe)); - hang =__igt_spin_batch_new (fd,0 ,0 ,0 ); + hang =spin_sync (fd,0 ,0 ); obj[0 ].handle = hang->handle;memset (&execbuf,0 ,sizeof (execbuf));@@ -273,7 +356,8 @@ static void test_inflight_suspend(int fd)igt_set_autoresume_delay (30 );igt_system_suspend_autoresume (SUSPEND_STATE_MEM ,SUSPEND_TEST_NONE ); -igt_assert_eq (__gem_wait (fd, obj[1 ].handle,-1 ),0 ); +igt_assert_eq (__check_wait (fd, obj[1 ].handle,10 ),0 ); +for (unsigned int n =0 ; n <ARRAY_SIZE (fence); n++) {igt_assert_eq (sync_fence_status (fence[n]), -EIO );close (fence[n]);@@ -301,7 +385,7 @@ static uint32_t context_create_safe(int i915)return param.ctx_id; } -static void test_inflight_contexts (int fd) +static void test_inflight_contexts (int fd,unsigned int wait) {struct drm_i915_gem_exec_object2 obj[2 ];const uint32_t bbe =MI_BATCH_BUFFER_END ;@@ -330,7 +414,7 @@ static void test_inflight_contexts(int fd)igt_debug ("Starting %s on engine '%s'\n" , __func__, e__->name);igt_require (i915_reset_control (false)); - hang =__igt_spin_batch_new (fd,0 , engine,0 ); + hang =spin_sync (fd,0 , engine); obj[0 ].handle = hang->handle;memset (&execbuf,0 ,sizeof (execbuf));@@ -345,7 +429,8 @@ static void test_inflight_contexts(int fd)igt_assert (fence[n] !=-1 ); } -igt_assert_eq (__gem_wait (fd, obj[1 ].handle,-1 ),0 ); +igt_assert_eq (__check_wait (fd, obj[1 ].handle, wait),0 ); +for (unsigned int n =0 ; n <ARRAY_SIZE (fence); n++) {igt_assert_eq (sync_fence_status (fence[n]), -EIO );close (fence[n]);@@ -375,7 +460,7 @@ static void test_inflight_external(int fd) fence =igt_cork_plug (&cork, fd);igt_require (i915_reset_control (false)); - hang =__igt_spin_batch_new (fd,0 ,0 ,0 ); + hang =__spin_poll (fd,0 ,0 );memset (&obj,0 ,sizeof (obj)); obj.handle =gem_create (fd,4096 );@@ -393,6 +478,9 @@ static void test_inflight_external(int fd) fence = execbuf.rsvd2 >>32 ;igt_assert (fence !=-1 ); +__spin_wait (fd, hang); +manual_hang (fd); +gem_sync (fd, hang->handle);/* wedged, with an unready batch */ igt_assert (!gem_bo_busy (fd, hang->handle));igt_assert (gem_bo_busy (fd, obj.handle));@@ -407,7 +495,7 @@ static void test_inflight_external(int fd)trigger_reset (fd); } -static void test_inflight_internal (int fd) +static void test_inflight_internal (int fd,unsigned int wait) {struct drm_i915_gem_execbuffer2 execbuf;struct drm_i915_gem_exec_object2 obj[2 ];@@ -420,7 +508,7 @@ static void test_inflight_internal(int fd)igt_require (gem_has_exec_fence (fd));igt_require (i915_reset_control (false)); - hang =__igt_spin_batch_new (fd,0 ,0 ,0 ); + hang =spin_sync (fd,0 ,0 );memset (obj,0 ,sizeof (obj)); obj[0 ].handle = hang->handle;@@ -441,7 +529,8 @@ static void test_inflight_internal(int fd) nfence++; } -igt_assert_eq (__gem_wait (fd, obj[1 ].handle,-1 ),0 ); +igt_assert_eq (__check_wait (fd, obj[1 ].handle, wait),0 ); +while (nfence--) {igt_assert_eq (sync_fence_status (fences[nfence]), -EIO );close (fences[nfence]);@@ -484,29 +573,46 @@ igt_main igt_subtest("execbuf")test_execbuf (fd); - igt_subtest("wait") -test_wait (fd); - igt_subtest("suspend")test_suspend (fd,SUSPEND_STATE_MEM ); igt_subtest("hibernate")test_suspend (fd,SUSPEND_STATE_DISK ); - igt_subtest("in-flight") -test_inflight (fd); - - igt_subtest("in-flight-contexts") -test_inflight_contexts (fd); - igt_subtest("in-flight-external")test_inflight_external (fd); - igt_subtest("in-flight-internal") { -igt_skip_on (gem_has_semaphores (fd)); -test_inflight_internal (fd); - } -
tests/gem_eio.c igt_main · line 594
Quoted 10 lines
tests/gem_eio.c +8
-0igt_subtest("in-flight-suspend")test_inflight_suspend (fd); + + igt_subtest_group { +const struct { +unsigned int wait; +const char *name; + } waits[] = { + { .wait =0 , .name ="immediate" }, + { .wait =10 , .name ="10us" },
i915_request_spin is set to 2us currently :| I guess that's a really hard window to hit reliably. Maybe we should spin for 200ms just to make testing easier!
tests/gem_eio.c igt_main · line 604
Quoted 10 lines
tests/gem_eio.c +10
-0+ { .wait = 10000, .name = "10ms" }, + }; +unsigned int i; + +for (i =0 ; i <sizeof (waits) /sizeof (waits[0 ]); i++) { + igt_subtest_f("wait-%s", waits[i].name) +test_wait (fd,0 , waits[i].wait); + + igt_subtest_f("wait-wedge-%s", waits[i].name) +test_wait (fd,TEST_WEDGE , waits[i].wait);
Ok.
tests/gem_eio.c igt_main · line 614
Quoted 10 lines
tests/gem_eio.c +10
-0+ + igt_subtest_f("in-flight-%s", waits[i].name) +test_inflight (fd, waits[i].wait); + + igt_subtest_f("in-flight-contexts-%s", waits[i].name) +test_inflight_contexts (fd, waits[i].wait); + + igt_subtest_f("in-flight-internal-%s", waits[i].name) { +igt_skip_on (gem_has_semaphores (fd)); +test_inflight_internal (fd, waits[i].wait);
And ok.
-Chris
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Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 2/3] tests/gem_eio: Speed up test execution
Quoted 138 lines · Chris Wilson
Quoting Tvrtko Ursulin (2018-03-22 17:24:16)
Quoted 110 lines
From: Tvrtko Ursulin <[email protected]>
If we stop relying on regular GPU hangs to be detected, but trigger them manually as soon as we know our batch of interest is actually executing on the GPU, we can dramatically speed up various subtests.
This is enabled by the pollable spin batch added in the previous patch.
v2:
* Testgem_waitafter reset/wedge and with reset/wedge after a few predefined intervals sincegem_waitinvocation. (Chris Wilson)Signed-off-by Tvrtko Ursulin <[email protected]>Suggested-by Chris Wilson <[email protected]>Cc Antonio Argenziano <[email protected]>--- lib.tar | Bin 0 -> 102400 bytes tests/gem_eio.c | 214 ++++++++++++++++++++++++++++++++++++++++++-------------- 2 files changed, 160 insertions(+), 54 deletions(-)create mode 100644 lib.tar
tests/gem_eio.c +46
-14@@ -35,6 +35,7 @@#include <inttypes.h> #include <errno.h> #include <sys/ioctl.h> +#include <signal.h> #include <drm.h> @@ -71,26 +72,23 @@ static void trigger_reset(int fd)gem_quiescent_gpu (fd); } -static void wedge_gpu (int fd) +static void manual_hang (int drm_fd) { -/* First idle the GPU then disable GPU resets before injecting a hang */ -gem_quiescent_gpu (fd); - -igt_require (i915_reset_control (false)); +int dir =igt_debugfs_dir (drm_fd); -igt_debug ("Wedging GPU by injecting hang\n" ); -igt_post_hang_ring (fd,igt_hang_ring (fd,I915_EXEC_DEFAULT )); +igt_sysfs_set (dir,"i915_wedged" ,"-1" ); -igt_assert (i915_reset_control (true)); +close (dir); } -static void wedgeme (int drm_fd) +static void wedge_gpu (int fd) { -int dir =igt_debugfs_dir (drm_fd); - -igt_sysfs_set (dir,"i915_wedged" ,"-1" ); +/* First idle the GPU then disable GPU resets before injecting a hang */ +gem_quiescent_gpu (fd); -close (dir); +igt_require (i915_reset_control (false)); +manual_hang (fd); +igt_assert (i915_reset_control (true)); }static int __gem_throttle (int fd)@@ -149,26 +147,111 @@ static int __gem_wait(int fd, uint32_t handle, int64_t timeout)return err; } -static void test_wait (int fd) +static igt_spin_t *__spin_poll (int fd,uint32_t ctx,unsigned long flags) +{ +if (gem_can_store_dword (fd, flags)) +return __igt_spin_batch_new_poll (fd, ctx, flags); +else +return __igt_spin_batch_new (fd, ctx, flags,0 ); +} + +static void __spin_wait (int fd,igt_spin_t *spin) +{ +if (spin->running) { +igt_spin_busywait_until_running (spin); + }else { +igt_debug ("__spin_wait - usleep mode\n" ); +usleep (500e3 );/* Better than nothing! */ + } +} + +static igt_spin_t *spin_sync (int fd,uint32_t ctx,unsigned long flags) +{ +igt_spin_t *spin =__spin_poll (fd, ctx, flags); + +__spin_wait (fd, spin); + +return spin; +} + +static int debugfs_dir =-1 ; + +static void hang_handler (int sig) +{ +igt_sysfs_set (debugfs_dir,"i915_wedged" ,"-1" ); +} + +static void hang_after (int fd,unsigned int us)tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 194
Quoted 10 lines
tests/gem_eio.c +10
-0+{ +struct sigaction sa = { .sa_handler = hang_handler }; +struct itimerval itv = { }; + + debugfs_dir =igt_debugfs_dir (fd); +igt_assert_fd (debugfs_dir); + +igt_assert_eq (sigaction (SIGALRM , &sa,NULL ),0 ); + + itv.it_value.tv_sec = us /1000000 ;
USEC_PER_SEC.tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 196
Quoted 2 lines
tests/gem_eio.c +2
-0+ itv.it_value.tv_usec = us %1000000 ; +setitimer (ITIMER_REAL , &itv,NULL );Ok, that gives a single shot signal.
I would have used
struct sigevent sev = {
.sigev_notify =SIGEV_THREAD,
.sigev_value.sigval_int =debugfs_dir
.sigev_notify_function =hang_handler
};timer_create(CLOCK_MONOTONIC, &sec, &timer);timer_settime(timer, 0, &its, NULL);
Quoted 8 lines
Then
static void
hang_handler(union sigval arg){ igt_sysfs_set(arg.sival_int, "i915_wedged", 1); }No signals, nor globals required :)
I wasn't familiar with this facility.
It creates a new thread, so any hopes for small microsecond delays might be ruined. I can try it if you think it is still worth it?
Quoted 3 lines
The problem with using a signal is that it interrupts the
gem_wait()and so we don't actually check that it is being woken by the hang because it is already awake. Gah.
Hm... if I am following correctly, we end up with -ERESTARTSYS and the the ioctl can get restarted for us, if I would set SA_RESTART.
At the moment it happens to work because drmIoctl restart the signal.
Quoted 8 lines
tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 203
Quoted 5 lines
tests/gem_eio.c +5
-0+static void cleanup_hang (void ) +{ +struct itimerval itv = { }; + +igt_assert_eq (setitimer (ITIMER_REAL , &itv,NULL ),0 );You also need a sleep here as it does not flush inflight signals. (Also
timer_destroy:)
I always pass a longer timeout to gem_wait than the signal so I think it should be guaranteed that the signal had fired before gem_wait will be exiting.
Regards,
Tvrtko
Quoted 269 lines
Quoted 10 lines
tests/gem_eio.c +9
-0+igt_assert_fd (debugfs_dir); +close (debugfs_dir); + debugfs_dir =-1 ; +} + +static int __check_wait (int fd,uint32_t bo,unsigned int wait) +{ +unsigned long wait_timeout =250e6 ;/* Some margin for actual reset. */ +int ret;tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 223
Quoted 10 lines
tests/gem_eio.c +10
-0+ +if (wait) { + wait_timeout += wait *2000 ;/* x2 for safety. */ + wait_timeout +=250e6 ;/* Margin for signal delay. */ ; +hang_after (fd, wait); + }else { +manual_hang (fd); + } + + ret =__gem_wait (fd, bo, wait_timeout);Ok, I understand where the concerned about how long it took to recover from reset came from :)
Quoted 208 lines
tests/gem_eio.c +44
-40+ +if (wait) +cleanup_hang (); + +return ret; +} + +#define TEST_WEDGE (1) + +static void test_wait (int fd,unsigned int flags,unsigned int wait) { -igt_hang_t hang; +igt_spin_t *hang;igt_require_gem (fd); -/* If the request we wait on completes due to a hang (even for +/* +* If the request we wait on completes due to a hang (even for * that request), the user expects the return value to 0 (success). */ - hang =igt_hang_ring (fd,I915_EXEC_DEFAULT ); -igt_assert_eq (__gem_wait (fd, hang.handle,-1 ),0 ); -igt_post_hang_ring (fd, hang); -/* If the GPU is wedged during the wait, again we expect the return -* value to be 0 (success). -*/ -igt_require (i915_reset_control (false)); - hang =igt_hang_ring (fd,I915_EXEC_DEFAULT ); -igt_assert_eq (__gem_wait (fd, hang.handle,-1 ),0 ); -igt_post_hang_ring (fd, hang); +if (flags &TEST_WEDGE ) +igt_require (i915_reset_control (false)); +else +igt_require (i915_reset_control (true)); + + hang =spin_sync (fd,0 ,I915_EXEC_DEFAULT ); + +igt_assert_eq (__check_wait (fd, hang->handle, wait),0 ); + +igt_spin_batch_free (fd, hang); +igt_require (i915_reset_control (true));trigger_reset (fd);@@ -181,7 +264,7 @@ static void test_suspend(int fd, int state)/* Check we can suspend when the driver is already wedged */ igt_require (i915_reset_control (false)); -wedgeme (fd); +manual_hang (fd);igt_system_suspend_autoresume (state,SUSPEND_TEST_DEVICES );@@ -189,7 +272,7 @@ static void test_suspend(int fd, int state)trigger_reset (fd); } -static void test_inflight (int fd) +static void test_inflight (int fd,unsigned int wait) {const uint32_t bbe =MI_BATCH_BUFFER_END ;struct drm_i915_gem_exec_object2 obj[2 ];@@ -209,11 +292,10 @@ static void test_inflight(int fd)int fence[64 ];/* conservative estimate of ring size */ gem_quiescent_gpu (fd); -igt_debug ("Starting %s on engine '%s'\n" , __func__, e__->name);igt_require (i915_reset_control (false)); - hang =__igt_spin_batch_new (fd,0 , engine,0 ); + hang =spin_sync (fd,0 , engine); obj[0 ].handle = hang->handle;memset (&execbuf,0 ,sizeof (execbuf));@@ -227,7 +309,8 @@ static void test_inflight(int fd)igt_assert (fence[n] !=-1 ); } -igt_assert_eq (__gem_wait (fd, obj[1 ].handle,-1 ),0 ); +igt_assert_eq (__check_wait (fd, obj[1 ].handle, wait),0 ); +for (unsigned int n =0 ; n <ARRAY_SIZE (fence); n++) {igt_assert_eq (sync_fence_status (fence[n]), -EIO );close (fence[n]);@@ -256,7 +339,7 @@ static void test_inflight_suspend(int fd) obj[1 ].handle =gem_create (fd,4096 );gem_write (fd, obj[1 ].handle,0 , &bbe,sizeof (bbe)); - hang =__igt_spin_batch_new (fd,0 ,0 ,0 ); + hang =spin_sync (fd,0 ,0 ); obj[0 ].handle = hang->handle;memset (&execbuf,0 ,sizeof (execbuf));@@ -273,7 +356,8 @@ static void test_inflight_suspend(int fd)igt_set_autoresume_delay (30 );igt_system_suspend_autoresume (SUSPEND_STATE_MEM ,SUSPEND_TEST_NONE ); -igt_assert_eq (__gem_wait (fd, obj[1 ].handle,-1 ),0 ); +igt_assert_eq (__check_wait (fd, obj[1 ].handle,10 ),0 ); +for (unsigned int n =0 ; n <ARRAY_SIZE (fence); n++) {igt_assert_eq (sync_fence_status (fence[n]), -EIO );close (fence[n]);@@ -301,7 +385,7 @@ static uint32_t context_create_safe(int i915)return param.ctx_id; } -static void test_inflight_contexts (int fd) +static void test_inflight_contexts (int fd,unsigned int wait) {struct drm_i915_gem_exec_object2 obj[2 ];const uint32_t bbe =MI_BATCH_BUFFER_END ;@@ -330,7 +414,7 @@ static void test_inflight_contexts(int fd)igt_debug ("Starting %s on engine '%s'\n" , __func__, e__->name);igt_require (i915_reset_control (false)); - hang =__igt_spin_batch_new (fd,0 , engine,0 ); + hang =spin_sync (fd,0 , engine); obj[0 ].handle = hang->handle;memset (&execbuf,0 ,sizeof (execbuf));@@ -345,7 +429,8 @@ static void test_inflight_contexts(int fd)igt_assert (fence[n] !=-1 ); } -igt_assert_eq (__gem_wait (fd, obj[1 ].handle,-1 ),0 ); +igt_assert_eq (__check_wait (fd, obj[1 ].handle, wait),0 ); +for (unsigned int n =0 ; n <ARRAY_SIZE (fence); n++) {igt_assert_eq (sync_fence_status (fence[n]), -EIO );close (fence[n]);@@ -375,7 +460,7 @@ static void test_inflight_external(int fd) fence =igt_cork_plug (&cork, fd);igt_require (i915_reset_control (false)); - hang =__igt_spin_batch_new (fd,0 ,0 ,0 ); + hang =__spin_poll (fd,0 ,0 );memset (&obj,0 ,sizeof (obj)); obj.handle =gem_create (fd,4096 );@@ -393,6 +478,9 @@ static void test_inflight_external(int fd) fence = execbuf.rsvd2 >>32 ;igt_assert (fence !=-1 ); +__spin_wait (fd, hang); +manual_hang (fd); +gem_sync (fd, hang->handle);/* wedged, with an unready batch */ igt_assert (!gem_bo_busy (fd, hang->handle));igt_assert (gem_bo_busy (fd, obj.handle));@@ -407,7 +495,7 @@ static void test_inflight_external(int fd)trigger_reset (fd); } -static void test_inflight_internal (int fd) +static void test_inflight_internal (int fd,unsigned int wait) {struct drm_i915_gem_execbuffer2 execbuf;struct drm_i915_gem_exec_object2 obj[2 ];@@ -420,7 +508,7 @@ static void test_inflight_internal(int fd)igt_require (gem_has_exec_fence (fd));igt_require (i915_reset_control (false)); - hang =__igt_spin_batch_new (fd,0 ,0 ,0 ); + hang =spin_sync (fd,0 ,0 );memset (obj,0 ,sizeof (obj)); obj[0 ].handle = hang->handle;@@ -441,7 +529,8 @@ static void test_inflight_internal(int fd) nfence++; } -igt_assert_eq (__gem_wait (fd, obj[1 ].handle,-1 ),0 ); +igt_assert_eq (__check_wait (fd, obj[1 ].handle, wait),0 ); +while (nfence--) {igt_assert_eq (sync_fence_status (fences[nfence]), -EIO );close (fences[nfence]);@@ -484,29 +573,46 @@ igt_main igt_subtest("execbuf")test_execbuf (fd); - igt_subtest("wait") -test_wait (fd); - igt_subtest("suspend")test_suspend (fd,SUSPEND_STATE_MEM ); igt_subtest("hibernate")test_suspend (fd,SUSPEND_STATE_DISK ); - igt_subtest("in-flight") -test_inflight (fd); - - igt_subtest("in-flight-contexts") -test_inflight_contexts (fd); - igt_subtest("in-flight-external")test_inflight_external (fd); - igt_subtest("in-flight-internal") { -igt_skip_on (gem_has_semaphores (fd)); -test_inflight_internal (fd); - } -tests/gem_eio.c igt_main · line 594
Quoted 10 lines
tests/gem_eio.c +8
-0igt_subtest("in-flight-suspend")test_inflight_suspend (fd); + + igt_subtest_group { +const struct { +unsigned int wait; +const char *name; + } waits[] = { + { .wait =0 , .name ="immediate" }, + { .wait =10 , .name ="10us" },
i915_request_spinis set to 2us currently :| I guess that's a really hard window to hit reliably. Maybe we should spin for 200ms just to make testing easier!tests/gem_eio.c igt_main · line 604
Quoted 10 lines
tests/gem_eio.c +10
-0+ { .wait = 10000, .name = "10ms" }, + }; +unsigned int i; + +for (i =0 ; i <sizeof (waits) /sizeof (waits[0 ]); i++) { + igt_subtest_f("wait-%s", waits[i].name) +test_wait (fd,0 , waits[i].wait); + + igt_subtest_f("wait-wedge-%s", waits[i].name) +test_wait (fd,TEST_WEDGE , waits[i].wait);Ok.
Quoted 9 lines
tests/gem_eio.c +9
-0+ + igt_subtest_f("in-flight-%s", waits[i].name) +test_inflight (fd, waits[i].wait); + + igt_subtest_f("in-flight-contexts-%s", waits[i].name) +test_inflight_contexts (fd, waits[i].wait); + + igt_subtest_f("in-flight-internal-%s", waits[i].name) { +igt_skip_on (gem_has_semaphores (fd));
Quoted 9 lines
tests/gem_eio.c igt_main · line 614
Quoted 1 line
tests/gem_eio.c +1
-0+test_inflight_internal (fd, waits[i].wait);And ok.
-Chris
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Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 2/3] tests/gem_eio: Speed up test execution
Quoting Tvrtko Ursulin (2018-03-23 09:46:49)
Quoted 24 lines · Chris Wilson
Quoted 22 lines
Quoting Tvrtko Ursulin (2018-03-22 17:24:16)
tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 196
Quoted 2 lines
tests/gem_eio.c +2
-0+ itv.it_value.tv_usec = us %1000000 ; +setitimer (ITIMER_REAL , &itv,NULL );Ok, that gives a single shot signal.
I would have used
struct sigevent sev = {
.sigev_notify =SIGEV_THREAD,
.sigev_value.sigval_int =debugfs_dir
.sigev_notify_function =hang_handler
};timer_create(CLOCK_MONOTONIC, &sec, &timer);timer_settime(timer, 0, &its, NULL);Then
static void
hang_handler(union sigval arg){ igt_sysfs_set(arg.sival_int, "i915_wedged", 1); }
Quoted 6 lines
Quoted 1 line
No signals, nor globals required :)
I wasn't familiar with this facility.
It creates a new thread, so any hopes for small microsecond delays might be ruined. I can try it if you think it is still worth it?
Yes, still worth a shot. We can always poke glibc for some smarts. Or chase it ourselves with custom threading. We need an igt_debug() to actually tell us how long it took to respond (from spin start to gem_wait return).
Quoted 8 lines
Quoted 3 lines
The problem with using a signal is that it interrupts the
gem_wait()and so we don't actually check that it is being woken by the hang because it is already awake. Gah.Hm... if I am following correctly, we end up with
-ERESTARTSYSand the the ioctl can get restarted for us, if I would setSA_RESTART.At the moment it happens to work because drmIoctl restart the signal.
Yes. But even automatic -ERESTARTSYS handling still implies we break i915_request_wait() due to signal_pending_state().
Quoted 9 lines
Quoted 8 lines
tests/gem_eio.c static int __gem_wait(int fd, uint32_t handle, int64_t timeout) · line 203
Quoted 5 lines
tests/gem_eio.c +5
-0+static void cleanup_hang (void ) +{ +struct itimerval itv = { }; + +igt_assert_eq (setitimer (ITIMER_REAL , &itv,NULL ),0 );You also need a sleep here as it does not flush inflight signals. (Also
timer_destroy:)
Quoted 3 lines
I always pass a longer timeout to
gem_waitthan the signal so I think it should be guaranteed that the signal had fired beforegem_waitwill be exiting.
I hadn't considered that. Please leave a comment as the timer cancellation leaving pending signals inflight is something that keeps catching me out.
-Chris
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PATCH v3 2/3 tests/gem_eio: Speed up test execution
From: Tvrtko Ursulin <[email protected]>
If we stop relying on regular GPU hangs to be detected, but trigger them manually as soon as we know our batch of interest is actually executing on the GPU, we can dramatically speed up various subtests.
This is enabled by the pollable spin batch added in the previous patch.
v2:
* Test gem_wait after reset/wedge and with reset/wedge after a few predefined intervals since gem_wait invocation. (Chris Wilson)
v3:
Chris Wilson:
* Decrease short test to 1us.
* Use POSIX timers instead of signals to avoid interrupting gem_wait.
* Improve comment.
--- tests/Makefile.am | 1 + tests/gem_eio.c | 235 +++++++++++++++++++++++++++++++++++++++++------------- tests/meson.build | 8 +- 3 files changed, 189 insertions(+), 55 deletions(-)
tests/Makefile.am +1 -0
@@ -130,6 +130,7 @@ gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_userptr_blits_LDADD = $(LDADD) -lpthread perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la +gem_eio_LDADD = $(LDADD) -lrt gem_wait_LDADD = $(LDADD) -lrt kms_flip_LDADD = $(LDADD) -lrt -lpthread pm_rc6_residency_LDADD = $(LDADD) -lrt
tests/gem_eio.c +181 -54
377 lines not on this page · raw message
tests/meson.build +7 -1
@@ -40,7 +40,6 @@ test_progs = [ 'gem_ctx_switch', 'gem_ctx_thrash', 'gem_double_irq_loop', - 'gem_eio', 'gem_evict_alignment', 'gem_evict_everything', 'gem_exec_alignment',
@@ -289,6 +288,13 @@ foreach prog : test_progs install : true) endforeach +test_executables += executable('gem_eio', 'gem_eio.c', + dependencies : test_deps + [ realtime ], + install_dir : libexecdir, + install_rpath : rpathdir, + install : true) +test_progs += 'gem_eio' + test_executables += executable('perf_pmu', 'perf_pmu.c', dependencies : test_deps + [ lib_igt_perf ], install_dir : libexecdir,
Signature · 6 lines
2.14.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [igt-dev] [Intel-gfx] [PATCH i-g-t v3 2/3] tests/gem_eio: Speed up test execution
Quoting Tvrtko Ursulin (2018-03-23 11:54:28)
Quoted 18 lines
From: Tvrtko Ursulin <[email protected]>
If we stop relying on regular GPU hangs to be detected, but trigger them manually as soon as we know our batch of interest is actually executing on the GPU, we can dramatically speed up various subtests.
This is enabled by the pollable spin batch added in the previous patch.
v2:
* Testgem_waitafter reset/wedge and with reset/wedge after a few predefined intervals sincegem_waitinvocation. (Chris Wilson)v3:
Chris Wilson:
* Decrease short test to 1us.
* Use POSIX timers instead of signals to avoid interruptinggem_wait.
* Improve comment.
Quoted 3 lines
Signed-off-by Tvrtko Ursulin <[email protected]>Suggested-by Chris Wilson <[email protected]>Cc Antonio Argenziano <[email protected]>
I can't think of anything else that might go wrong, so
-Chris
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PATCH 3/3 tests/perf_pmu: Improve accuracy by waiting on spinner to start
In reply to Tvrtko UrsulinFrom: Tvrtko Ursulin <[email protected]>
More than one test assumes that the spinner is running pretty much immediately after we have create or submitted it.
In actuality there is a variable delay, especially on execlists platforms, between submission and spin batch starting to run on the hardware.
To enable tests which care about this level of timing to account for this, we add a new spin batch constructor which provides an output field which can be polled to determine when the batch actually started running.
This is implemented via MI_STOREDW_IMM from the spin batch, writing into memory mapped page shared with userspace.
Using this facility from perf_pmu, where applicable, should improve very occasional test fails across the set and platforms.
v2:
Chris Wilson:
* Use caching mapping if available.
* Handle old gens better.
* Use gem_can_store_dword.
* Cache exec obj array in spin_batch_t for easier resubmit.
v3:
* Forgot I915_EXEC_NO_RELOC. (Chris Wilson)
v4:
* Mask out all non-engine flags in gem_can_store_dword.
* Added some debug logging.
v5:
* Fix relocs and batch munmap. (Chris)
* Added assert idle spinner batch looks as expected.
v6:
* Skip accuracy tests when !gem_can_store_dword.
v7:
* Fix batch recursion reloc address.
v8:
Chris Wilson:
* Pull up gem_can_store_dword check before we start submitting.
* Build spinner batch in a way we can skip store dword when not needed so we can run on SandyBridge.
v9:
* Fix wait on spinner.
* More tweaks to accuracy test.
v10:
* Dropped accuracy subtest changes due problems with RT thread and tasklet submission.
v11:
* Use READ_ONCE.
--- tests/perf_pmu.c | 151 +++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 103 insertions(+), 48 deletions(-)
tests/perf_pmu.c +103 -48
@@ -170,6 +170,56 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)#define FLAG_LONG (16)#define FLAG_HANG (32) +static igt_spin_t *__spin_poll (int fd,uint32_t ctx,unsigned long flags) +{ +if (gem_can_store_dword (fd, flags)) +return __igt_spin_batch_new_poll (fd, ctx, flags); +else +return __igt_spin_batch_new (fd, ctx, flags,0 ); +} + +static unsigned long __spin_wait (int fd,igt_spin_t *spin) +{ +struct timespec start = { }; + +igt_nsec_elapsed (&start); + +if (spin->running) { +unsigned long timeout =0 ; + +while (!READ_ONCE (*spin->running)) { +unsigned long t =igt_nsec_elapsed (&start); + +if ((t - timeout) >250e6 ) { + timeout = t; +igt_warn ("Spinner not running after %.2fms\n" , + (double )t /1e6 ); + } + } + }else { +igt_debug ("__spin_wait - usleep mode\n" ); +usleep (500e3 );/* Better than nothing! */ + } + +return igt_nsec_elapsed (&start); +} + +static igt_spin_t *__spin_sync (int fd,uint32_t ctx,unsigned long flags) +{ +igt_spin_t *spin =__spin_poll (fd, ctx, flags); + +__spin_wait (fd, spin); + +return spin; +} + +static igt_spin_t *spin_sync (int fd,uint32_t ctx,unsigned long flags) +{ +igt_require_gem (fd); + +return __spin_sync (fd, ctx, flags); +} +static void end_spin (int fd,igt_spin_t *spin,unsigned int flags) {if (!spin)
@@ -180,8 +230,25 @@ static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)if (flags &FLAG_SYNC )gem_sync (fd, spin->handle); -if (flags &TEST_TRAILING_IDLE ) -usleep (batch_duration_ns /5000 ); +if (flags &TEST_TRAILING_IDLE ) { +unsigned long t, timeout =0 ; +struct timespec start = { }; + +igt_nsec_elapsed (&start); + +do { + t =igt_nsec_elapsed (&start); + +if (gem_bo_busy (fd, spin->handle) && + (t - timeout) >10e6 ) { + timeout = t; +igt_warn ("Spinner not idle after %.2fms\n" , + (double )t /1e6 ); + } + +usleep (1e3 ); + }while (t < batch_duration_ns /5 ); + } } static void
@@ -195,7 +262,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags) fd =open_pmu (I915_PMU_ENGINE_BUSY (e->class, e->instance));if (flags &TEST_BUSY ) - spin =igt_spin_batch_new (gem_fd,0 ,e2ring (gem_fd, e),0 ); + spin =spin_sync (gem_fd,0 ,e2ring (gem_fd, e));else spin =NULL ;
@@ -251,13 +318,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)*/ sleep (2 ); - spin =__igt_spin_batch_new (gem_fd,0 ,e2ring (gem_fd, e),0 ); - -/* -* Sleep for a bit after making the engine busy to make sure the PMU -* gets enabled when the batch is already running. -*/ -usleep (500e3 ); + spin =__spin_sync (gem_fd,0 ,e2ring (gem_fd, e)); fd =open_pmu (I915_PMU_ENGINE_BUSY (e->class, e->instance));
@@ -300,7 +361,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)* re-submission in execlists mode. Make sure busyness is correctly * reported with the engine busy, and after the engine went idle. */ - spin[0 ] =__igt_spin_batch_new (gem_fd,0 ,e2ring (gem_fd, e),0 ); + spin[0 ] =__spin_sync (gem_fd,0 ,e2ring (gem_fd, e));usleep (500e3 ); spin[1 ] =__igt_spin_batch_new (gem_fd, ctx,e2ring (gem_fd, e),0 );
@@ -386,7 +447,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,igt_assert_eq (i, num_engines); - spin =igt_spin_batch_new (gem_fd,0 ,e2ring (gem_fd, e),0 ); + spin =spin_sync (gem_fd,0 ,e2ring (gem_fd, e));pmu_read_multi (fd[0 ], num_engines, tval[0 ]); slept =measured_usleep (batch_duration_ns /1000 );if (flags &TEST_TRAILING_IDLE )
@@ -412,15 +473,15 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e, }static void -__submit_spin_batch (int gem_fd, -struct drm_i915_gem_exec_object2 *obj, -const struct intel_execution_engine2 *e) +__submit_spin_batch (int gem_fd,igt_spin_t *spin, +const struct intel_execution_engine2 *e, +int offset) { -struct drm_i915_gem_execbuffer2 eb = { - .buffer_count =1 , - .buffers_ptr =to_user_pointer (obj), - .flags =e2ring (gem_fd, e), - }; +struct drm_i915_gem_execbuffer2 eb = spin->execbuf; + + eb.flags &= ~(0x3f |I915_EXEC_BSD_MASK ); + eb.flags |=e2ring (gem_fd, e) |I915_EXEC_NO_RELOC ; + eb.batch_start_offset += offset;gem_execbuf (gem_fd, &eb); }
@@ -429,7 +490,6 @@ static void most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e, const unsigned int num_engines, unsigned int flags) { - struct drm_i915_gem_exec_object2 obj = {}; const struct intel_execution_engine2 *e_;uint64_t tval[2 ][num_engines];uint64_t val[num_engines];
@@ -443,15 +503,12 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,if (!gem_has_engine (gem_fd, e_->class, e_->instance))continue ; -if (e == e_) { +if (e == e_) idle_idx = i; - }else if (spin) { -__submit_spin_batch (gem_fd, &obj, e_); - }else { - spin =igt_spin_batch_new (gem_fd,0 , -e2ring (gem_fd, e_),0 ); - obj.handle = spin->handle; - } +else if (spin) +__submit_spin_batch (gem_fd, spin, e_,64 ); +else + spin =__spin_poll (gem_fd,0 ,e2ring (gem_fd, e_)); val[i++] =I915_PMU_ENGINE_BUSY (e_->class, e_->instance); }
@@ -461,6 +518,9 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,for (i =0 ; i < num_engines; i++) fd[i] =open_group (val[i], fd[0 ]); +/* Small delay to allow engines to start. */ +usleep (__spin_wait (gem_fd, spin) * num_engines /1e3 ); +pmu_read_multi (fd[0 ], num_engines, tval[0 ]); slept =measured_usleep (batch_duration_ns /1000 );if (flags &TEST_TRAILING_IDLE )
@@ -489,7 +549,6 @@ static void all_busy_check_all(int gem_fd, const unsigned int num_engines, unsigned int flags) { - struct drm_i915_gem_exec_object2 obj = {}; const struct intel_execution_engine2 *e;uint64_t tval[2 ][num_engines];uint64_t val[num_engines];
@@ -503,13 +562,10 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,if (!gem_has_engine (gem_fd, e->class, e->instance))continue ; -if (spin) { -__submit_spin_batch (gem_fd, &obj, e); - }else { - spin =igt_spin_batch_new (gem_fd,0 , -e2ring (gem_fd, e),0 ); - obj.handle = spin->handle; - } +if (spin) +__submit_spin_batch (gem_fd, spin, e,64 ); +else + spin =__spin_poll (gem_fd,0 ,e2ring (gem_fd, e)); val[i++] =I915_PMU_ENGINE_BUSY (e->class, e->instance); }
@@ -519,6 +575,9 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,for (i =0 ; i < num_engines; i++) fd[i] =open_group (val[i], fd[0 ]); +/* Small delay to allow engines to start. */ +usleep (__spin_wait (gem_fd, spin) * num_engines /1e3 ); +pmu_read_multi (fd[0 ], num_engines, tval[0 ]); slept =measured_usleep (batch_duration_ns /1000 );if (flags &TEST_TRAILING_IDLE )
@@ -550,7 +609,7 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)open_group (I915_PMU_ENGINE_WAIT (e->class, e->instance), fd);if (flags &TEST_BUSY ) - spin =igt_spin_batch_new (gem_fd,0 ,e2ring (gem_fd, e),0 ); + spin =spin_sync (gem_fd,0 ,e2ring (gem_fd, e));else spin =NULL ;
@@ -884,7 +943,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)*/ fd[1 ] =open_pmu (config); - spin =igt_spin_batch_new (gem_fd,0 ,e2ring (gem_fd, e),0 ); + spin =spin_sync (gem_fd,0 ,e2ring (gem_fd, e)); val[0 ] = val[1 ] =__pmu_read_single (fd[0 ], &ts[0 ]); slept[1 ] =measured_usleep (batch_duration_ns /1000 );
@@ -1248,7 +1307,7 @@ test_frequency(int gem_fd)igt_require (igt_sysfs_get_u32 (sysfs,"gt_boost_freq_mhz" ) == min_freq);gem_quiescent_gpu (gem_fd);/* Idle to be sure the change takes effect */ - spin =igt_spin_batch_new (gem_fd,0 ,I915_EXEC_RENDER ,0 ); + spin =spin_sync (gem_fd,0 ,I915_EXEC_RENDER ); slept =pmu_read_multi (fd,2 , start);measured_usleep (batch_duration_ns /1000 );
@@ -1274,7 +1333,7 @@ test_frequency(int gem_fd)igt_require (igt_sysfs_get_u32 (sysfs,"gt_min_freq_mhz" ) == max_freq);gem_quiescent_gpu (gem_fd); - spin =igt_spin_batch_new (gem_fd,0 ,I915_EXEC_RENDER ,0 ); + spin =spin_sync (gem_fd,0 ,I915_EXEC_RENDER ); slept =pmu_read_multi (fd,2 , start);measured_usleep (batch_duration_ns /1000 );
@@ -1517,7 +1576,6 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,const unsigned long timeout[] = { pwm_calibration_us *1000 , test_us *1000 }; -struct drm_i915_gem_exec_object2 obj = {};uint64_t total_busy_ns =0 , total_idle_ns =0 ;igt_spin_t *spin;int ret;
@@ -1531,11 +1589,8 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,/* Allocate our spin batch and idle it. */ spin =igt_spin_batch_new (gem_fd,0 ,e2ring (gem_fd, e),0 ); - obj.handle = spin->handle; -__submit_spin_batch (gem_fd, &obj, e);/* record its location */ igt_spin_batch_end (spin); -gem_sync (gem_fd, obj.handle); - obj.flags |=EXEC_OBJECT_PINNED ; +gem_sync (gem_fd, spin->handle);/* 1st pass is calibration, second pass is the test. */ for (int pass =0 ; pass <ARRAY_SIZE (timeout); pass++) {
@@ -1549,7 +1604,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,/* Restart the spinbatch. */ __rearm_spin_batch (spin); -__submit_spin_batch (gem_fd, &obj, e); +__submit_spin_batch (gem_fd, spin, e,0 );/* * Note that the submission may be delayed to a
@@ -1559,7 +1614,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e, t_busy =measured_usleep (busy_us);igt_spin_batch_end (spin); -gem_sync (gem_fd, obj.handle); +gem_sync (gem_fd, spin->handle); total_busy_ns += t_busy;
Signature · 6 lines
2.14.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] lib/dummyload: Add pollable spin batch
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: series starting with [i-g-t,1/3] lib/dummyload: Add pollable spin batch
URL : https://patchwork.freedesktop.org/series/40498/
State : success
== Summary ==
IGT patchset tested on top of latest successful build 0d5665783284fee1750bc4a9d7a0378cb5ce77fe lib: Run gem_test_engine() in an isolated context
with latest DRM-Tip kernel build CI_DRM_396840fcdd23bec7 drm-tip: 2018y-03m-22d-15h-28m-32s UTC integration manifest
Testlist changes:
+igt@gem_eio@in-flight-10ms
+igt@gem_eio@in-flight-10us
+igt@gem_eio@in-flight-contexts-10ms
+igt@gem_eio@in-flight-contexts-10us
+igt@gem_eio@in-flight-contexts-immediate
+igt@gem_eio@in-flight-immediate
+igt@gem_eio@in-flight-internal-10ms
+igt@gem_eio@in-flight-internal-10us
+igt@gem_eio@in-flight-internal-immediate
+igt@gem_eio@wait-10ms
+igt@gem_eio@wait-10us
+igt@gem_eio@wait-immediate
+igt@gem_eio@wait-wedge-10ms
+igt@gem_eio@wait-wedge-10us
+igt@gem_eio@wait-wedge-immediate
-igt@gem_eio@in-flight
-igt@gem_eio@in-flight-contexts
-igt@gem_eio@in-flight-internal
-igt@gem_eio@wait
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713 +1
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b-frame-sequence:
incomplete -> PASS (fi-cnl-y3) fdo#103191fdo#103713
fdo#102575
fdo#103191
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:431s fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:445s fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:382s fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:540s fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:297s fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:514s fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:514s fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:521s fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:505s fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:411s fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:510s fi-cnl-drrs total:285 pass:254 dwarn:3 dfail:0 fail:0 skip:28 time:541s fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:585s fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:428s fi-gdg-551 total:285 pass:177 dwarn:0 dfail:0 fail:0 skip:108 time:318s fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:535s fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:403s fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:422s fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:467s fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:432s fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:478s fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:465s fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:518s fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:654s fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:436s fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:530s fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:507s fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:497s fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:431s fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:449s fi-snb-2520m total:242 pass:208 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:399s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1183/issues.html
_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev
Patchwork
CI[igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/3] lib/dummyload: Add pollable spin batch
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: series starting with [i-g-t,1/3] lib/dummyload: Add pollable spin batch
URL : https://patchwork.freedesktop.org/series/40498/
State : failure
== Summary ==
---- Possible new issues:
Test gem_pwrite:
Subgroup big-cpu-forwards:
pass -> SKIP (shard-apl)
Test kms_vblank:
Subgroup pipe-a-ts-continuation-modeset-hang:
pass -> INCOMPLETE (shard-hsw)---- Known issues:
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (shard-hsw) fdo#100368
Subgroup dpms-vs-vblank-race:
fail -> PASS (shard-hsw) fdo#103060 +2fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
shard-apl total:3495 pass:1830 dwarn:1 dfail:0 fail:7 skip:1656 time:12915s shard-hsw total:3486 pass:1777 dwarn:1 dfail:0 fail:3 skip:1703 time:11184s shard-snb total:3495 pass:1374 dwarn:1 dfail:0 fail:3 skip:2117 time:7197s
Blacklisted hosts:
shard-kbl total:3477 pass:1926 dwarn:8 dfail:0 fail:10 skip:1532 time:9450s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1183/shards.html
_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev
Patchwork
CI[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] lib/dummyload: Add pollable spin batch (rev2)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: series starting with [i-g-t,1/3] lib/dummyload: Add pollable spin batch (rev2)
URL : https://patchwork.freedesktop.org/series/40498/
State : success
== Summary ==
IGT patchset tested on top of latest successful build c2ee90774496a9772f17a7a359d7a670bf7d6b85 meson: Chamelium depends on GSL
with latest DRM-Tip kernel build CI_DRM_3976101f8aec6229 drm-tip: 2018y-03m-23d-17h-52m-01s UTC integration manifest
Testlist changes:
+igt@gem_eio@in-flight-1us
+igt@gem_eio@in-flight-10ms
+igt@gem_eio@in-flight-contexts-1us
+igt@gem_eio@in-flight-contexts-10ms
+igt@gem_eio@in-flight-contexts-immediate
+igt@gem_eio@in-flight-immediate
+igt@gem_eio@in-flight-internal-1us
+igt@gem_eio@in-flight-internal-10ms
+igt@gem_eio@in-flight-internal-immediate
+igt@gem_eio@wait-1us
+igt@gem_eio@wait-10ms
+igt@gem_eio@wait-immediate
+igt@gem_eio@wait-wedge-1us
+igt@gem_eio@wait-wedge-10ms
+igt@gem_eio@wait-wedge-immediate
-igt@gem_eio@in-flight
-igt@gem_eio@in-flight-contexts
-igt@gem_eio@in-flight-internal
-igt@gem_eio@wait
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-cnl-y3) fdo#104951
Test prime_vgem:
Subgroup basic-fence-flip:
fail -> PASS (fi-ilk-650) fdo#104008fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:435s fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:444s fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:385s fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:539s fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:296s fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:512s fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:517s fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:526s fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:510s fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:410s fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:513s fi-cnl-y3 total:285 pass:258 dwarn:1 dfail:0 fail:0 skip:26 time:592s fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:429s fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:318s fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:539s fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:408s fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:423s fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:475s fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:432s fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:473s fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:468s fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:518s fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:655s fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:441s fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:531s fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:506s fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:498s fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:427s fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:448s fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:575s fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:408s Blacklisted hosts: fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:569s fi-cnl-psr total:224 pass:198 dwarn:0 dfail:0 fail:1 skip:24 fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:493s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1185/issues.html
_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev
Patchwork
CI[igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/3] lib/dummyload: Add pollable spin batch (rev2)
In reply to Tvrtko Ursulin== Series Details ==
== Series Details ==
Series: series starting with [i-g-t,1/3] lib/dummyload: Add pollable spin batch (rev2)
URL : https://patchwork.freedesktop.org/series/40498/
State : success
== Summary ==
---- Possible new issues:
Test pm_rc6_residency:
Subgroup rc6-accuracy:
skip -> PASS (shard-snb)---- Known issues:
Test kms_flip:
Subgroup 2x-plain-flip-fb-recreate-interruptible:
fail -> PASS (shard-hsw) fdo#100368 +2
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
pass -> FAIL (shard-snb) fdo#103925fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
shard-apl total:3495 pass:1831 dwarn:1 dfail:0 fail:7 skip:1655 time:12860s shard-hsw total:3495 pass:1783 dwarn:1 dfail:0 fail:1 skip:1709 time:11791s shard-snb total:3495 pass:1374 dwarn:1 dfail:0 fail:4 skip:2116 time:7026s
Blacklisted hosts:
shard-kbl total:3495 pass:1952 dwarn:1 dfail:0 fail:10 skip:1532 time:9745s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1185/shards.html
_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev