target/ppc: Fix reserved bit mask of dstst instruction
PATCH 1/1 target/ppc: Fix reserved bit mask of dstst instruction
According to the Vector/SIMD extension documentation bit 6 that is currently masked is valid (listed as transient bit) but bits 7 and 8 should be reserved instead. Fix the mask to match this.
--- target/ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
target/ppc/translate.c +1 -1
@@ -6561,7 +6561,7 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),GEN_HANDLER_E (dcbtls,0x1F ,0x06 ,0x05 ,0x02000001 ,PPC_BOOKE ,PPC2_BOOKE206 ),GEN_HANDLER (dcbz,0x1F ,0x16 ,0x1F ,0x03C00001 ,PPC_CACHE_DCBZ ),GEN_HANDLER (dst,0x1F ,0x16 ,0x0A ,0x01800001 ,PPC_ALTIVEC ), -GEN_HANDLER (dstst,0x1F ,0x16 ,0x0B ,0x02000001 ,PPC_ALTIVEC ), +GEN_HANDLER (dstst,0x1F ,0x16 ,0x0B ,0x01800001 ,PPC_ALTIVEC ),GEN_HANDLER (dss,0x1F ,0x16 ,0x19 ,0x019FF801 ,PPC_ALTIVEC ),GEN_HANDLER (icbi,0x1F ,0x16 ,0x1E ,0x03E00001 ,PPC_CACHE_ICBI ), GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
Signature · 1 line
2.7.6
Quoted 3 lines · BALATON Zoltan
According to the Vector/SIMD extension documentation bit 6 that is currently masked is valid (listed as transient bit) but bits 7 and 8 should be reserved instead. Fix the mask to match this.
What document can I find information on dstst in? The ISA documents I have handy are either too early (the instruction didn't exist yet) or too late (the instruction was considered obsolete and no details are given).
Quoted 18 lines
Signed-off-by BALATON Zoltan <[email protected]>--- target/ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)target/ppc/translate.c +1
-1@@ -6561,7 +6561,7 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),GEN_HANDLER_E (dcbtls,0x1F ,0x06 ,0x05 ,0x02000001 ,PPC_BOOKE ,PPC2_BOOKE206 ),GEN_HANDLER (dcbz,0x1F ,0x16 ,0x1F ,0x03C00001 ,PPC_CACHE_DCBZ ),GEN_HANDLER (dst,0x1F ,0x16 ,0x0A ,0x01800001 ,PPC_ALTIVEC ), -GEN_HANDLER (dstst,0x1F ,0x16 ,0x0B ,0x02000001 ,PPC_ALTIVEC ), +GEN_HANDLER (dstst,0x1F ,0x16 ,0x0B ,0x01800001 ,PPC_ALTIVEC ),GEN_HANDLER (dss,0x1F ,0x16 ,0x19 ,0x019FF801 ,PPC_ALTIVEC ),GEN_HANDLER (icbi,0x1F ,0x16 ,0x1E ,0x03E00001 ,PPC_CACHE_ICBI ), GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
Signature · 4 lines
David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
Quoted 9 lines · David Gibson
Quoted 3 lines · BALATON Zoltan
According to the Vector/SIMD extension documentation bit 6 that is currently masked is valid (listed as transient bit) but bits 7 and 8 should be reserved instead. Fix the mask to match this.
What document can I find information on dstst in? The ISA documents I have handy are either too early (the instruction didn't exist yet) or too late (the instruction was considered obsolete and no details are given).
I've found it in "PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual" Version 2.06 which was the first one Google found. According to this document dstst should have the same reserved bits as dst.
Regards,
BALATON Zoltan
Quoted 11 lines · BALATON Zoltan
Quoted 9 lines · David Gibson
Quoted 3 lines · BALATON Zoltan
According to the Vector/SIMD extension documentation bit 6 that is currently masked is valid (listed as transient bit) but bits 7 and 8 should be reserved instead. Fix the mask to match this.
What document can I find information on dstst in? The ISA documents I have handy are either too early (the instruction didn't exist yet) or too late (the instruction was considered obsolete and no details are given).
Quoted 4 lines
I've found it in "PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual" Version 2.06 which was the first one Google found. According to this document dstst should have the same reserved bits as dst.
Thanks.
Signature · 4 lines
David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
David Gibson
AppliedQuoted 5 lines · BALATON Zoltan
According to the Vector/SIMD extension documentation bit 6 that is currently masked is valid (listed as transient bit) but bits 7 and 8 should be reserved instead. Fix the mask to match this.
Signed-off-by BALATON Zoltan <[email protected]>
Applied to ppc-for-2.13, thanks.
Quoted 17 lines
--- target/ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)target/ppc/translate.c +1
-1@@ -6561,7 +6561,7 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),GEN_HANDLER_E (dcbtls,0x1F ,0x06 ,0x05 ,0x02000001 ,PPC_BOOKE ,PPC2_BOOKE206 ),GEN_HANDLER (dcbz,0x1F ,0x16 ,0x1F ,0x03C00001 ,PPC_CACHE_DCBZ ),GEN_HANDLER (dst,0x1F ,0x16 ,0x0A ,0x01800001 ,PPC_ALTIVEC ), -GEN_HANDLER (dstst,0x1F ,0x16 ,0x0B ,0x02000001 ,PPC_ALTIVEC ), +GEN_HANDLER (dstst,0x1F ,0x16 ,0x0B ,0x01800001 ,PPC_ALTIVEC ),GEN_HANDLER (dss,0x1F ,0x16 ,0x19 ,0x019FF801 ,PPC_ALTIVEC ),GEN_HANDLER (icbi,0x1F ,0x16 ,0x1E ,0x03E00001 ,PPC_CACHE_ICBI ), GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
Signature · 4 lines
David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson