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ARM: dts: imx6q-icore-ofcap12: Switch LVDS timings from panel-simple

PATCH Applied Jagan Teki 2 participants 3 messages Mar 26, 2018 – Apr 18, 2018

Subsystems (3)
Device tree bindings Arm i.MX and Layerscape Arm and arm64 SoC sub-architectures (common parts)
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Jagan Teki

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#0 lore raw

PATCH v4 1/1 ARM: dts: imx6q-icore-ofcap12: Switch LVDS timings from panel-simple

Switch to use koe_tx31d200vm0baa LVDS timings from panel-simple instead hard coding the same in dts.

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v4:
- Send as seprate patch from previous series
https://patchwork.kernel.org/patch/10199423/
Changes for v3, v2:
- none

 arch/arm/boot/dts/imx6q-icore-ofcap12.dts | 31 +++++++++++++++++--------------
 arch/arm/boot/dts/imx6qdl-icore.dtsi      |  2 +-
 2 files changed, 18 insertions(+), 15 deletions(-)
arch/arm/boot/dts/imx6q-icore-ofcap12.dts +17 -14
index 9e230f56c5fb..6e27c8143f82 100644
@@ -48,28 +48,31 @@
 / {
 	model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 12 Kit";
 	compatible = "engicam,imx6-icore", "fsl,imx6q";
+
+	panel {
+		compatible = "koe,tx31d200vm0baa";
+		backlight = <&backlight_lvds>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
 };
 
 &ldb {
 	status = "okay";
 
 	lvds-channel at 0 {
-		fsl,data-mapping = "spwg";
-		fsl,data-width = <18>;
+		reg = <0>;
 		status = "okay";
 
-		display-timings {
-			native-mode = <&timing0>;
-			timing0: timing0 {
-				clock-frequency = <46800000>;
-				hactive = <1280>;
-				vactive = <480>;
-				hback-porch = <353>;
-				hfront-porch = <47>;
-				vback-porch = <39>;
-				vfront-porch = <4>;
-				hsync-len = <8>;
-				vsync-len = <2>;
+		port at 4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in>;
 			};
 		};
 	};
arch/arm/boot/dts/imx6qdl-icore.dtsi +1 -1
index b3a463a5908b..1bce85c3376b 100644
@@ -49,7 +49,7 @@
 		reg = <0x10000000 0x80000000>;
 	};
 
-	backlight {
+	backlight_lvds: backlight-lvds {
 		compatible = "pwm-backlight";
 		pwms = <&pwm3 0 100000>;
 		brightness-levels = <0 4 8 16 32 64 128 255>;
Signature · 1 line
2.14.3
author
#1 lore raw

PATCH v4 1/1 ARM: dts: imx6q: Add Engicam i.CoreM6 1.5 Quad/Dual MIPI starter kit support

i.CoreM6 1.5 is an another i.CoreM6 QDL cpu modules which can be connected to EDIMM starter kit design with eMMC and MIPI-CSI interfaces suitable for Android and video capture application.

notable features:
CPU NXP i.MX6 S/DL/D/Q, Up to 4 x Cortex-A9 at 800MHz
Memory Up to 2 GB DDR3-1066
Video Interfaces Up to 1 Parallel Up to 2 LVDS HDMI 1.4
port 8 bit CSI INPUT MIPI-CSI INPUT
1 x 10/100 Ethernet interface, 2 x USB, 1 x PCIe, 1 x I2S etc

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v4:
- Send as seprate patch from previous series
https://patchwork.kernel.org/patch/10199429/
Changes for v3:
- none
Changes for v2:
- new patch

 arch/arm/boot/dts/Makefile             |  1 +
 arch/arm/boot/dts/imx6q-icore-mipi.dts | 25 +++++++++++++++++++++++++
 arch/arm/boot/dts/imx6qdl-icore.dtsi   | 23 +++++++++++++++++++++++
 3 files changed, 49 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6q-icore-mipi.dts
arch/arm/boot/dts/Makefile +1 -0
index 3b4cc1b64a1e..ac188ecee1a1 100644
@@ -463,6 +463,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6q-hummingboard2-emmc-som-v15.dtb \
 	imx6q-hummingboard2-som-v15.dtb \
 	imx6q-icore.dtb \
+	imx6q-icore-mipi.dtb \
 	imx6q-icore-ofcap10.dtb \
 	imx6q-icore-ofcap12.dtb \
 	imx6q-icore-rqs.dtb \
arch/arm/boot/dts/imx6q-icore-mipi.dts new file +25 -0
new file mode 100644
index 000000000000..acd3d33476d4
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Engicam S.r.l.
+ * Copyright (C) 2017 Amarula Solutions B.V.
+ * Author: Jagan Teki <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+	model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit";
+	compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&usdhc3 {
+	status = "okay";
+};
arch/arm/boot/dts/imx6qdl-icore.dtsi +23 -0
index 1bce85c3376b..0a1574998fc6 100644
@@ -265,6 +265,14 @@
 	status = "okay";
 };
 
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	no-1-8-v;
+	non-removable;
+	status = "disabled";
+};
+
 &iomuxc {
 	pinctrl_audmux: audmux {
 		fsl,pins = <

@@ -378,4 +386,19 @@
 			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
 		>;
 	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+		>;
+	};
 };
Signature · 1 line
2.14.3