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PCI: aardvark: misc fixes and improvements

PATCH Superseded Thomas Petazzoni 2 participants 18 messages Mar 27, 2018

Subsystems (2)
Stable branch PCI

v3 of 4 Superseded Latest is v4 →

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Thomas Petazzoni

author
#0 lore raw

v3 cover PCI: aardvark: misc fixes and improvements

Hello Bjorn,

This patch series brings a number of improvements to the aardvark PCIe. Sorry for being so slow at sending the v3 after the v2 sent in January. Hopefully this time around the series will be fine.

Changes since v2:

- Rebased on v4.16-rc7

- Dropped the patches disabling L0S and aligning the MPS between RC and EP, since we are working on a different solution, implementing a proper root port. Therefore, this patch series only has the (hopefully) non-controversial changes.

- Add a patch (PATCH 1) that factorizes the logic to decide if the target of a configuration space access is a valid device or not into a advk_pcie_valid_device() helper, and adjust PATCH 2 accordingly.

- Drop unused PCIE_BDF macro in PATCH 3.

Best regards,

Thomas Petazzoni

Evan Wang (2):
PCI: aardvark: fix PCIe max read request size setting
PCI: aardvark: remove PCIe outbound window configuration

Thomas Petazzoni (1):
PCI: aardvark: introduce an advk_pcie_valid_device() helper

Victor Gu (3):
PCI: aardvark: fix logic in advk_pcie_valid_device()
PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf()
PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode

 drivers/pci/host/pci-aardvark.c | 117 ++++++++++++++--------------------------
 1 file changed, 39 insertions(+), 78 deletions(-)
Signature · 1 line
2.14.3
author
#1 lore raw

PATCH v3 1/6 PCI: aardvark: introduce an advk_pcie_valid_device() helper

From: Thomas Petazzoni <[email protected]>

In other to mimic other PCIe host controller drivers, introduce an advk_pcie_valid_device() helper, used in the configuration read/write functions.

This patch by itself is not a fix, but it is required for a follow-up patch that is a fix, hence the Fixes tag and the Cc to stable.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Thomas Petazzoni <[email protected]>

---
Changes since v2:
- New patch

---
 drivers/pci/host/pci-aardvark.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)
drivers/pci/host/pci-aardvark.c +11 -2
index b04d37b3c5de..ccd0304a0c21 100644
@@ -430,6 +430,15 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
 	return -ETIMEDOUT;
 }
 
+static int advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
+				  int devfn)
+{
+	if (PCI_SLOT(devfn) != 0)
+		return false;
+
+	return true;
+}
+
 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
 			     int where, int size, u32 *val)
 {

@@ -437,7 +446,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
 	u32 reg;
 	int ret;
 
-	if (PCI_SLOT(devfn) != 0) {
+	if (!advk_pcie_valid_device(pcie, bus, devfn)) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}

@@ -491,7 +500,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 	int offset;
 	int ret;
 
-	if (PCI_SLOT(devfn) != 0)
+	if (!advk_pcie_valid_device(pcie, bus, devfn))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	if (where % size)
Signature · 1 line
2.14.3
author
#2 lore raw

PATCH v3 1/6 PCI: aardvark: introduce an advk_pcie_valid_device() helper

In reply to Thomas Petazzoni

From: Thomas Petazzoni <[email protected]>

In other to mimic other PCIe host controller drivers, introduce an advk_pcie_valid_device() helper, used in the configuration read/write functions.

This patch by itself is not a fix, but it is required for a follow-up patch that is a fix, hence the Fixes tag and the Cc to stable.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Thomas Petazzoni <[email protected]>

---
Changes since v2:
- New patch

---
 drivers/pci/host/pci-aardvark.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)
drivers/pci/host/pci-aardvark.c +11 -2
index b04d37b3c5de..ccd0304a0c21 100644
@@ -430,6 +430,15 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
 	return -ETIMEDOUT;
 }
 
+static int advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
+				  int devfn)
+{
+	if (PCI_SLOT(devfn) != 0)
+		return false;
+
+	return true;
+}
+
 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
 			     int where, int size, u32 *val)
 {

@@ -437,7 +446,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
 	u32 reg;
 	int ret;
 
-	if (PCI_SLOT(devfn) != 0) {
+	if (!advk_pcie_valid_device(pcie, bus, devfn)) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}

@@ -491,7 +500,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 	int offset;
 	int ret;
 
-	if (PCI_SLOT(devfn) != 0)
+	if (!advk_pcie_valid_device(pcie, bus, devfn))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	if (where % size)
Signature · 1 line
2.14.3
#3 lore raw

PATCH v3 1/6 PCI: aardvark: introduce an advk_pcie_valid_device() helper

Quoted 25 lines · Thomas Petazzoni

From: Thomas Petazzoni <[email protected]>

In other to mimic other PCIe host controller drivers, introduce an advk_pcie_valid_device() helper, used in the configuration read/write functions.

This patch by itself is not a fix, but it is required for a follow-up patch that is a fix, hence the Fixes tag and the Cc to stable.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Thomas Petazzoni <[email protected]>

---
Changes since v2:
- New patch

---
 drivers/pci/host/pci-aardvark.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)
drivers/pci/host/pci-aardvark.c +0 -0
index b04d37b3c5de..ccd0304a0c21 100644
@@ -430,6 +430,15 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
 	return -ETIMEDOUT;

drivers/pci/host/pci-aardvark.c static int advk_pcie_wait_pio(struct advk_pcie *pcie) · line 440

Quoted 10 lines
drivers/pci/host/pci-aardvark.c +8 -0
 }
 
+static int advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
+				  int devfn)
+{
+	if (PCI_SLOT(devfn) != 0)
+		return false;
+
+	return true;
+}

Thanks for following the style of the other drivers.

Some of them return int, some return bool. I don't really care which you use , but you should probably use one consistently, e.g., declare this as a bool function, or declare it as int and return 0/1.

author
#4 lore raw

PATCH v3 2/6 PCI: aardvark: fix logic in advk_pcie_valid_device()

In reply to Thomas Petazzoni

From: Victor Gu <[email protected]>

The PCI configuration space read/write functions were special casing the situation where PCI_SLOT(devfn) != 0, and returned PCIBIOS_DEVICE_NOT_FOUND in this case.

However, while this is what is intended for the root bus, it is not intended for the child busses, as it prevents discovering devices with PCI_SLOT(x) != 0. Therefore, we return PCIBIOS_DEVICE_NOT_FOUND only if we're on the root bus.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Victor Gu <[email protected]>
Reviewed-by Wilson Ding <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>

---
Changes since v2:
- The logic has been factorized into a advk_pcie_valid_device() helper in a previous patch, so this patch was adjusted accordingly.

---
 drivers/pci/host/pci-aardvark.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/host/pci-aardvark.c +1 -1
index ccd0304a0c21..be140dc7109b 100644
@@ -433,7 +433,7 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
 static int advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
 				  int devfn)
 {
-	if (PCI_SLOT(devfn) != 0)
+	if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
 		return false;
 
 	return true;
Signature · 1 line
2.14.3
author
#5 lore raw

PATCH v3 2/6 PCI: aardvark: fix logic in advk_pcie_valid_device()

In reply to Thomas Petazzoni

From: Victor Gu <[email protected]>

The PCI configuration space read/write functions were special casing the situation where PCI_SLOT(devfn) != 0, and returned PCIBIOS_DEVICE_NOT_FOUND in this case.

However, while this is what is intended for the root bus, it is not intended for the child busses, as it prevents discovering devices with PCI_SLOT(x) != 0. Therefore, we return PCIBIOS_DEVICE_NOT_FOUND only if we're on the root bus.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Victor Gu <[email protected]>
Reviewed-by Wilson Ding <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>

---
Changes since v2:
- The logic has been factorized into a advk_pcie_valid_device() helper in a previous patch, so this patch was adjusted accordingly.

---
 drivers/pci/host/pci-aardvark.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/host/pci-aardvark.c +1 -1
index ccd0304a0c21..be140dc7109b 100644
@@ -433,7 +433,7 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
 static int advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
 				  int devfn)
 {
-	if (PCI_SLOT(devfn) != 0)
+	if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
 		return false;
 
 	return true;
Signature · 1 line
2.14.3
author
#6 lore raw

PATCH v3 3/6 PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf()

In reply to Thomas Petazzoni

From: Victor Gu <[email protected]>

When setting the PIO_ADDR_LS register during a configuration read, we were properly passing the device number, function number and register number, but not the bus number, causing issues when reading the configuration of PCIe devices.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Victor Gu <[email protected]>
Reviewed-by Wilson Ding <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>

---
Changes since v2:
- Drop PCIE_BDF() macro, since it's no longer used. Noticed by Bjorn Helgaas.

---
 drivers/pci/host/pci-aardvark.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)
drivers/pci/host/pci-aardvark.c +1 -3
index be140dc7109b..4affbf1b826b 100644
@@ -172,8 +172,6 @@
 #define PCIE_CONFIG_WR_TYPE0			0xa
 #define PCIE_CONFIG_WR_TYPE1			0xb
 
-/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(dev)				(dev << 4)
 #define PCIE_CONF_BUS(bus)			(((bus) & 0xff) << 20)
 #define PCIE_CONF_DEV(dev)			(((dev) & 0x1f) << 15)
 #define PCIE_CONF_FUNC(fun)			(((fun) & 0x7)	<< 12)

@@ -465,7 +463,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
 	advk_writel(pcie, reg, PIO_CTRL);
 
 	/* Program the address registers */
-	reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
+	reg = PCIE_CONF_ADDR(bus->number, devfn, where);
 	advk_writel(pcie, reg, PIO_ADDR_LS);
 	advk_writel(pcie, 0, PIO_ADDR_MS);
Signature · 1 line
2.14.3
author
#7 lore raw

PATCH v3 3/6 PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf()

In reply to Thomas Petazzoni

From: Victor Gu <[email protected]>

When setting the PIO_ADDR_LS register during a configuration read, we were properly passing the device number, function number and register number, but not the bus number, causing issues when reading the configuration of PCIe devices.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Victor Gu <[email protected]>
Reviewed-by Wilson Ding <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>

---
Changes since v2:
- Drop PCIE_BDF() macro, since it's no longer used. Noticed by Bjorn Helgaas.

---
 drivers/pci/host/pci-aardvark.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)
drivers/pci/host/pci-aardvark.c +1 -3
index be140dc7109b..4affbf1b826b 100644
@@ -172,8 +172,6 @@
 #define PCIE_CONFIG_WR_TYPE0			0xa
 #define PCIE_CONFIG_WR_TYPE1			0xb
 
-/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(dev)				(dev << 4)
 #define PCIE_CONF_BUS(bus)			(((bus) & 0xff) << 20)
 #define PCIE_CONF_DEV(dev)			(((dev) & 0x1f) << 15)
 #define PCIE_CONF_FUNC(fun)			(((fun) & 0x7)	<< 12)

@@ -465,7 +463,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
 	advk_writel(pcie, reg, PIO_CTRL);
 
 	/* Program the address registers */
-	reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
+	reg = PCIE_CONF_ADDR(bus->number, devfn, where);
 	advk_writel(pcie, reg, PIO_ADDR_LS);
 	advk_writel(pcie, 0, PIO_ADDR_MS);
Signature · 1 line
2.14.3
author
#8 lore raw

v3 cover PCI: aardvark: misc fixes and improvements

In reply to Thomas Petazzoni

Hello Bjorn,

This patch series brings a number of improvements to the aardvark PCIe. Sorry for being so slow at sending the v3 after the v2 sent in January. Hopefully this time around the series will be fine.

Changes since v2:

- Rebased on v4.16-rc7

- Dropped the patches disabling L0S and aligning the MPS between RC and EP, since we are working on a different solution, implementing a proper root port. Therefore, this patch series only has the (hopefully) non-controversial changes.

- Add a patch (PATCH 1) that factorizes the logic to decide if the target of a configuration space access is a valid device or not into a advk_pcie_valid_device() helper, and adjust PATCH 2 accordingly.

- Drop unused PCIE_BDF macro in PATCH 3.

Best regards,

Thomas Petazzoni

Evan Wang (2):
PCI: aardvark: fix PCIe max read request size setting
PCI: aardvark: remove PCIe outbound window configuration

Thomas Petazzoni (1):
PCI: aardvark: introduce an advk_pcie_valid_device() helper

Victor Gu (3):
PCI: aardvark: fix logic in advk_pcie_valid_device()
PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf()
PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode

 drivers/pci/host/pci-aardvark.c | 117 ++++++++++++++--------------------------
 1 file changed, 39 insertions(+), 78 deletions(-)
Signature · 1 line
2.14.3
#9 lore raw

v3 cover PCI: aardvark: misc fixes and improvements

[+cc Lorenzo, who is now maintaining drivers/pci/host/]

Quoted 9 lines · Thomas Petazzoni

Hello Bjorn,

This patch series brings a number of improvements to the aardvark PCIe. Sorry for being so slow at sending the v3 after the v2 sent in January. Hopefully this time around the series will be fine.

Changes since v2:

- Rebased on v4.16-rc7

No need to rebase to anything other than "master" unless your series depends on something already merged.

Quoted 11 lines

Evan Wang (2):
PCI: aardvark: fix PCIe max read request size setting
PCI: aardvark: remove PCIe outbound window configuration

Thomas Petazzoni (1):
PCI: aardvark: introduce an advk_pcie_valid_device() helper

Victor Gu (3):
PCI: aardvark: fix logic in advk_pcie_valid_device()
PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf()
PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode

Please capitalize the first word of every title, e.g.,

PCI: aardvark: Remove PCIe outbound window configuration

and proper nouns, e.g., things directly defined by the spec, as "Max Read Request Size", as a hint that this has specific meaning and can be looked up:

PCI: aardvark: Fix PCIe Max Read Request Size setting

author
#10 lore raw

PATCH v3 4/6 PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode

In reply to Thomas Petazzoni

From: Victor Gu <[email protected]>

The Aardvark has two interrupts sets:

- first set is bit[23:16] of PCIe ISR 0 register(RD0074840h)

- second set is bit[11:8] of PCIe ISR 1 register(RD0074848h)

Only one set should be used, while another set should be masked.

The second set, ISR1, is more advanced, the Legacy INT_X status bit is asserted once Assert_INTX message is received, and de-asserted after Deassert_INTX message is received. Therefore, it matches what the driver is currently doing in the ->irq_mask() and ->irq_unmask() functions. The ISR0 requires additional work to deassert the interrupt, which the driver doesn't do currently.

This commit resolves a number of issues with legacy interrupts.

This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was reported as the user to be important to get a Intel 7260 mini-PCIe WiFi card working.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Victor Gu <[email protected]>
Reviewed-by Evan Wang <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>
---
 drivers/pci/host/pci-aardvark.c | 41 ++++++++++++++++++++++++-----------------
 1 file changed, 24 insertions(+), 17 deletions(-)
drivers/pci/host/pci-aardvark.c +24 -17
index 4affbf1b826b..c6cd7b17868f 100644
@@ -100,7 +100,8 @@
 #define PCIE_ISR1_MASK_REG			(CONTROL_BASE_ADDR + 0x4C)
 #define     PCIE_ISR1_POWER_STATE_CHANGE	BIT(4)
 #define     PCIE_ISR1_FLUSH			BIT(5)
-#define     PCIE_ISR1_ALL_MASK			GENMASK(5, 4)
+#define     PCIE_ISR1_INTX_ASSERT(val)		BIT(8 + (val))
+#define     PCIE_ISR1_ALL_MASK			GENMASK(11, 4)
 #define PCIE_MSI_ADDR_LOW_REG			(CONTROL_BASE_ADDR + 0x50)
 #define PCIE_MSI_ADDR_HIGH_REG			(CONTROL_BASE_ADDR + 0x54)
 #define PCIE_MSI_STATUS_REG			(CONTROL_BASE_ADDR + 0x58)

@@ -616,9 +617,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 	u32 mask;
 
-	mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
-	mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
-	advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+	mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
+	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
 }
 
 static void advk_pcie_irq_unmask(struct irq_data *d)

@@ -627,9 +628,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 	u32 mask;
 
-	mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
-	mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
-	advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+	mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
+	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
 }
 
 static int advk_pcie_irq_map(struct irq_domain *h,

@@ -772,29 +773,35 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
 
 static void advk_pcie_handle_int(struct advk_pcie *pcie)
 {
-	u32 val, mask, status;
+	u32 isr0_val, isr0_mask, isr0_status;
+	u32 isr1_val, isr1_mask, isr1_status;
 	int i, virq;
 
-	val = advk_readl(pcie, PCIE_ISR0_REG);
-	mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
-	status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
+	isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
+	isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
+	isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
 
-	if (!status) {
-		advk_writel(pcie, val, PCIE_ISR0_REG);
+	isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
+	isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+	isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
+
+	if (!isr0_status && !isr1_status) {
+		advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
+		advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
 		return;
 	}
 
 	/* Process MSI interrupts */
-	if (status & PCIE_ISR0_MSI_INT_PENDING)
+	if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
 		advk_pcie_handle_msi(pcie);
 
 	/* Process legacy interrupts */
 	for (i = 0; i < PCI_NUM_INTX; i++) {
-		if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
+		if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
 			continue;
 
-		advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
-			    PCIE_ISR0_REG);
+		advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
+			    PCIE_ISR1_REG);
 
 		virq = irq_find_mapping(pcie->irq_domain, i);
 		generic_handle_irq(virq);
Signature · 1 line
2.14.3
author
#11 lore raw

PATCH v3 4/6 PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode

In reply to Thomas Petazzoni

From: Victor Gu <[email protected]>

The Aardvark has two interrupts sets:

- first set is bit[23:16] of PCIe ISR 0 register(RD0074840h)

- second set is bit[11:8] of PCIe ISR 1 register(RD0074848h)

Only one set should be used, while another set should be masked.

The second set, ISR1, is more advanced, the Legacy INT_X status bit is asserted once Assert_INTX message is received, and de-asserted after Deassert_INTX message is received. Therefore, it matches what the driver is currently doing in the ->irq_mask() and ->irq_unmask() functions. The ISR0 requires additional work to deassert the interrupt, which the driver doesn't do currently.

This commit resolves a number of issues with legacy interrupts.

This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was reported as the user to be important to get a Intel 7260 mini-PCIe WiFi card working.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Victor Gu <[email protected]>
Reviewed-by Evan Wang <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>
---
 drivers/pci/host/pci-aardvark.c | 41 ++++++++++++++++++++++++-----------------
 1 file changed, 24 insertions(+), 17 deletions(-)
drivers/pci/host/pci-aardvark.c +24 -17
index 4affbf1b826b..c6cd7b17868f 100644
@@ -100,7 +100,8 @@
 #define PCIE_ISR1_MASK_REG			(CONTROL_BASE_ADDR + 0x4C)
 #define     PCIE_ISR1_POWER_STATE_CHANGE	BIT(4)
 #define     PCIE_ISR1_FLUSH			BIT(5)
-#define     PCIE_ISR1_ALL_MASK			GENMASK(5, 4)
+#define     PCIE_ISR1_INTX_ASSERT(val)		BIT(8 + (val))
+#define     PCIE_ISR1_ALL_MASK			GENMASK(11, 4)
 #define PCIE_MSI_ADDR_LOW_REG			(CONTROL_BASE_ADDR + 0x50)
 #define PCIE_MSI_ADDR_HIGH_REG			(CONTROL_BASE_ADDR + 0x54)
 #define PCIE_MSI_STATUS_REG			(CONTROL_BASE_ADDR + 0x58)

@@ -616,9 +617,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 	u32 mask;
 
-	mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
-	mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
-	advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+	mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
+	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
 }
 
 static void advk_pcie_irq_unmask(struct irq_data *d)

@@ -627,9 +628,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 	u32 mask;
 
-	mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
-	mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
-	advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+	mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
+	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
 }
 
 static int advk_pcie_irq_map(struct irq_domain *h,

@@ -772,29 +773,35 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
 
 static void advk_pcie_handle_int(struct advk_pcie *pcie)
 {
-	u32 val, mask, status;
+	u32 isr0_val, isr0_mask, isr0_status;
+	u32 isr1_val, isr1_mask, isr1_status;
 	int i, virq;
 
-	val = advk_readl(pcie, PCIE_ISR0_REG);
-	mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
-	status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
+	isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
+	isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
+	isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
 
-	if (!status) {
-		advk_writel(pcie, val, PCIE_ISR0_REG);
+	isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
+	isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+	isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
+
+	if (!isr0_status && !isr1_status) {
+		advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
+		advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
 		return;
 	}
 
 	/* Process MSI interrupts */
-	if (status & PCIE_ISR0_MSI_INT_PENDING)
+	if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
 		advk_pcie_handle_msi(pcie);
 
 	/* Process legacy interrupts */
 	for (i = 0; i < PCI_NUM_INTX; i++) {
-		if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
+		if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
 			continue;
 
-		advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
-			    PCIE_ISR0_REG);
+		advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
+			    PCIE_ISR1_REG);
 
 		virq = irq_find_mapping(pcie->irq_domain, i);
 		generic_handle_irq(virq);
Signature · 1 line
2.14.3
author
#12 lore raw

PATCH v3 5/6 PCI: aardvark: fix PCIe max read request size setting

In reply to Thomas Petazzoni

From: Evan Wang <[email protected]>

There is an obvious typo issue in the definition of the PCIe maximum read request size: a bit shift is directly used as a value, while it should be used to shift the correct value.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Evan Wang <[email protected]>
Reviewed-by Victor Gu <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>
---
 drivers/pci/host/pci-aardvark.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/pci/host/pci-aardvark.c +3 -1
index c6cd7b17868f..d0688dc6b6d9 100644
@@ -29,6 +29,7 @@
 #define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT	5
 #define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE		(0 << 11)
 #define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT	12
+#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ		0x2
 #define PCIE_CORE_LINK_CTRL_STAT_REG				0xd0
 #define     PCIE_CORE_LINK_L0S_ENTRY				BIT(0)
 #define     PCIE_CORE_LINK_TRAINING				BIT(5)

@@ -295,7 +296,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
 		(7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
 		PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
-		PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
+		(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
+		 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
 	advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
 
 	/* Program PCIe Control 2 to disable strict ordering */
Signature · 1 line
2.14.3
author
#13 lore raw

PATCH v3 5/6 PCI: aardvark: fix PCIe max read request size setting

In reply to Thomas Petazzoni

From: Evan Wang <[email protected]>

There is an obvious typo issue in the definition of the PCIe maximum read request size: a bit shift is directly used as a value, while it should be used to shift the correct value.

Fixes 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc <[email protected]>
Signed-off-by Evan Wang <[email protected]>
Reviewed-by Victor Gu <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>
---
 drivers/pci/host/pci-aardvark.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/pci/host/pci-aardvark.c +3 -1
index c6cd7b17868f..d0688dc6b6d9 100644
@@ -29,6 +29,7 @@
 #define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT	5
 #define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE		(0 << 11)
 #define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT	12
+#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ		0x2
 #define PCIE_CORE_LINK_CTRL_STAT_REG				0xd0
 #define     PCIE_CORE_LINK_L0S_ENTRY				BIT(0)
 #define     PCIE_CORE_LINK_TRAINING				BIT(5)

@@ -295,7 +296,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
 		(7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
 		PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
-		PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
+		(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
+		 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
 	advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
 
 	/* Program PCIe Control 2 to disable strict ordering */
Signature · 1 line
2.14.3
author
#14 lore raw

PATCH v3 6/6 PCI: aardvark: remove PCIe outbound window configuration

In reply to Thomas Petazzoni

From: Evan Wang <[email protected]>

Outbound window is used to translate CPU space addresses to PCIe space addresses when the CPU initiates PCIe transactions.

According to the suggestion of the HW designers, the recommended solution is to use the default outbound parameters, even though the current outbound window setting does not cause any known functional issue.

This patch doesn't address any known functional issue, but aligns to HW design guidelines, and removes code that isn't needed.

Signed-off-by Evan Wang <[email protected]>
Reviewed-by Victor Gu <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>
---
 drivers/pci/host/pci-aardvark.c | 55 -----------------------------------------
 1 file changed, 55 deletions(-)
drivers/pci/host/pci-aardvark.c +0 -55
index d0688dc6b6d9..d0559152b8e1 100644
@@ -109,24 +109,6 @@
 #define PCIE_MSI_MASK_REG			(CONTROL_BASE_ADDR + 0x5C)
 #define PCIE_MSI_PAYLOAD_REG			(CONTROL_BASE_ADDR + 0x9C)
 
-/* PCIe window configuration */
-#define OB_WIN_BASE_ADDR			0x4c00
-#define OB_WIN_BLOCK_SIZE			0x20
-#define OB_WIN_REG_ADDR(win, offset)		(OB_WIN_BASE_ADDR + \
-						 OB_WIN_BLOCK_SIZE * (win) + \
-						 (offset))
-#define OB_WIN_MATCH_LS(win)			OB_WIN_REG_ADDR(win, 0x00)
-#define OB_WIN_MATCH_MS(win)			OB_WIN_REG_ADDR(win, 0x04)
-#define OB_WIN_REMAP_LS(win)			OB_WIN_REG_ADDR(win, 0x08)
-#define OB_WIN_REMAP_MS(win)			OB_WIN_REG_ADDR(win, 0x0c)
-#define OB_WIN_MASK_LS(win)			OB_WIN_REG_ADDR(win, 0x10)
-#define OB_WIN_MASK_MS(win)			OB_WIN_REG_ADDR(win, 0x14)
-#define OB_WIN_ACTIONS(win)			OB_WIN_REG_ADDR(win, 0x18)
-
-/* PCIe window types */
-#define OB_PCIE_MEM				0x0
-#define OB_PCIE_IO				0x4
-
 /* LMI registers base address and register offsets */
 #define LMI_BASE_ADDR				0x6000
 #define CFG_REG					(LMI_BASE_ADDR + 0x0)

@@ -245,34 +227,9 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
 	return -ETIMEDOUT;
 }
 
-/*
- * Set PCIe address window register which could be used for memory
- * mapping.
- */
-static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
-				 u32 win_num, u32 match_ms,
-				 u32 match_ls, u32 mask_ms,
-				 u32 mask_ls, u32 remap_ms,
-				 u32 remap_ls, u32 action)
-{
-	advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
-	advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
-	advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
-	advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
-	advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
-	advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
-	advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
-	advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
-}
-
 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 {
 	u32 reg;
-	int i;
-
-	/* Point PCIe unit MBUS decode windows to DRAM space */
-	for (i = 0; i < 8; i++)
-		advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
 
 	/* Set to Direct mode */
 	reg = advk_readl(pcie, CTRL_CONFIG_REG);

@@ -851,12 +808,6 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
 
 		switch (resource_type(res)) {
 		case IORESOURCE_IO:
-			advk_pcie_set_ob_win(pcie, 1,
-					     upper_32_bits(res->start),
-					     lower_32_bits(res->start),
-					     0,	0xF8000000, 0,
-					     lower_32_bits(res->start),
-					     OB_PCIE_IO);
 			err = pci_remap_iospace(res, iobase);
 			if (err) {
 				dev_warn(dev, "error %d: failed to map resource %pR\n",

@@ -865,12 +816,6 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
 			}
 			break;
 		case IORESOURCE_MEM:
-			advk_pcie_set_ob_win(pcie, 0,
-					     upper_32_bits(res->start),
-					     lower_32_bits(res->start),
-					     0x0, 0xF8000000, 0,
-					     lower_32_bits(res->start),
-					     (2 << 20) | OB_PCIE_MEM);
 			res_valid |= !(res->flags & IORESOURCE_PREFETCH);
 			break;
 		case IORESOURCE_BUS:
Signature · 1 line
2.14.3
author
#15 lore raw

PATCH v3 6/6 PCI: aardvark: remove PCIe outbound window configuration

In reply to Thomas Petazzoni

From: Evan Wang <[email protected]>

Outbound window is used to translate CPU space addresses to PCIe space addresses when the CPU initiates PCIe transactions.

According to the suggestion of the HW designers, the recommended solution is to use the default outbound parameters, even though the current outbound window setting does not cause any known functional issue.

This patch doesn't address any known functional issue, but aligns to HW design guidelines, and removes code that isn't needed.

Signed-off-by Evan Wang <[email protected]>
Reviewed-by Victor Gu <[email protected]>
Reviewed-by Nadav Haklai <[email protected]>
[Thomas: tweak commit log.]
Signed-off-by Thomas Petazzoni <[email protected]>
---
 drivers/pci/host/pci-aardvark.c | 55 -----------------------------------------
 1 file changed, 55 deletions(-)
drivers/pci/host/pci-aardvark.c +0 -55
index d0688dc6b6d9..d0559152b8e1 100644
@@ -109,24 +109,6 @@
 #define PCIE_MSI_MASK_REG			(CONTROL_BASE_ADDR + 0x5C)
 #define PCIE_MSI_PAYLOAD_REG			(CONTROL_BASE_ADDR + 0x9C)
 
-/* PCIe window configuration */
-#define OB_WIN_BASE_ADDR			0x4c00
-#define OB_WIN_BLOCK_SIZE			0x20
-#define OB_WIN_REG_ADDR(win, offset)		(OB_WIN_BASE_ADDR + \
-						 OB_WIN_BLOCK_SIZE * (win) + \
-						 (offset))
-#define OB_WIN_MATCH_LS(win)			OB_WIN_REG_ADDR(win, 0x00)
-#define OB_WIN_MATCH_MS(win)			OB_WIN_REG_ADDR(win, 0x04)
-#define OB_WIN_REMAP_LS(win)			OB_WIN_REG_ADDR(win, 0x08)
-#define OB_WIN_REMAP_MS(win)			OB_WIN_REG_ADDR(win, 0x0c)
-#define OB_WIN_MASK_LS(win)			OB_WIN_REG_ADDR(win, 0x10)
-#define OB_WIN_MASK_MS(win)			OB_WIN_REG_ADDR(win, 0x14)
-#define OB_WIN_ACTIONS(win)			OB_WIN_REG_ADDR(win, 0x18)
-
-/* PCIe window types */
-#define OB_PCIE_MEM				0x0
-#define OB_PCIE_IO				0x4
-
 /* LMI registers base address and register offsets */
 #define LMI_BASE_ADDR				0x6000
 #define CFG_REG					(LMI_BASE_ADDR + 0x0)

@@ -245,34 +227,9 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
 	return -ETIMEDOUT;
 }
 
-/*
- * Set PCIe address window register which could be used for memory
- * mapping.
- */
-static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
-				 u32 win_num, u32 match_ms,
-				 u32 match_ls, u32 mask_ms,
-				 u32 mask_ls, u32 remap_ms,
-				 u32 remap_ls, u32 action)
-{
-	advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
-	advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
-	advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
-	advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
-	advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
-	advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
-	advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
-	advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
-}
-
 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 {
 	u32 reg;
-	int i;
-
-	/* Point PCIe unit MBUS decode windows to DRAM space */
-	for (i = 0; i < 8; i++)
-		advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
 
 	/* Set to Direct mode */
 	reg = advk_readl(pcie, CTRL_CONFIG_REG);

@@ -851,12 +808,6 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
 
 		switch (resource_type(res)) {
 		case IORESOURCE_IO:
-			advk_pcie_set_ob_win(pcie, 1,
-					     upper_32_bits(res->start),
-					     lower_32_bits(res->start),
-					     0,	0xF8000000, 0,
-					     lower_32_bits(res->start),
-					     OB_PCIE_IO);
 			err = pci_remap_iospace(res, iobase);
 			if (err) {
 				dev_warn(dev, "error %d: failed to map resource %pR\n",

@@ -865,12 +816,6 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
 			}
 			break;
 		case IORESOURCE_MEM:
-			advk_pcie_set_ob_win(pcie, 0,
-					     upper_32_bits(res->start),
-					     lower_32_bits(res->start),
-					     0x0, 0xF8000000, 0,
-					     lower_32_bits(res->start),
-					     (2 << 20) | OB_PCIE_MEM);
 			res_valid |= !(res->flags & IORESOURCE_PREFETCH);
 			break;
 		case IORESOURCE_BUS:
Signature · 1 line
2.14.3
author
#16 lore raw

v3 cover PCI: aardvark: misc fixes and improvements

In reply to Thomas Petazzoni

Hello Bjorn,

Quoted 3 lines · Thomas Petazzoni

This patch series brings a number of improvements to the aardvark PCIe. Sorry for being so slow at sending the v3 after the v2 sent in January. Hopefully this time around the series will be fine.

Sorry, I screwed up. I'm not sure how, but I did. The series was sent twice, and only the second iteration is correct, the first one lacked some Cc: to stable.

I have marked the bogus patches as Superseded in patchwork, so if you look at patchwork, you will only see the patches worth considering.

Let me know if you would like to resend anyway.

Sorry again for the mess,

Thomas Petazzoni

Signature · 3 lines
Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
#17 lore raw

v3 cover PCI: aardvark: misc fixes and improvements

Quoted 6 lines · Thomas Petazzoni
Quoted 3 lines · Thomas Petazzoni

This patch series brings a number of improvements to the aardvark PCIe. Sorry for being so slow at sending the v3 after the v2 sent in January. Hopefully this time around the series will be fine.

Quoted 8 lines

Sorry, I screwed up. I'm not sure how, but I did. The series was sent twice, and only the second iteration is correct, the first one lacked some Cc: to stable.

I have marked the bogus patches as Superseded in patchwork, so if you look at patchwork, you will only see the patches worth considering.

Let me know if you would like to resend anyway.

No worries, no need to resend for that. And also no need to resend to rebase them.

Lorenzo is out this week, but I'm sure he'll look at them when he returns. They all look pretty straightforward and obviously only affect aardvark, so we may still be able to squeeze them in for v4.17.

Bjorn