powerpc tlbie reductions again
Subsystems (2)
Nicholas Piggin
maintainercover powerpc tlbie reductions again
Last time this came up, there was concern about whether we can trim the mm cpumask, and what concurrency there is vs use_mm(). I've had more of a look and still think this is okay. I haven't thought of a good way to add debug checks to ensure it though.
When doing a parallel kernel build on a 2 socket P9 system, this series causes tlbie (broadcast) to go from 1.37 million (22k/sec) to 181 thousand (3k/sec).
tlbiel (local) flushes increase from 20.2 to 23.7 million. Due to requiring 128 tlbiel (vs 1 tlbie) to flush a PID, and also we set the cutoff higher before we switch from va range to full PID flush, when doing tlbiel.
End result performance was very little changed, very tiny improvement maybe but well under 1%. Kernel compile mostly stays off the interconnect, and this is a small system, and without nMMU involvement. Any of these factors could make broadcast tlbie reduction more important.
Remaining work - ensuring correctness of this stuff, implementations for hash, understanding and testing nMMU cases better, using IPIs for some/all types of invalidations, then possibly looking at doing something more fancy with the PID allocator.
Nicholas Piggin (3):
powerpc/64s: do not flush TLB when relaxing access powerpc/64s/radix: reset mm_cpumask for single thread process when
possible
powerpc/64s: always flush non-local CPUs from single threaded mms
arch/powerpc/include/asm/mmu_context.h | 33 ++++++++++---- arch/powerpc/include/asm/tlb.h | 7 +++ arch/powerpc/mm/pgtable-book3s64.c | 1 - arch/powerpc/mm/pgtable.c | 3 +- arch/powerpc/mm/tlb-radix.c | 78 +++++++++++++++++++++++++--------- 5 files changed, 92 insertions(+), 30 deletions(-)
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2.16.1
Nicholas Piggin
maintainerRFC PATCH 1/3 powerpc/64s: do not flush TLB when relaxing access
Book3S does not require TLB flushing when protection is being relaxed.
Quoted 1 line
From Power ISA v3.0B, p.1090:
Setting a Reference or Change Bit or Upgrading Access Authority (PTE Subject to Atomic Hardware Updates)
If the only change being made to a valid PTE that is subject to atomic hardware updates is to set the Refer- ence or Change bit to 1 or to add access authorities, a simpler sequence suffices because the translation hardware will refetch the PTE if an access is attempted for which the only problems were reference and/or change bits needing to be set or insufficient access authority.
--- arch/powerpc/mm/pgtable-book3s64.c | 1 - arch/powerpc/mm/pgtable.c | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-)
arch/powerpc/mm/pgtable-book3s64.c +0 -1
@@ -40,7 +40,6 @@ int pmdp_set_access_flags(struct vm_area_struct *vma, unsigned long address,if (changed) {__ptep_set_access_flags (vma->vm_mm,pmdp_ptep (pmdp),pmd_pte (entry), address); -flush_pmd_tlb_range (vma, address, address +HPAGE_PMD_SIZE ); }return changed; }
arch/powerpc/mm/pgtable.c +2 -1
@@ -224,7 +224,8 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,if (!is_vm_hugetlb_page (vma))assert_pte_locked (vma->vm_mm, address);__ptep_set_access_flags (vma->vm_mm, ptep, entry, address); -flush_tlb_page (vma, address); +if (!IS_ENABLED (CONFIG_PPC_BOOK3S_64 )) +flush_tlb_page (vma, address); }return changed; }
Signature · 1 line
2.16.1
Nicholas Piggin
maintainerRFC PATCH 2/3 powerpc/64s/radix: reset mm_cpumask for single thread process when possible
In reply to Nicholas PigginWhen a single-threaded process has a non-local mm_cpumask and requires a full PID tlbie invalidation, use that as an opportunity to reset the cpumask back to the current CPU we're running on.
No other thread can concurrently switch to this mm, because it must have had a reference on mm_users before it could use_mm. mm_users can be asynchronously incremented e.g., by mmget_not_zero, but those users should not be doing use_mm.
--- arch/powerpc/include/asm/mmu_context.h | 33 +++++++++++++++----- arch/powerpc/include/asm/tlb.h | 7 +++++ arch/powerpc/mm/tlb-radix.c | 57 +++++++++++++++++++++++++--------- 3 files changed, 75 insertions(+), 22 deletions(-)
arch/powerpc/include/asm/mmu_context.h +25 -8
@@ -6,6 +6,7 @@#include <linux/kernel.h> #include <linux/mm.h> #include <linux/sched.h> +#include <linux/sched/mm.h> #include <linux/spinlock.h> #include <asm/mmu.h> #include <asm/cputable.h>
@@ -102,13 +103,6 @@ static inline void mm_context_add_copro(struct mm_struct *mm)static inline void mm_context_remove_copro (struct mm_struct *mm) { -int c; - - c =atomic_dec_if_positive (&mm->context.copros); - -/* Detect imbalance between add and remove */ -WARN_ON (c <0 ); -/* * Need to broadcast a global flush of the full mm before * decrementing active_cpus count, as the next TLBI may be
@@ -119,10 +113,15 @@ static inline void mm_context_remove_copro(struct mm_struct *mm)* for the time being. Invalidations will remain global if * used on hash. */ -if (c ==0 &&radix_enabled ()) { +if (radix_enabled ()) {flush_all_mm (mm);dec_mm_active_cpus (mm); } + +/* Detect imbalance between add and remove */ +WARN_ON (!atomic_read (&mm->context.copros)); + atomic_dec(&mm->context.copros); + }#else static inline void inc_mm_active_cpus (struct mm_struct *mm) { }
@@ -162,6 +161,24 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)static inline void enter_lazy_tlb (struct mm_struct *mm,struct task_struct *tsk) { +#ifdef CONFIG_PPC_BOOK3S_64 +/* +* Under radix, we do not want to keep lazy PIDs around because +* even if the CPU does not access userspace, it can still bring +* in translations through speculation and prefetching. +* +* Switching away here allows us to trim back the mm_cpumask in +* cases where we know the process is not running on some CPUs +* (see mm/tlb-radix.c). +*/ +if (radix_enabled () && mm != &init_mm) { +mmgrab (&init_mm); + tsk->active_mm = &init_mm; +switch_mm_irqs_off (mm, tsk->active_mm, tsk); +mmdrop (mm); + } +#endif +/* 64-bit Book3E keeps track of current PGD in the PACA */ #ifdef CONFIG_PPC_BOOK3E_64 get_paca ()->pgd =NULL ;
arch/powerpc/include/asm/tlb.h +7 -0
@@ -76,6 +76,13 @@ static inline int mm_is_thread_local(struct mm_struct *mm)return false;return cpumask_test_cpu (smp_processor_id (),mm_cpumask (mm)); } +static inline void mm_reset_thread_local (struct mm_struct *mm) +{ +WARN_ON (!(atomic_read (&mm->mm_users) ==1 && current->mm == mm)); +atomic_set (&mm->context.active_cpus,1 ); +cpumask_clear (mm_cpumask (mm)); +cpumask_set_cpu (smp_processor_id (),mm_cpumask (mm)); +}#else /* CONFIG_PPC_BOOK3S_64 */ static inline int mm_is_thread_local (struct mm_struct *mm) {
arch/powerpc/mm/tlb-radix.c +43 -14
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2.16.1
Nicholas Piggin
maintainerRFC PATCH 3/3 powerpc/64s: always flush non-local CPUs from single threaded mms
In reply to Nicholas PigginGo one step further, if we're going to put a tlbie on the bus at all, make it count. Always flush all others and restore our mm to a local one.
--- arch/powerpc/mm/tlb-radix.c | 45 +++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 18 deletions(-)
arch/powerpc/mm/tlb-radix.c +27 -18
@@ -424,10 +424,16 @@ void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,return ;preempt_disable (); -if (!mm_is_thread_local (mm)) -_tlbie_va (vmaddr, pid, psize,RIC_FLUSH_TLB ); -else +if (mm_is_thread_local (mm)) {_tlbiel_va (vmaddr, pid, psize,RIC_FLUSH_TLB ); + }else { +if (mm_is_singlethreaded (mm)) { +_tlbie_pid (pid,RIC_FLUSH_ALL ); +mm_reset_thread_local (mm); + }else { +_tlbie_va (vmaddr, pid, psize,RIC_FLUSH_TLB ); + } + }preempt_enable (); }
@@ -496,14 +502,14 @@ void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start, nr_pages > tlb_single_page_flush_ceiling); } -if (full) { +if (!local &&mm_is_singlethreaded (mm)) { +_tlbie_pid (pid,RIC_FLUSH_ALL ); +mm_reset_thread_local (mm); + }else if (full) {if (local) {_tlbiel_pid (pid,RIC_FLUSH_TLB ); }else { -if (mm_is_singlethreaded (mm)) { -_tlbie_pid (pid,RIC_FLUSH_ALL ); -mm_reset_thread_local (mm); - }else if (mm_needs_flush_escalation (mm)) { +if (mm_needs_flush_escalation (mm)) {_tlbie_pid (pid,RIC_FLUSH_ALL ); }else {_tlbie_pid (pid,RIC_FLUSH_TLB );
@@ -618,19 +624,17 @@ static inline void __radix__flush_tlb_range_psize(struct mm_struct *mm, nr_pages > tlb_single_page_flush_ceiling); } -if (full) { +if (!local &&mm_is_singlethreaded (mm)) { +_tlbie_pid (pid,RIC_FLUSH_ALL ); +mm_reset_thread_local (mm); + }else if (full) {if (local) {_tlbiel_pid (pid, also_pwc ?RIC_FLUSH_ALL :RIC_FLUSH_TLB ); }else { -if (mm_is_singlethreaded (mm)) { -_tlbie_pid (pid,RIC_FLUSH_ALL ); -mm_reset_thread_local (mm); - }else { -if (mm_needs_flush_escalation (mm)) - also_pwc = true; +if (mm_needs_flush_escalation (mm)) + also_pwc = true; -_tlbie_pid (pid, also_pwc ?RIC_FLUSH_ALL :RIC_FLUSH_TLB ); - } +_tlbie_pid (pid, also_pwc ?RIC_FLUSH_ALL :RIC_FLUSH_TLB ); } }else {if (local)
@@ -676,7 +680,12 @@ void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)if (mm_is_thread_local (mm)) {_tlbiel_va_range (addr, end, pid,PAGE_SIZE , mmu_virtual_psize, true); }else { -_tlbie_va_range (addr, end, pid,PAGE_SIZE , mmu_virtual_psize, true); +if (mm_is_singlethreaded (mm)) { +_tlbie_pid (pid,RIC_FLUSH_ALL ); +mm_reset_thread_local (mm); + }else { +_tlbie_va_range (addr, end, pid,PAGE_SIZE , mmu_virtual_psize, true); + } }preempt_enable ();
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2.16.1