idle improvements again

PATCH Applied Nicholas Piggin 2 participants 5 messages Apr 1, 2018 – Apr 4, 2018 PowerPC

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Nicholas Piggin

author reviewer

2018-04-01 05:49 UTC #0 lore raw

v3 cover idle improvements again

Since last time, this has been rebased on top of the KVM / SMT4 forcing changes. It has also been updated so as to not disable EC=ESL=0 idle states for CPU unplug.

That case (and powersave=off) continues to be broken for KVM with unplugged dependent secondaries, but that's another issue.

This also has EC=ESL=0 states to skip the new hwsync added for the KVM workaround, which should increase their performance advantage a little further.

Thanks,
Nick

Nicholas Piggin (3):
powerpc/64s/idle: POWER9 implement a separate idle stop function for
hotplug
powerpc/64s/idle: avoid sync for KVM state when waking from idle powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

 arch/powerpc/include/asm/processor.h  |  1 +
 arch/powerpc/kernel/idle_book3s.S     | 69 +++++++++++++++++------------------
 arch/powerpc/platforms/powernv/idle.c |  2 +-
 3 files changed, 36 insertions(+), 36 deletions(-)

Signature · 1 line

2.16.3

Nicholas Piggin

author reviewer

2018-04-01 05:49 UTC #1 lore raw

PATCH v3 1/3 powerpc/64s/idle: POWER9 implement a separate idle stop function for hotplug

Implement a new function to invoke stop, power9_offline_stop, which is like power9_idle_stop but used by the cpu hotplug code.

Move KVM secondary state manipulation code to the offline case.

Cc Vaidyanathan Srinivasan <[email protected]>

Cc Gautham R. Shenoy <[email protected]>

Cc Paul Mackerras <[email protected]>

Signed-off-by Nicholas Piggin <[email protected]>

---
 arch/powerpc/include/asm/processor.h  |  1 +
 arch/powerpc/kernel/idle_book3s.S     | 21 +++++++++++++++------
 arch/powerpc/platforms/powernv/idle.c |  2 +-
 3 files changed, 17 insertions(+), 7 deletions(-)

arch/powerpc/include/asm/processor.h +1 -0

index bb9cb25ffb20..c4b36a494a63 100644
@@ -518,6 +518,7 @@ extern int powersave_nap;	/* set if nap mode can be used in idle loop */
 extern unsigned long power7_idle_insn(unsigned long type); /* PNV_THREAD_NAP/etc*/
 extern void power7_idle_type(unsigned long type);
 extern unsigned long power9_idle_stop(unsigned long psscr_val);
+extern unsigned long power9_offline_stop(unsigned long psscr_val);
 extern void power9_idle_type(unsigned long stop_psscr_val,
 			      unsigned long stop_psscr_mask);

arch/powerpc/kernel/idle_book3s.S +15 -6

index d503203842b0..fc2e5cf2c74c 100644
@@ -325,12 +325,6 @@ enter_winkle:
  * r3 - PSSCR value corresponding to the requested stop state.
  */
 power_enter_stop:
-#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
-	/* Tell KVM we're entering idle */
-	li	r4,KVM_HWTHREAD_IN_IDLE
-	/* DO THIS IN REAL MODE!  See comment above. */
-	stb	r4,HSTATE_HWTHREAD_STATE(r13)
-#endif
 /*
  * Check if we are executing the lite variant with ESL=EC=0
  */

@@ -428,7 +422,22 @@ ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66);		\
 /*
  * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
  * r3 contains desired PSSCR register value.
+ *
+ * Offline (CPU unplug) case also must notify KVM that the CPU is
+ * idle.
  */
+_GLOBAL(power9_offline_stop)
+#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
+	/*
+	 * Tell KVM we're entering idle.
+	 * This does not have to be done in real mode because the P9 MMU
+	 * is independent per-thread. Some steppings share radix/hash mode
+	 * between threads, but in that case KVM has a barrier sync in real
+	 * mode before and after switching between radix and hash.
+	 */
+	li	r4,KVM_HWTHREAD_IN_IDLE
+	stb	r4,HSTATE_HWTHREAD_STATE(r13)
+#endif
 _GLOBAL(power9_idle_stop)
 	std	r3, PACA_REQ_PSSCR(r13)
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE

arch/powerpc/platforms/powernv/idle.c +1 -1

index d9e366bb23da..378fde1f85a8 100644
@@ -511,7 +511,7 @@ unsigned long pnv_cpu_offline(unsigned int cpu)
 		psscr = mfspr(SPRN_PSSCR);
 		psscr = (psscr & ~pnv_deepest_stop_psscr_mask) |
 						pnv_deepest_stop_psscr_val;
-		srr1 = power9_idle_stop(psscr);
+		srr1 = power9_offline_stop(psscr);
 
 	} else if ((idle_states & OPAL_PM_WINKLE_ENABLED) &&
 		   (idle_states & OPAL_PM_LOSE_FULL_CONTEXT)) {

Signature · 1 line

2.16.3

Nicholas Piggin

author reviewer

2018-04-01 05:49 UTC #2 lore raw

PATCH v3 2/3 powerpc/64s/idle: avoid sync for KVM state when waking from idle

In reply to Nicholas Piggin

When waking from a CPU idle instruction (e.g., nap or stop), the sync for ordering the KVM secondary thread state can be avoided if there wakeup is coming from a kernel context rather than KVM context.

This improves performance for ping-pong benchmark with the stop0 idle state by 0.46% for 2 threads in the same core, and 1.02% for different cores.

Cc Vaidyanathan Srinivasan <[email protected]>

Cc Gautham R. Shenoy <[email protected]>

Cc Paul Mackerras <[email protected]>

Signed-off-by Nicholas Piggin <[email protected]>

---
 arch/powerpc/kernel/idle_book3s.S | 3 +++
 1 file changed, 3 insertions(+)

arch/powerpc/kernel/idle_book3s.S +3 -0

index fc2e5cf2c74c..68fa97885fc0 100644
@@ -549,6 +549,9 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
 	mr	r3,r12
 
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
+	lbz	r0,HSTATE_HWTHREAD_STATE(r13)
+	cmpwi	r0,KVM_HWTHREAD_IN_KERNEL
+	beq	1f
 	li	r0,KVM_HWTHREAD_IN_KERNEL
 	stb	r0,HSTATE_HWTHREAD_STATE(r13)
 	/* Order setting hwthread_state vs. testing hwthread_req */

Signature · 1 line

2.16.3

Nicholas Piggin

author reviewer

2018-04-01 05:49 UTC #3 lore raw

PATCH v3 3/3 powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

In reply to Nicholas Piggin

When stop is executed with EC=ESL=0, it appears to execute like a normal instruction (resuming from NIP when woken by interrupt). So all the save/restore handling can be avoided completely. In particular NV GPRs do not have to be saved, and MSR does not have to be switched back to kernel MSR.

So move the test for EC=ESL=0 sleep states out to power9_idle_stop, and return directly to the caller after stop in that case.

This improves performance for ping-pong benchmark with the stop0_lite idle state by 2.54% for 2 threads in the same core, and 2.57% for different cores. Performance increase with HV_POSSIBLE defined will be improved further by avoiding the hwsync.

Cc Vaidyanathan Srinivasan <[email protected]>

Cc Gautham R. Shenoy <[email protected]>

Cc Paul Mackerras <[email protected]>

Signed-off-by Nicholas Piggin <[email protected]>

---
 arch/powerpc/kernel/idle_book3s.S | 45 ++++++++++++++-------------------------
 1 file changed, 16 insertions(+), 29 deletions(-)

arch/powerpc/kernel/idle_book3s.S +16 ~~-29~~

index 68fa97885fc0..dedcd78a204a 100644
@@ -324,32 +324,8 @@ enter_winkle:
 /*
  * r3 - PSSCR value corresponding to the requested stop state.
  */
-power_enter_stop:
-/*
- * Check if we are executing the lite variant with ESL=EC=0
- */
-	andis.   r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
+power_enter_stop_esl:
 	clrldi   r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
-	bne	 .Lhandle_esl_ec_set
-	PPC_STOP
-	li	r3,0  /* Since we didn't lose state, return 0 */
-	std	r3, PACA_REQ_PSSCR(r13)
-
-	/*
-	 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so
-	 * it can determine if the wakeup reason is an HMI in
-	 * CHECK_HMI_INTERRUPT.
-	 *
-	 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup
-	 * reason, so there is no point setting r12 to SRR1.
-	 *
-	 * Further, we clear r12 here, so that we don't accidentally enter the
-	 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.
-	 */
-	li	r12, 0
-	b 	pnv_wakeup_noloss
-
-.Lhandle_esl_ec_set:
 BEGIN_FTR_SECTION
 	/*
 	 * POWER9 DD2.0 or earlier can incorrectly set PMAO when waking up after

@@ -439,21 +415,32 @@ _GLOBAL(power9_offline_stop)
 	stb	r4,HSTATE_HWTHREAD_STATE(r13)
 #endif
 _GLOBAL(power9_idle_stop)
+	mtspr 	SPRN_PSSCR,r3
+	/*
+	 * The ESL=EC=0 case does not wake up at 0x100, and it does not
+	 * allow SMT mode switching, so it does not require PSSCR to be
+	 * saved.
+	 */
+	andis.	r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
+	bne	1f
+	PPC_STOP
+	li	r3,0  /* Since we didn't lose state, return 0 */
+	blr
+1:
 	std	r3, PACA_REQ_PSSCR(r13)
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 BEGIN_FTR_SECTION
 	sync
 	lwz	r5, PACA_DONT_STOP(r13)
 	cmpwi	r5, 0
-	bne	1f
+	bne	2f
 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
 #endif
-	mtspr 	SPRN_PSSCR,r3
-	LOAD_REG_ADDR(r4,power_enter_stop)
+	LOAD_REG_ADDR(r4,power_enter_stop_esl)
 	b	pnv_powersave_common
 	/* No return */
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
-1:
+2:
 	/*
 	 * We get here when TM / thread reconfiguration bug workaround
 	 * code wants to get the CPU into SMT4 mode, and therefore

Signature · 1 line

2.16.3

Michael Ellerman

Applied

2018-04-04 14:39 UTC #4 lore raw

Re: [v3, 3/3] powerpc/64s/idle: POWER9 ESL=0 stop avoid save/restore overhead

Quoted 14 lines · Nicholas Piggin

When stop is executed with EC=ESL=0, it appears to execute like a normal instruction (resuming from NIP when woken by interrupt). So all the save/restore handling can be avoided completely. In particular NV GPRs do not have to be saved, and MSR does not have to be switched back to kernel MSR.
So move the test for EC=ESL=0 sleep states out to power9_idle_stop, and return directly to the caller after stop in that case.
This improves performance for ping-pong benchmark with the stop0_lite idle state by 2.54% for 2 threads in the same core, and 2.57% for different cores. Performance increase with HV_POSSIBLE defined will be improved further by avoiding the hwsync.

Quoted 4 lines

Cc Vaidyanathan Srinivasan <[email protected]>
Cc Gautham R. Shenoy <[email protected]>
Cc Paul Mackerras <[email protected]>
Signed-off-by Nicholas Piggin <[email protected]>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/b9ee31e100e73075431faaf7af2ee0

cheers