Cleanup for Amlogic GX SoCs
Subsystems (3)
cover Cleanup for Amlogic GX SoCs
The Amlogic Meson GXBB and GXL are both part of the GX SoC family, this patchset renames the GXBB files and defines to take this fact in account and align the namings with linux.
With this applied, we can add a SoC Info code to display the SoC name and package marketing name along the revisions.
Example output :
[...]
U-Boot 2018.03-00004-g69704da (Mar 28 2018 - 11:39:17 +0200) libretech-cc
CPU: Amlogic Meson GXL (S905X) rev 21:b (82:2)
DRAM: 2 GiB
[...]
On the LibreTech-CC board.
This patchset depends on the "mmc: avoid division by zero in meson_mmc_config_clock" patch to allow U-Boot to work correctly.
Neil Armstrong (2):
ARM: meson: rename GXBB to GX
ARM: meson: Add cpu info display for GX SoCs
arch/arm/include/asm/arch-meson/{gxbb.h => gx.h} | 91 +++++++++---------
arch/arm/mach-meson/Makefile | 2 +-
arch/arm/mach-meson/board.c | 28 +++---
arch/arm/mach-meson/cpu_info.c | 105 +++++++++++++++++++++
arch/arm/mach-meson/eth.c | 24 ++---
arch/arm/mach-meson/sm.c | 2 +-
board/amlogic/khadas-vim/khadas-vim.c | 2 +-
board/amlogic/libretech-cc/libretech-cc.c | 6 +-
board/amlogic/odroid-c2/odroid-c2.c | 10 +-
board/amlogic/p212/p212.c | 2 +-
configs/khadas-vim_defconfig | 2 +-
configs/libretech-cc_defconfig | 2 +-
configs/odroid-c2_defconfig | 2 +-
configs/odroid_defconfig | 1 +
configs/p212_defconfig | 2 +-
include/configs/khadas-vim.h | 2 +-
include/configs/libretech-cc.h | 2 +-
.../{meson-gxbb-common.h => meson-gx-common.h} | 8 +-
include/configs/odroid-c2.h | 2 +-
include/configs/p212.h | 2 +-
20 files changed, 202 insertions(+), 95 deletions(-)
rename arch/arm/include/asm/arch-meson/{gxbb.h => gx.h} (13%)
create mode 100644 arch/arm/mach-meson/cpu_info.c
rename include/configs/{meson-gxbb-common.h => meson-gx-common.h} (86%)Signature · 1 line
2.7.4
PATCH 1/2 ARM: meson: rename GXBB to GX
Taking into account the Amlogic Family name starts with GX, including the GXBB, GXL and GXM SoCs.
---
arch/arm/include/asm/arch-meson/{gxbb.h => gx.h} | 90 +++++++++++-----------
arch/arm/mach-meson/board.c | 28 +++----
arch/arm/mach-meson/eth.c | 24 +++---
arch/arm/mach-meson/sm.c | 2 +-
board/amlogic/khadas-vim/khadas-vim.c | 2 +-
board/amlogic/libretech-cc/libretech-cc.c | 6 +-
board/amlogic/odroid-c2/odroid-c2.c | 10 +--
board/amlogic/p212/p212.c | 2 +-
include/configs/khadas-vim.h | 2 +-
include/configs/libretech-cc.h | 2 +-
.../{meson-gxbb-common.h => meson-gx-common.h} | 8 +-
include/configs/odroid-c2.h | 2 +-
include/configs/p212.h | 2 +-
13 files changed, 90 insertions(+), 90 deletions(-)
rename arch/arm/include/asm/arch-meson/{gxbb.h => gx.h} (13%)
rename include/configs/{meson-gxbb-common.h => meson-gx-common.h} (86%)arch/arm/include/asm/arch-meson/gx.h renamed from arch/arm/include/asm/arch-meson/gxbb.h +45 -45
@@ -4,67 +4,67 @@* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __GXBB_H__ -#define __GXBB_H__ +#ifndef __GX_H__ +#define __GX_H__ -#define GXBB_FIRMWARE_MEM_SIZE 0x1000000 +#define GX_FIRMWARE_MEM_SIZE 0x1000000 -#define GXBB_AOBUS_BASE 0xc8100000 -#define GXBB_PERIPHS_BASE 0xc8834400 -#define GXBB_HIU_BASE 0xc883c000 -#define GXBB_ETH_BASE 0xc9410000 +#define GX_AOBUS_BASE 0xc8100000 +#define GX_PERIPHS_BASE 0xc8834400 +#define GX_HIU_BASE 0xc883c000 +#define GX_ETH_BASE 0xc9410000/* Always-On Peripherals registers */ -#define GXBB_AO_ADDR (off) (GXBB_AOBUS_BASE + ((off) << 2)) +#define GX_AO_ADDR (off) (GX_AOBUS_BASE + ((off) << 2)) -#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90) -#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93) -#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94) -#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95) +#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90) +#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93) +#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) +#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) -#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000 -#define GXBB_AO_MEM_SIZE_SHIFT 16 -#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 -#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16 -#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF +#define GX_AO_MEM_SIZE_MASK 0xFFFF0000 +#define GX_AO_MEM_SIZE_SHIFT 16 +#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF/* Peripherals registers */ -#define GXBB_PERIPHS_ADDR (off) (GXBB_PERIPHS_BASE + ((off) << 2)) +#define GX_PERIPHS_ADDR (off) (GX_PERIPHS_BASE + ((off) << 2))/* GPIO registers 0 to 6 */ -#define _GXBB_GPIO_OFF (n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) -#define GXBB_GPIO_EN (n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0) -#define GXBB_GPIO_IN (n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1) -#define GXBB_GPIO_OUT (n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2) - -#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50) -#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51) -#define GXBB_ETH_REG_2 GXBB_PERIPHS_ADDR(0x56) -#define GXBB_ETH_REG_3 GXBB_PERIPHS_ADDR(0x57) - -#define GXBB_ETH_REG_0_PHY_INTF BIT(0) -#define GXBB_ETH_REG_0_TX_PHASE (x) (((x) & 3) << 5) -#define GXBB_ETH_REG_0_TX_RATIO (x) (((x) & 7) << 7) -#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10) -#define GXBB_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define GXBB_ETH_REG_0_CLK_EN BIT(12) +#define _GX_GPIO_OFF (n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) +#define GX_GPIO_EN (n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0) +#define GX_GPIO_IN (n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) +#define GX_GPIO_OUT (n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) + +#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50) +#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51) +#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56) +#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57) + +#define GX_ETH_REG_0_PHY_INTF BIT(0) +#define GX_ETH_REG_0_TX_PHASE (x) (((x) & 3) << 5) +#define GX_ETH_REG_0_TX_RATIO (x) (((x) & 7) << 7) +#define GX_ETH_REG_0_PHY_CLK_EN BIT(10) +#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define GX_ETH_REG_0_CLK_EN BIT(12)/* HIU registers */ -#define GXBB_HIU_ADDR (off) (GXBB_HIU_BASE + ((off) << 2)) +#define GX_HIU_ADDR (off) (GX_HIU_BASE + ((off) << 2)) -#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40) +#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40)/* Ethernet memory power domain */ -#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) +#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))/* Clock gates */ -#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50) -#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51) -#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52) -#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53) -#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54) +#define GX_GCLK_MPEG_0 GX_HIU_ADDR(0x50) +#define GX_GCLK_MPEG_1 GX_HIU_ADDR(0x51) +#define GX_GCLK_MPEG_2 GX_HIU_ADDR(0x52) +#define GX_GCLK_MPEG_OTHER GX_HIU_ADDR(0x53) +#define GX_GCLK_MPEG_AO GX_HIU_ADDR(0x54) -#define GXBB_GCLK_MPEG_0_I2C BIT(9) -#define GXBB_GCLK_MPEG_1_ETH BIT(3) +#define GX_GCLK_MPEG_0_I2C BIT(9) +#define GX_GCLK_MPEG_1_ETH BIT(3) -#endif /* __GXBB_H__ */ +#endif /* __GX_H__ */
arch/arm/mach-meson/board.c +14 -14
@@ -7,7 +7,7 @@#include <common.h> #include <linux/libfdt.h> #include <linux/err.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <asm/arch/sm.h> #include <asm/armv8/mmu.h> #include <asm/unaligned.h>
@@ -40,8 +40,8 @@ int dram_init(void)phys_size_t get_effective_memsize (void ) {/* Size is reported in MiB, convert it in bytes */ -return ((readl (GXBB_AO_SEC_GP_CFG0 ) &GXBB_AO_MEM_SIZE_MASK ) - >>GXBB_AO_MEM_SIZE_SHIFT ) *SZ_1M ; +return ((readl (GX_AO_SEC_GP_CFG0 ) &GX_AO_MEM_SIZE_MASK ) + >>GX_AO_MEM_SIZE_SHIFT ) *SZ_1M ; }static void meson_board_add_reserved_memory (void *fdt,u64 start,u64 size)
@@ -72,27 +72,27 @@ void meson_gx_init_reserved_memory(void *fdt)* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL */ - reg =readl (GXBB_AO_SEC_GP_CFG3 ); + reg =readl (GX_AO_SEC_GP_CFG3 ); - bl31_size = ((reg &GXBB_AO_BL31_RSVMEM_SIZE_MASK ) - >>GXBB_AO_BL31_RSVMEM_SIZE_SHIFT ) *SZ_1K ; - bl32_size = (reg &GXBB_AO_BL32_RSVMEM_SIZE_MASK ) *SZ_1K ; + bl31_size = ((reg &GX_AO_BL31_RSVMEM_SIZE_MASK ) + >>GX_AO_BL31_RSVMEM_SIZE_SHIFT ) *SZ_1K ; + bl32_size = (reg &GX_AO_BL32_RSVMEM_SIZE_MASK ) *SZ_1K ; - bl31_start =readl (GXBB_AO_SEC_GP_CFG5 ); - bl32_start =readl (GXBB_AO_SEC_GP_CFG4 ); + bl31_start =readl (GX_AO_SEC_GP_CFG5 ); + bl32_start =readl (GX_AO_SEC_GP_CFG4 );/* -* Early Meson GXBB Firmware revisions did not provide the reserved +* Early Meson GX Firmware revisions did not provide the reserved * memory zones in the registers, keep fixed memory zone handling. */ -if (IS_ENABLED (CONFIG_MESON_GXBB ) && +if (IS_ENABLED (CONFIG_MESON_GX ) && !reg && !bl31_start && !bl32_start) { bl31_start =0x10000000 ; bl31_size =0x200000 ; }/* Add first 16MiB reserved zone */ -meson_board_add_reserved_memory (fdt,0 ,GXBB_FIRMWARE_MEM_SIZE ); +meson_board_add_reserved_memory (fdt,0 ,GX_FIRMWARE_MEM_SIZE );/* Add BL31 reserved zone */ if (bl31_start && bl31_size)
@@ -108,7 +108,7 @@ void reset_cpu(ulong addr)psci_system_reset (); } -static struct mm_region gxbb_mem_map[] = { +static struct mm_region gx_mem_map[] = { { .virt =0x0UL , .phys =0x0UL ,
@@ -128,4 +128,4 @@ static struct mm_region gxbb_mem_map[] = { } }; -struct mm_region *mem_map = gxbb_mem_map; +struct mm_region *mem_map = gx_mem_map;
arch/arm/mach-meson/eth.c +12 -12
@@ -8,7 +8,7 @@#include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <asm/arch/eth.h> #include <phy.h>
@@ -23,23 +23,23 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)case PHY_INTERFACE_MODE_RGMII_RXID :case PHY_INTERFACE_MODE_RGMII_TXID :/* Set RGMII mode */ -setbits_le32 (GXBB_ETH_REG_0 ,GXBB_ETH_REG_0_PHY_INTF | -GXBB_ETH_REG_0_TX_PHASE (1 ) | -GXBB_ETH_REG_0_TX_RATIO (4 ) | -GXBB_ETH_REG_0_PHY_CLK_EN | -GXBB_ETH_REG_0_CLK_EN ); +setbits_le32 (GX_ETH_REG_0 ,GX_ETH_REG_0_PHY_INTF | +GX_ETH_REG_0_TX_PHASE (1 ) | +GX_ETH_REG_0_TX_RATIO (4 ) | +GX_ETH_REG_0_PHY_CLK_EN | +GX_ETH_REG_0_CLK_EN );break ;case PHY_INTERFACE_MODE_RMII :/* Set RMII mode */ -out_le32 (GXBB_ETH_REG_0 ,GXBB_ETH_REG_0_INVERT_RMII_CLK | -GXBB_ETH_REG_0_CLK_EN ); +out_le32 (GX_ETH_REG_0 ,GX_ETH_REG_0_INVERT_RMII_CLK | +GX_ETH_REG_0_CLK_EN );/* Use GXL RMII Internal PHY */ if (IS_ENABLED (CONFIG_MESON_GXL ) && (flags &MESON_GXL_USE_INTERNAL_RMII_PHY )) { -writel (0x10110181 ,GXBB_ETH_REG_2 ); -writel (0xe40908ff ,GXBB_ETH_REG_3 ); +writel (0x10110181 ,GX_ETH_REG_2 ); +writel (0xe40908ff ,GX_ETH_REG_3 ); }break ;
@@ -50,6 +50,6 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) }/* Enable power and clock gate */ -setbits_le32 (GXBB_GCLK_MPEG_1 ,GXBB_GCLK_MPEG_1_ETH ); -clrbits_le32 (GXBB_MEM_PD_REG_0 ,GXBB_MEM_PD_REG_0_ETH_MASK ); +setbits_le32 (GX_GCLK_MPEG_1 ,GX_GCLK_MPEG_1_ETH ); +clrbits_le32 (GX_MEM_PD_REG_0 ,GX_MEM_PD_REG_0_ETH_MASK ); }
arch/arm/mach-meson/sm.c +1 -1
@@ -7,7 +7,7 @@*/ #include <common.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <linux/kernel.h> #define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020
board/amlogic/khadas-vim/khadas-vim.c +1 -1
@@ -8,7 +8,7 @@#include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <asm/arch/mem.h> #include <asm/arch/sm.h> #include <asm/arch/eth.h>
board/amlogic/libretech-cc/libretech-cc.c +3 -3
@@ -8,7 +8,7 @@#include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <asm/arch/sm.h> #include <asm/arch/eth.h> #include <asm/arch/mem.h>
@@ -33,8 +33,8 @@ int misc_init_r(void) MESON_GXL_USE_INTERNAL_RMII_PHY);/* Enable power and clock gate */ -setbits_le32 (GXBB_GCLK_MPEG_1 ,GXBB_GCLK_MPEG_1_ETH ); -clrbits_le32 (GXBB_MEM_PD_REG_0 ,GXBB_MEM_PD_REG_0_ETH_MASK ); +setbits_le32 (GX_GCLK_MPEG_1 ,GX_GCLK_MPEG_1_ETH ); +clrbits_le32 (GX_MEM_PD_REG_0 ,GX_MEM_PD_REG_0_ETH_MASK );if (!eth_env_get_enetaddr ("ethaddr" , mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
board/amlogic/odroid-c2/odroid-c2.c +5 -5
@@ -7,7 +7,7 @@#include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <asm/arch/sm.h> #include <asm/arch/eth.h> #include <asm/arch/mem.h>
@@ -31,13 +31,13 @@ int misc_init_r(void)meson_gx_eth_init (PHY_INTERFACE_MODE_RGMII ,0 );/* Enable power and clock gate */ -setbits_le32 (GXBB_GCLK_MPEG_0 ,GXBB_GCLK_MPEG_0_I2C ); +setbits_le32 (GX_GCLK_MPEG_0 ,GX_GCLK_MPEG_0_I2C );/* Reset PHY on GPIOZ_14 */ -clrbits_le32 (GXBB_GPIO_EN (3 ),BIT (14 )); -clrbits_le32 (GXBB_GPIO_OUT (3 ),BIT (14 )); +clrbits_le32 (GX_GPIO_EN (3 ),BIT (14 )); +clrbits_le32 (GX_GPIO_OUT (3 ),BIT (14 ));mdelay (10 ); -setbits_le32 (GXBB_GPIO_OUT (3 ),BIT (14 )); +setbits_le32 (GX_GPIO_OUT (3 ),BIT (14 ));if (!eth_env_get_enetaddr ("ethaddr" , mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
board/amlogic/p212/p212.c +1 -1
@@ -8,7 +8,7 @@#include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/gxbb.h> +#include <asm/arch/gx.h> #include <asm/arch/sm.h> #include <asm/arch/eth.h> #include <asm/arch/mem.h>
include/configs/khadas-vim.h +1 -1
@@ -16,6 +16,6 @@#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0" -#include <configs/meson-gxbb-common.h> +#include <configs/meson-gx-common.h> #endif /* __CONFIG_H */
include/configs/libretech-cc.h +1 -1
@@ -16,6 +16,6 @@#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0" -#include <configs/meson-gxbb-common.h> +#include <configs/meson-gx-common.h> #endif /* __CONFIG_H */
include/configs/meson-gx-common.h renamed from include/configs/meson-gxbb-common.h +4 -4
@@ -1,12 +1,12 @@/* -* Configuration for Amlogic Meson GXBB SoCs +* Configuration for Amlogic Meson GX SoCs * (C) Copyright 2016 Beniamino Galvani <[email protected]> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __MESON_GXBB_COMMON_CONFIG_H -#define __MESON_GXBB_COMMON_CONFIG_H +#ifndef __MESON_GX_COMMON_CONFIG_H +#define __MESON_GX_COMMON_CONFIG_H#define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF
@@ -44,4 +44,4 @@#define CONFIG_SYS_BOOTM_LEN (64 << 20)/* 64 MiB */ -#endif /* __MESON_GXBB_COMMON_CONFIG_H */ +#endif /* __MESON_GX_COMMON_CONFIG_H */
include/configs/odroid-c2.h +1 -1
@@ -15,6 +15,6 @@#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0" -#include <configs/meson-gxbb-common.h> +#include <configs/meson-gx-common.h> #endif /* __CONFIG_H */
include/configs/p212.h +1 -1
@@ -19,6 +19,6 @@#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0" -#include <configs/meson-gxbb-common.h> +#include <configs/meson-gx-common.h> #endif /* __CONFIG_H */
Signature · 1 line
2.7.4
PATCH 1/2 ARM: meson: rename GXBB to GX
Quoted 4 lines · Neil Armstrong
Taking into account the Amlogic Family name starts with GX, including the GXBB, GXL and GXM SoCs.
Signed-off-by Neil Armstrong <[email protected]>
Hi,
looks good to me, but perhaps can you align again register values and other macros in gx.h?
Beniamino
PATCH 1/2 ARM: meson: rename GXBB to GX
Quoted 4 lines · Beniamino Galvani
Quoted 3 lines · Neil Armstrong
Taking into account the Amlogic Family name starts with GX, including the GXBB, GXL and GXM SoCs.
Quoted 9 lines
Quoted 1 line
Signed-off-by Neil Armstrong <[email protected]>Hi,
looks good to me, but perhaps can you align again register values and other macros in
gx.h?Beniamino
Will do,
Neil
PATCH 2/2 ARM: meson: Add cpu info display for GX SoCs
In reply to Neil ArmstrongThe Amlogic SoCs have a registers containing the die revision and packaging type to determine the SoC family and package marketing name like S905X for the GXL SoC Family.
This code is taken for the Linux meson-gx-socinfo driver and adapted to U-Boot printing.
--- arch/arm/include/asm/arch-meson/gx.h | 1 + arch/arm/mach-meson/Makefile | 2 +- arch/arm/mach-meson/cpu_info.c | 105 +++++++++++++++++++++++++++++++++++ configs/khadas-vim_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/odroid-c2_defconfig | 2 +- configs/odroid_defconfig | 1 + configs/p212_defconfig | 2 +- 8 files changed, 112 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-meson/cpu_info.c
arch/arm/include/asm/arch-meson/gx.h +1 -0
@@ -17,6 +17,7 @@/* Always-On Peripherals registers */ #define GX_AO_ADDR (off) (GX_AOBUS_BASE + ((off) << 2)) +#define GX_AO_SEC_SD_CFG8 GX_AO_ADDR(0x88)#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90)#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93)#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)
arch/arm/mach-meson/Makefile +1 -1
@@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o sm.o eth.o +obj-y += board.o sm.o eth.o cpu_info.o
arch/arm/mach-meson/cpu_info.c new file +105 -0
105 lines not on this page · raw message
configs/khadas-vim_defconfig +1 -1
@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" khadas-vim" CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set
configs/libretech-cc_defconfig +1 -1
@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" libretech-cc" CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set
configs/odroid-c2_defconfig +1 -1
@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" odroid-c2" CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set
configs/odroid_defconfig +1 -0
@@ -56,3 +56,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_LIB_HW_RAND=y CONFIG_ERRNO_STR=y +CONFIG_DISPLAY_CPUINFO=y
configs/p212_defconfig +1 -1
@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" p212" CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-p212" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set
Signature · 1 line
2.7.4
PATCH 2/2 ARM: meson: Add cpu info display for GX SoCs
Quoted 132 lines · Neil Armstrong
The Amlogic SoCs have a registers containing the die revision and packaging type to determine the SoC family and package marketing name like S905X for the GXL SoC Family.
This code is taken for the Linux meson-gx-socinfo driver and adapted to U-Boot printing.Signed-off-by Neil Armstrong <[email protected]>--- arch/arm/include/asm/arch-meson/gx.h | 1 + arch/arm/mach-meson/Makefile | 2 +- arch/arm/mach-meson/cpu_info.c | 105 +++++++++++++++++++++++++++++++++++ configs/khadas-vim_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/odroid-c2_defconfig | 2 +- configs/odroid_defconfig | 1 + configs/p212_defconfig | 2 +- 8 files changed, 112 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-meson/cpu_info.carch/arm/include/asm/arch-meson/gx.h +1
-0@@ -17,6 +17,7 @@/* Always-On Peripherals registers */ #define GX_AO_ADDR (off) (GX_AOBUS_BASE + ((off) << 2)) +#define GX_AO_SEC_SD_CFG8 GX_AO_ADDR(0x88)#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90)#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93)#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)arch/arm/mach-meson/Makefile +1
-1@@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o sm.o eth.o +obj-y += board.o sm.o eth.o cpu_info.oarch/arm/mach-meson/cpu_info.c new file +85
-0@@ -0,0 +1,105 @@ +/* +* Copyright (C) 2018 BayLibre, SAS +* Author: Neil Armstrong <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <asm/arch/gx.h> + +#ifdef CONFIG_DISPLAY_CPUINFO + +#define SOCINFO_MAJOR GENMASK(31, 24) +#define SOCINFO_PACK GENMASK(23, 16) +#define SOCINFO_MINOR GENMASK(15, 8) +#define SOCINFO_MISC GENMASK(7, 0) + +static const struct meson_gx_soc_id { +const char *name; +unsigned int id; +} soc_ids[] = { + {"GXBB" ,0x1f }, + {"GXTVBB" ,0x20 }, + {"GXL" ,0x21 }, + {"GXM" ,0x22 }, + {"TXL" ,0x23 }, +}; + +static const struct meson_gx_package_id { +const char *name; +unsigned int major_id; +unsigned int pack_id; +} soc_packages[] = { + {"S905" ,0x1f ,0 }, + {"S905M" ,0x1f ,0x20 }, + {"S905D" ,0x21 ,0 }, + {"S905X" ,0x21 ,0x80 }, + {"S905L" ,0x21 ,0xc0 }, + {"S905M2" ,0x21 ,0xe0 }, + {"S912" ,0x22 ,0 }, +}; + +static inline unsigned int socinfo_to_major (u32 socinfo) +{ +return FIELD_GET (SOCINFO_MAJOR , socinfo); +} + +static inline unsigned int socinfo_to_minor (u32 socinfo) +{ +return FIELD_GET (SOCINFO_MINOR , socinfo); +} + +static inline unsigned int socinfo_to_pack (u32 socinfo) +{ +return FIELD_GET (SOCINFO_PACK , socinfo); +} + +static inline unsigned int socinfo_to_misc (u32 socinfo) +{ +return FIELD_GET (SOCINFO_MISC , socinfo); +} + +static const char *socinfo_to_package_id (u32 socinfo) +{ +unsigned int pack =socinfo_to_pack (socinfo) &0xf0 ; +unsigned int major =socinfo_to_major (socinfo); +int i; + +for (i =0 ; i <ARRAY_SIZE (soc_packages) ; ++i) { +if (soc_packages[i].major_id == major && + soc_packages[i].pack_id == pack) +return soc_packages[i].name; + } + +return "Unknown" ; +} + +static const char *socinfo_to_soc_id (u32 socinfo) +{ +unsigned int id =socinfo_to_major (socinfo); +int i; + +for (i =0 ; i <ARRAY_SIZE (soc_ids) ; ++i) {
arch/arm/mach-meson/cpu_info.c line 95
Quoted 10 lines
arch/arm/mach-meson/cpu_info.c new file +10
-0+if (soc_ids[i].id == id) +return soc_ids[i].name; + } + +return "Unknown" ; +} + +int print_cpuinfo (void ) +{ +u32 socinfo =readl (GX_AO_SEC_SD_CFG8 );
Perhaps, add a blank line between declarations and code? checkpatch issues a warning about this.
Quoted 54 lines
arch/arm/mach-meson/cpu_info.c new file +10
-0+printf ("CPU: Amlogic Meson %s (%s) rev %x:%x (%x:%x)\n" , +socinfo_to_soc_id (socinfo), +socinfo_to_package_id (socinfo), +socinfo_to_major (socinfo), +socinfo_to_minor (socinfo), +socinfo_to_pack (socinfo), +socinfo_to_misc (socinfo)); + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ configs/khadas-vim_defconfig +1
-1@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" khadas-vim" CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not setconfigs/libretech-cc_defconfig +1
-1@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" libretech-cc" CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not setconfigs/odroid-c2_defconfig +1
-1@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" odroid-c2" CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not setconfigs/odroid_defconfig +0
-0
configs/odroid_defconfig CONFIG_USB_HOST_ETHER=y · line 59
Quoted 4 lines
configs/odroid_defconfig +1
-0@@ -56,3 +56,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_LIB_HW_RAND=y CONFIG_ERRNO_STR=y +CONFIG_DISPLAY_CPUINFO=y
Odroid is not an Amlogic board.
With these 2 issues fixed: Reviewed-by: Beniamino Galvani <[email protected]>
Beniamino
PATCH 2/2 ARM: meson: Add cpu info display for GX SoCs
Quoted 138 lines · Beniamino Galvani
Quoted 137 lines · Neil Armstrong
The Amlogic SoCs have a registers containing the die revision and packaging type to determine the SoC family and package marketing name like S905X for the GXL SoC Family.
This code is taken for the Linux meson-gx-socinfo driver and adapted to U-Boot printing.Signed-off-by Neil Armstrong <[email protected]>--- arch/arm/include/asm/arch-meson/gx.h | 1 + arch/arm/mach-meson/Makefile | 2 +- arch/arm/mach-meson/cpu_info.c | 105 +++++++++++++++++++++++++++++++++++ configs/khadas-vim_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/odroid-c2_defconfig | 2 +- configs/odroid_defconfig | 1 + configs/p212_defconfig | 2 +- 8 files changed, 112 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-meson/cpu_info.carch/arm/include/asm/arch-meson/gx.h +1
-0@@ -17,6 +17,7 @@/* Always-On Peripherals registers */ #define GX_AO_ADDR (off) (GX_AOBUS_BASE + ((off) << 2)) +#define GX_AO_SEC_SD_CFG8 GX_AO_ADDR(0x88)#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90)#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93)#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)arch/arm/mach-meson/Makefile +1
-1@@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o sm.o eth.o +obj-y += board.o sm.o eth.o cpu_info.oarch/arm/mach-meson/cpu_info.c new file +90
-0@@ -0,0 +1,105 @@ +/* +* Copyright (C) 2018 BayLibre, SAS +* Author: Neil Armstrong <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <asm/arch/gx.h> + +#ifdef CONFIG_DISPLAY_CPUINFO + +#define SOCINFO_MAJOR GENMASK(31, 24) +#define SOCINFO_PACK GENMASK(23, 16) +#define SOCINFO_MINOR GENMASK(15, 8) +#define SOCINFO_MISC GENMASK(7, 0) + +static const struct meson_gx_soc_id { +const char *name; +unsigned int id; +} soc_ids[] = { + {"GXBB" ,0x1f }, + {"GXTVBB" ,0x20 }, + {"GXL" ,0x21 }, + {"GXM" ,0x22 }, + {"TXL" ,0x23 }, +}; + +static const struct meson_gx_package_id { +const char *name; +unsigned int major_id; +unsigned int pack_id; +} soc_packages[] = { + {"S905" ,0x1f ,0 }, + {"S905M" ,0x1f ,0x20 }, + {"S905D" ,0x21 ,0 }, + {"S905X" ,0x21 ,0x80 }, + {"S905L" ,0x21 ,0xc0 }, + {"S905M2" ,0x21 ,0xe0 }, + {"S912" ,0x22 ,0 }, +}; + +static inline unsigned int socinfo_to_major (u32 socinfo) +{ +return FIELD_GET (SOCINFO_MAJOR , socinfo); +} + +static inline unsigned int socinfo_to_minor (u32 socinfo) +{ +return FIELD_GET (SOCINFO_MINOR , socinfo); +} + +static inline unsigned int socinfo_to_pack (u32 socinfo) +{ +return FIELD_GET (SOCINFO_PACK , socinfo); +} + +static inline unsigned int socinfo_to_misc (u32 socinfo) +{ +return FIELD_GET (SOCINFO_MISC , socinfo); +} + +static const char *socinfo_to_package_id (u32 socinfo) +{ +unsigned int pack =socinfo_to_pack (socinfo) &0xf0 ; +unsigned int major =socinfo_to_major (socinfo); +int i; + +for (i =0 ; i <ARRAY_SIZE (soc_packages) ; ++i) { +if (soc_packages[i].major_id == major && + soc_packages[i].pack_id == pack) +return soc_packages[i].name; + } + +return "Unknown" ; +} + +static const char *socinfo_to_soc_id (u32 socinfo) +{ +unsigned int id =socinfo_to_major (socinfo); +int i; + +for (i =0 ; i <ARRAY_SIZE (soc_ids) ; ++i) { +if (soc_ids[i].id == id) +return soc_ids[i].name; + } + +return "Unknown" ;
Quoted 8 lines
arch/arm/mach-meson/cpu_info.c line 95
Quoted 5 lines
arch/arm/mach-meson/cpu_info.c new file +5
-0+} + +int print_cpuinfo (void ) +{ +u32 socinfo =readl (GX_AO_SEC_SD_CFG8 );Perhaps, add a blank line between declarations and code? checkpatch issues a warning about this.
Ok
Quoted 53 lines
Quoted 53 lines
arch/arm/mach-meson/cpu_info.c new file +10
-0+printf ("CPU: Amlogic Meson %s (%s) rev %x:%x (%x:%x)\n" , +socinfo_to_soc_id (socinfo), +socinfo_to_package_id (socinfo), +socinfo_to_major (socinfo), +socinfo_to_minor (socinfo), +socinfo_to_pack (socinfo), +socinfo_to_misc (socinfo)); + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ configs/khadas-vim_defconfig +1
-1@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" khadas-vim" CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not setconfigs/libretech-cc_defconfig +1
-1@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" libretech-cc" CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not setconfigs/odroid-c2_defconfig +1
-1@@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" odroid-c2" CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y -# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not setconfigs/odroid_defconfig +0
-1--- a/configs/odroid_defconfig
Quoted 8 lines
configs/odroid_defconfig CONFIG_USB_HOST_ETHER=y · line 59
Quoted 6 lines
+++ b/configs/odroid_defconfig
configs/odroid_defconfig +1
-0@@ -56,3 +56,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_LIB_HW_RAND=y CONFIG_ERRNO_STR=y +CONFIG_DISPLAY_CPUINFO=yOdroid is not an Amlogic board.
Oops, will remove it.
Quoted 5 lines
With these 2 issues fixed: Reviewed-by: Beniamino Galvani <[email protected]>
Beniamino
PATCH 2/2 ARM: meson: Add cpu info display for GX SoCs
In reply to Neil ArmstrongHi,
Quoted 7 lines · Neil Armstrong
The Amlogic SoCs have a registers containing the die revision and packaging type to determine the SoC family and package marketing name like S905X for the GXL SoC Family.
This code is taken for the Linux meson-gx-socinfo driver and adapted to U-Boot printing.Signed-off-by Neil Armstrong <[email protected]>
Quoted 11 lines
--- arch/arm/include/asm/arch-meson/gx.h | 1 + arch/arm/mach-meson/Makefile | 2 +- arch/arm/mach-meson/cpu_info.c | 105 +++++++++++++++++++++++++++++++++++ configs/khadas-vim_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/odroid-c2_defconfig | 2 +- configs/odroid_defconfig | 1 + configs/p212_defconfig | 2 +- 8 files changed, 112 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-meson/cpu_info.c
Please can you use driver model's CPU interface for this?
Regards,
Simon
PATCH 2/2 ARM: meson: Add cpu info display for GX SoCs
Quoted 22 lines · Simon Glass
Hi,
Quoted 7 lines · Neil Armstrong
The Amlogic SoCs have a registers containing the die revision and packaging type to determine the SoC family and package marketing name like S905X for the GXL SoC Family.
This code is taken for the Linux meson-gx-socinfo driver and adapted to U-Boot printing.Signed-off-by Neil Armstrong <[email protected]>Quoted 11 lines
--- arch/arm/include/asm/arch-meson/gx.h | 1 + arch/arm/mach-meson/Makefile | 2 +- arch/arm/mach-meson/cpu_info.c | 105 +++++++++++++++++++++++++++++++++++ configs/khadas-vim_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/odroid-c2_defconfig | 2 +- configs/odroid_defconfig | 1 + configs/p212_defconfig | 2 +- 8 files changed, 112 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-meson/cpu_info.c
Quoted 5 lines
Please can you use driver model's CPU interface for this?
Regards,
Simon
You are right, I totally missed this one.
Neil
PATCH 2/2 ARM: meson: Add cpu info display for GX SoCs
In reply to Simon GlassQuoted 22 lines · Simon Glass
Hi,
Quoted 7 lines · Neil Armstrong
The Amlogic SoCs have a registers containing the die revision and packaging type to determine the SoC family and package marketing name like S905X for the GXL SoC Family.
This code is taken for the Linux meson-gx-socinfo driver and adapted to U-Boot printing.Signed-off-by Neil Armstrong <[email protected]>Quoted 11 lines
--- arch/arm/include/asm/arch-meson/gx.h | 1 + arch/arm/mach-meson/Makefile | 2 +- arch/arm/mach-meson/cpu_info.c | 105 +++++++++++++++++++++++++++++++++++ configs/khadas-vim_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/odroid-c2_defconfig | 2 +- configs/odroid_defconfig | 1 + configs/p212_defconfig | 2 +- 8 files changed, 112 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-meson/cpu_info.c
Quoted 5 lines
Please can you use driver model's CPU interface for this?
Regards,
Simon
Hi Simon,
The CPU uclass is designed for the /cpu/* nodes, here we fetch the SoC information in some /soc/ subnodes which cannot be used with the current CPU uclass and won't be probed before relocation.
Either I push is as a MISC driver (with the pre-reloc issue) or we leave this in mach-meson.
What do you think ?
Thanks,
Neil
PATCH 2/2 ARM: meson: Add cpu info display for GX SoCs
Hi Neil,
Quoted 31 lines · Neil Armstrong
Quoted 22 lines · Simon Glass
Hi,
Quoted 7 lines · Neil Armstrong
The Amlogic SoCs have a registers containing the die revision and packaging type to determine the SoC family and package marketing name like S905X for the GXL SoC Family.
This code is taken for the Linux meson-gx-socinfo driver and adapted to U-Boot printing.Signed-off-by Neil Armstrong <[email protected]>Quoted 11 lines
--- arch/arm/include/asm/arch-meson/gx.h | 1 + arch/arm/mach-meson/Makefile | 2 +- arch/arm/mach-meson/cpu_info.c | 105 +++++++++++++++++++++++++++++++++++ configs/khadas-vim_defconfig | 2 +- configs/libretech-cc_defconfig | 2 +- configs/odroid-c2_defconfig | 2 +- configs/odroid_defconfig | 1 + configs/p212_defconfig | 2 +- 8 files changed, 112 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-meson/cpu_info.cQuoted 5 lines
Please can you use driver model's CPU interface for this?
Regards,
SimonHi Simon,
Quoted 7 lines
The CPU uclass is designed for the /cpu/* nodes, here we fetch the SoC information in some /soc/ subnodes which cannot be used with the current CPU uclass and won't be probed before relocation.
Either I push is as a MISC driver (with the pre-reloc issue) or we leave this in mach-meson.
What do you think ?
Do you think it could search both /cpu and /soc ? They seem to be fairly equivalent. Is that the only problem?
Quoted 3 lines
Thanks,
Neil
Regards,
Simon