rockchip: clean up board file for rockchip SoCs

The configure_l2ctlr() is used only by rk3288, do not need to locate in sys_proto.h

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/include/asm/arch-rockchip/sys_proto.h | 22 ----------------------
 arch/arm/mach-rockchip/rk3288/rk3288.c         | 26 +++++++++++++++++++++++++-
 2 files changed, 25 insertions(+), 23 deletions(-)

The configure_l2ctlr() is used only by rk3288, do not need to locate in sys_proto.h

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---

arch/arm/include/asm/arch-rockchip/sys_proto.h | 22 ----------------------
arch/arm/mach-rockchip/rk3288/rk3288.c | 26 +++++++++++++++++++++++++-

2 files changed, 25 insertions(+), 23 deletions(-)

arch/arm/include/asm/arch-rockchip/sys_proto.h +0 -22

index e428d59..3617ac2 100644
@@ -7,27 +7,5 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
-#ifdef CONFIG_ROCKCHIP_RK3288
-#include <asm/armv7.h>
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-#endif /* CONFIG_ROCKCHIP_RK3288 */
 
 #endif /* _ASM_ARCH_SYS_PROTO_H */

arch/arm/mach-rockchip/rk3288/rk3288.c +0 -0

index acc3b79..1e1c6be 100644

Quoted 2 lines · Kever Yang

The configure_l2ctlr() is used only by rk3288, do not need to locate in sys_proto.h

Please elaborate on what the function does and why it is not needed by any of the other SOCs (after all: it has been available to all SOCs so far).

Quoted 3 lines

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

This should be a standalone patch and doesn't need to be part of the series it is in.  This series has way too many different things happening at once and needs to be broken up into individual series that do one well-defined thing each.

See below for requested changes.

Quoted 54 lines

---

arch/arm/include/asm/arch-rockchip/sys_proto.h | 22
----------------------
arch/arm/mach-rockchip/rk3288/rk3288.c         | 26
+++++++++++++++++++++++++-

2 files changed, 25 insertions(+), 23 deletions(-)

arch/arm/include/asm/arch-rockchip/sys_proto.h +0 -22

index e428d59..3617ac2 100644
@@ -7,27 +7,5 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
-#ifdef CONFIG_ROCKCHIP_RK3288
-#include <asm/armv7.h>
-
-static void configure_l2ctlr(void)
-{
-    uint32_t l2ctlr;
-
-    l2ctlr = read_l2ctlr();
-    l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-    /*
-    * Data RAM write latency: 2 cycles
-    * Data RAM read latency: 2 cycles
-    * Data RAM setup latency: 1 cycle
-    * Tag RAM write latency: 1 cycle
-    * Tag RAM read latency: 1 cycle
-    * Tag RAM setup latency: 1 cycle
-    */
-    l2ctlr |= (1 << 3 | 1 << 0);
-    write_l2ctlr(l2ctlr);
-}
-#endif /* CONFIG_ROCKCHIP_RK3288 */
 
 #endif /* _ASM_ARCH_SYS_PROTO_H */

arch/arm/mach-rockchip/rk3288/rk3288.c +1 -0

index acc3b79..1e1c6be 100644
@@ -3,15 +3,39 @@
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
+#include <asm/armv7.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 

arch/arm/mach-rockchip/rk3288/rk3288.c line 10

Quoted 1 line

arch/arm/mach-rockchip/rk3288/rk3288.c +0 -0

 #define GRF_SOC_CON2 0xff77024c

Please make this a const-declaration in the function it is needed in.

arch/arm/mach-rockchip/rk3288/rk3288.c line 11

Quoted 3 lines

arch/arm/mach-rockchip/rk3288/rk3288.c +1 -0

+#ifdef CONFIG_SPL_BUILD

Should this really happen both for TPL and SPL?

arch/arm/mach-rockchip/rk3288/rk3288.c line 18

Quoted 7 lines

arch/arm/mach-rockchip/rk3288/rk3288.c +6 -0

+static void configure_l2ctlr(void)
+{
+    u32 l2ctlr;
+
+    l2ctlr = read_l2ctlr();
+    l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */

What are bits 0...17?

arch/arm/mach-rockchip/rk3288/rk3288.c line 27

Quoted 9 lines

arch/arm/mach-rockchip/rk3288/rk3288.c +9 -0

+
+    /*
+     * Data RAM write latency: 2 cycles
+     * Data RAM read latency: 2 cycles
+     * Data RAM setup latency: 1 cycle
+     * Tag RAM write latency: 1 cycle
+     * Tag RAM read latency: 1 cycle
+     * Tag RAM setup latency: 1 cycle
+     */

Please add a symbolic way to assemble these (i.e. something that makes it easy for the casual reader to see what values you are writing to which bitfields).

arch/arm/mach-rockchip/rk3288/rk3288.c line 28

Quoted 1 line

arch/arm/mach-rockchip/rk3288/rk3288.c +1 -0

+    l2ctlr |= (1 << 3 | 1 << 0);

From the "clear bit0 ~ bit17" and this, I assume you actually want to do a clrsetbits_le32...

Quoted 4 lines

arch/arm/mach-rockchip/rk3288/rk3288.c +3 -0

+    write_l2ctlr(l2ctlr);
+}
+#endif

arch/arm/mach-rockchip/rk3288/rk3288.c line 40

Quoted 10 lines

arch/arm/mach-rockchip/rk3288/rk3288.c +4 -1

+
 int arch_cpu_init(void)
 {
     /* We do some SoC one time setting here. */
-
+#ifdef CONFIG_SPL_BUILD
+    configure_l2ctlr();
+#else
     /* Use rkpwm by default */
     rk_setreg(GRF_SOC_CON2, 1 << 0);

Please use a symbolic way to write the (1 << 0), wo it is easy for the casual reader to see what gets enabled/disabled here.

Quoted 3 lines

All rockchip SoCs can use ARM arch timer, let's enable it in common header file

Signed-off-by Kever Yang <[email protected]>

---

 include/configs/rk3368_common.h   | 2 --
 include/configs/rk3399_common.h   | 2 --
 include/configs/rockchip-common.h | 4 ++++
 3 files changed, 4 insertions(+), 4 deletions(-)

All rockchip SoCs can use ARM arch timer, let's enable it in common header file

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---

include/configs/rk3368_common.h   | 2 --
include/configs/rk3399_common.h   | 2 --
include/configs/rockchip-common.h | 4 ++++
3 files changed, 4 insertions(+), 4 deletions(-)

include/configs/rk3368_common.h +0 -2

index 10f643f..a7fe4ca 100644
@@ -22,8 +22,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define COUNTER_FREQUENCY               24000000
-
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000

include/configs/rk3399_common.h +0 -2

index d700bf2..fe8c675 100644
@@ -17,8 +17,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #endif
 
-#define COUNTER_FREQUENCY               24000000
-
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000

include/configs/rockchip-common.h +0 -0

index 26d41b5..24651ce 100644

include/configs/rockchip-common.h +1 -0

+
 #ifndef CONFIG_SPL_BUILD
 
 /* First try to boot from SD (index 0), then eMMC (index 1) */

Quoted 2 lines · Kever Yang

All rockchip SoCs can use ARM arch timer, let's enable it in common header file

Please provide a commit message that is more descriptive of what actually happens... i.e. that COUNTER_FREQUENCY gets moved to a common header.

It would be great to document why this will always remain 24M.

Quoted 3 lines

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

See below for requested changes.

Quoted 44 lines

---

include/configs/rk3368_common.h   | 2 --
include/configs/rk3399_common.h   | 2 --
include/configs/rockchip-common.h | 4 ++++

3 files changed, 4 insertions(+), 4 deletions(-)

include/configs/rk3368_common.h +0 -2

index 10f643f..a7fe4ca 100644
@@ -22,8 +22,6 @@
 #define CONFIG_SYS_CBSIZE        1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define COUNTER_FREQUENCY               24000000
-
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_INIT_SP_ADDR        0x00300000

include/configs/rk3399_common.h +0 -2

index d700bf2..fe8c675 100644
@@ -17,8 +17,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #endif
 
-#define COUNTER_FREQUENCY               24000000
-
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_INIT_SP_ADDR        0x00300000

include/configs/rockchip-common.h +0 -0

index 26d41b5..24651ce 100644
@@ -8,6 +8,10 @@
 #define _ROCKCHIP_COMMON_H_
 #include <linux/sizes.h>
 

include/configs/rockchip-common.h line 11

Quoted 1 line

include/configs/rockchip-common.h +1 -0

+#define COUNTER_FREQUENCY               24000000

Is this really safe for all past, current and future SOCs (after all:
you are putting this into 'rockchip-common.h'?

include/configs/rockchip-common.h line 12

Quoted 2 lines

include/configs/rockchip-common.h +1 -0

+#define CONFIG_SYS_ARCH_TIMER

I don't agree with putting this here, as the CONFIG_SYS_ARCH_TIMER definition is only used on ARMv7, but this file is also included by ARMv8 SOCs.

include/configs/rockchip-common.h line 13

Quoted 2 lines

include/configs/rockchip-common.h +1 -0

+#define CONFIG_SYS_HZ_CLOCK    24000000

You might want to have this refer back to COUNTER_FREQUENCY.

Quoted 5 lines

include/configs/rockchip-common.h +1 -0

+
 #ifndef CONFIG_SPL_BUILD
 
 /* First try to boot from SD (index 0), then eMMC (index 1) */

All rockchip SoCs can use ns16550 driver, enable it for all and set SYS_NS16550_MEM32 for all SoCs.

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/Kconfig                  | 1 +
 arch/arm/mach-rockchip/Kconfig    | 1 -
 include/configs/rk3036_common.h   | 3 ---
 include/configs/rk3128_common.h   | 2 --
 include/configs/rk3188_common.h   | 2 --
 include/configs/rk322x_common.h   | 1 -
 include/configs/rk3288_common.h   | 2 --
 include/configs/rk3328_common.h   | 2 --
 include/configs/rk3368_common.h   | 2 --
 include/configs/rk3399_common.h   | 2 --
 include/configs/rockchip-common.h | 2 ++
 include/configs/rv1108_common.h   | 3 ---
 12 files changed, 3 insertions(+), 20 deletions(-)

All rockchip SoCs can use ns16550 driver, enable it for all and set SYS_NS16550_MEM32 for all SoCs.

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

arch/arm/Kconfig                  | 1 +
arch/arm/mach-rockchip/Kconfig    | 1 -
include/configs/rk3036_common.h   | 3 ---
include/configs/rk3128_common.h   | 2 --
include/configs/rk3188_common.h   | 2 --
include/configs/rk322x_common.h   | 1 -
include/configs/rk3288_common.h   | 2 --
include/configs/rk3328_common.h   | 2 --
include/configs/rk3368_common.h   | 2 --
include/configs/rk3399_common.h   | 2 --
include/configs/rockchip-common.h | 2 ++
include/configs/rv1108_common.h   | 3 ---
12 files changed, 3 insertions(+), 20 deletions(-)

arch/arm/Kconfig +0 -0

index 2c52ff0..3e9a80d 100644

arch/arm/Kconfig +0 -0

 	imply CMD_FASTBOOT
 	imply FASTBOOT
 	imply FAT_WRITE

arch/arm/mach-rockchip/Kconfig +0 -1

index 0adaed4..007cb22 100644
@@ -103,7 +103,6 @@ config ROCKCHIP_RK3368
 	imply SPL_SERIAL_SUPPORT
 	imply TPL_SERIAL_SUPPORT
 	select DEBUG_UART_BOARD_INIT
-	select SYS_NS16550
 	help
 	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
 	  into a big and little cluster with 4 cores each) Cortex-A53 including

include/configs/rk3036_common.h +0 -3

index f39a272..c5ec864 100644
@@ -18,9 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 #define CONFIG_SPL_STACK		0x10081fff

include/configs/rk3128_common.h +0 -2

index bd8019c..c593f18 100644
@@ -19,8 +19,6 @@
 #define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 

include/configs/rk3188_common.h +0 -2

index 94f8cda..30c150e 100644
@@ -22,8 +22,6 @@
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
 #endif

include/configs/rk322x_common.h +0 -1

index 7f9c7fb..832f037 100644
@@ -18,7 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE		0x110c00a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800
 #define CONFIG_SPL_STACK		0x10088000

include/configs/rk3288_common.h +0 -2

index 78595b8..44d5c2a 100644
@@ -19,8 +19,6 @@
 #define	CONFIG_SYS_TIMER_BASE		0xff810020 /* TIMER7 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
 #endif

include/configs/rk3328_common.h +0 -2

index 7018668..ce650c8 100644
@@ -13,8 +13,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 

include/configs/rk3368_common.h +0 -2

index a7fe4ca..866383d 100644
@@ -22,8 +22,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00280000
 

include/configs/rk3399_common.h +0 -2

index fe8c675..53691e5 100644
@@ -17,8 +17,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #endif
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 #define CONFIG_SPL_STACK		0xff8effff

include/configs/rockchip-common.h +2 -0

index 24651ce..4062480 100644
@@ -12,6 +12,8 @@
 #define CONFIG_SYS_ARCH_TIMER
 #define CONFIG_SYS_HZ_CLOCK	24000000
 
+#define CONFIG_SYS_NS16550_MEM32
+
 #ifndef CONFIG_SPL_BUILD
 
 /* First try to boot from SD (index 0), then eMMC (index 1) */

include/configs/rv1108_common.h +0 -3

index 349c53c..cd204e9 100644
@@ -18,9 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE		0x10350020
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x100000)

We have enable NS16550 in Kconfig, do not need enable at defconfig

Signed-off-by Kever Yang <[email protected]>

---

 configs/evb-rk3128_defconfig      | 1 -
 configs/evb-rk3229_defconfig      | 1 -
 configs/evb-rk3288_defconfig      | 1 -
 configs/evb-rk3328_defconfig      | 1 -
 configs/evb-rk3399_defconfig      | 1 -
 configs/fennec-rk3288_defconfig   | 1 -
 configs/firefly-rk3288_defconfig  | 1 -
 configs/firefly-rk3399_defconfig  | 1 -
 configs/miqi-rk3288_defconfig     | 1 -
 configs/phycore-rk3288_defconfig  | 1 -
 configs/popmetal-rk3288_defconfig | 1 -
 configs/puma-rk3399_defconfig     | 1 -
 configs/tinker-rk3288_defconfig   | 1 -
 configs/vyasa-rk3288_defconfig    | 1 -
 14 files changed, 14 deletions(-)

We have enable NS16550 in Kconfig, do not need enable at defconfig

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

STIMER is can only access in secure mode if the SoCs supports trust, and it locate in alive power domain, as the source of ARM arch/generic timer, we add a base addr for all SoCs so that we can init with a common function.

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

STIMER is can only access in secure mode if the SoCs supports trust, and it locate in alive power domain, as the source of ARM arch/generic timer, we add a base addr for all SoCs so that we can init with a common function.

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---

arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++

1 file changed, 19 insertions(+)

arch/arm/mach-rockchip/Kconfig +0 -0

index 007cb22..5dfe452 100644

arch/arm/mach-rockchip/Kconfig +5 -0

+	default 0x200440a0 if ROCKCHIP_RK3036
+	default 0x2000e000 if ROCKCHIP_RK3066
+	default 0x20018020 if ROCKCHIP_RK3126
+	default 0x200440a0 if ROCKCHIP_RK3128
+	default 0x2000e000 if ROCKCHIP_RK3188

arch/arm/mach-rockchip/Kconfig +1 -0

+

config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0

Quoted 4 lines · Kever Yang

STIMER is can only access in secure mode if the SoCs supports trust, and it locate in alive power domain, as the source of ARM arch/generic timer, we add a base addr for all SoCs so that we can init with a common function.

The commit message does not really tell what the source changes are

(although it seems to describe part of the motivation for this change).

Quoted 3 lines

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

See below for requested changes.

Quoted 15 lines

---

arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++

1 file changed, 19 insertions(+)

arch/arm/mach-rockchip/Kconfig +0 -0

index 007cb22..5dfe452 100644
@@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG

      The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
      according to the value from this register.

Quoted 3 lines

+config ROCKCHIP_STIMER_BASE
+    hex "Rockchip Secure timer base address"
+    default 0xff220020 if ROCKCHIP_PX30

We don't have support for the PX30 in the U-Boot code base yet. Until a series to add support for the PX30 comes in, you should not have this here yet (and then add this specific case when the PX30 support is added).

Quoted 8 lines

+    default 0x200440a0 if ROCKCHIP_RK3036
+    default 0x2000e000 if ROCKCHIP_RK3066
+    default 0x20018020 if ROCKCHIP_RK3126
+    default 0x200440a0 if ROCKCHIP_RK3128
+    default 0x2000e000 if ROCKCHIP_RK3188
+    default 0x110d0020 if ROCKCHIP_RK322X
+    default 0xff810020 if ROCKCHIP_RK3288
+    default 0xff1d0020 if ROCKCHIP_RK3328

Quoted 8 lines

+    default 0xff830020 if ROCKCHIP_RK3368
+    default 0xff8680a0 if ROCKCHIP_RK3399
+    default 0x10350020 if ROCKCHIP_RV1108
+    default 0
+    help
+      The secure timer inited in SPL/TPL in secure word, ARM generic timer
+      works after this timer work.

This should not be in Kconfig and rather in a header-file.

With what you do here, a user (e.g. via 'make menuconfig') or a defconfig file (e.g. due to a typo) could accidentially change overwrite this.

Quoted 6 lines

+
config ROCKCHIP_SPL_RESERVE_IRAM
    hex "Size of IRAM reserved in SPL"
    default 0

This should not be in Kconfig and rather in a header-file. With what you do here, a user (e.g. via 'make menuconfig') or a defconfig file (e.g. due to a typo) could accidentially change overwrite this.

asm/arch-rockchip would be preferable over include/config as a header

STIMER is can only access in secure mode if the SoCs supports trust, and it locate in alive power domain, as the source of ARM arch/generic timer, we add a base addr for all SoCs so that we can init with a common function.

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/mach-rockchip/Kconfig | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

arch/arm/mach-rockchip/Kconfig +17 -0

index 007cb22..5dfe452 100644
@@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG
          The Soc will enter to different boot mode(defined in
 asm/arch/boot_mode.h)
          according to the value from this register.
 
+config ROCKCHIP_STIMER_BASE
+       hex "Rockchip Secure timer base address"
+       default 0xff220020 if ROCKCHIP_PX30
+       default 0x200440a0 if ROCKCHIP_RK3036
+       default 0x2000e000 if ROCKCHIP_RK3066
+       default 0x20018020 if ROCKCHIP_RK3126
+       default 0x200440a0 if ROCKCHIP_RK3128
+       default 0x2000e000 if ROCKCHIP_RK3188
+       default 0x110d0020 if ROCKCHIP_RK322X
+       default 0xff810020 if ROCKCHIP_RK3288
+       default 0xff1d0020 if ROCKCHIP_RK3328
+       default 0xff830020 if ROCKCHIP_RK3368
+       default 0xff8680a0 if ROCKCHIP_RK3399
+       default 0x10350020 if ROCKCHIP_RV1108
+       default 0
+       help
+         The secure timer inited in SPL/TPL in secure word, ARM generic

timer

arch/arm/mach-rockchip/Kconfig +2 -1

+         works after this timer work.
+
 config ROCKCHIP_SPL_RESERVE_IRAM
        hex "Size of IRAM reserved in SPL"
        default 0
--

1.9.1

This should not be in Kconfig and rather in a header-file. With what you do here, a user (e.g. via 'make menuconfig') or a defconfig file (e.g. due to a typo) could accidentially change overwrite this.

Here are the solutions from previous discussion:
- dts (by Simon)
    extra dtb code needed, setting separate into individual board dts; not available and not suggestion to use in TPL/SPL;
- move to header in 'asm/arch-rockchip' (by Philipp)
    one more place to config, make config options more complicate; may separate in more than 10+ files for different soc/board;
- RMII setting like, (by Philipp)
    reference to 'drivers/net/gmac_rockchip.c', driver for different SoCs are not re-usable, driver needs to update for each new SoC support; not available with DM in early TPL/SPL;
- Kconfig with default value in this patch
    Keep driver clean and no need to update with new SoC; One place rather than 10+ individual files, same usage like SYS_TEXT_BASE, reference to:
      341c058654 sunxi: move CONFIG_SYS_TEXT_BASE out of defconfigs

We add this for get the location for boot device of bootrom.

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/mach-rockchip/Kconfig | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

We add this for get the location for boot device of bootrom.

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---

arch/arm/mach-rockchip/Kconfig | 17 +++++++++++++++++

1 file changed, 17 insertions(+)

arch/arm/mach-rockchip/Kconfig +0 -0

index 5dfe452..98bf935 100644

arch/arm/mach-rockchip/Kconfig +1 -0

+

config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0

Quoted 1 line · Kever Yang

We add this for get the location for boot device of bootrom.

Your commit message should be specific enough, so the motivation for the change, where it fits into the overall architecture and what is changed are apparent.

Quoted 2 lines

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

See below for requested changes.

Quoted 15 lines

---

arch/arm/mach-rockchip/Kconfig | 17 +++++++++++++++++

1 file changed, 17 insertions(+)

arch/arm/mach-rockchip/Kconfig +0 -0

index 5dfe452..98bf935 100644
@@ -209,6 +209,23 @@ config ROCKCHIP_STIMER_BASE

      The secure timer inited in SPL/TPL in secure word, ARM generic timer
      works after this timer work.

Quoted 2 lines

+config ROCKCHIP_IRAM_START_ADDR
+    hex "Rockchip Secure timer base address"

Huh: copy-and-paste?

Quoted 2 lines

+    default 0xff0e0000 if ROCKCHIP_PX30

See my earlier comment regarding changes specific to the PX30.

Quoted 5 lines

+    default 0x10080000 if ROCKCHIP_RK3036
+    default 0x10080000 if ROCKCHIP_RK3128
+    default 0x10080000 if ROCKCHIP_RK3188
+    default 0x10080000 if ROCKCHIP_RK322X
+    default 0xff700000 if ROCKCHIP_RK3288

Quoted 8 lines

+    default 0xff091000 if ROCKCHIP_RK3328
+    default 0xff8c0000 if ROCKCHIP_RK3368
+    default 0xff8c0000 if ROCKCHIP_RK3399
+    default 0x10080000 if ROCKCHIP_RV1108
+    default 0
+    help
+      The IRAM start addr is to locate variant of the boot device from +      bootrom.

The same comment as for the secure timer-base applies here. This is way to important to have it in Kconfig, where a user can easily override.

Quoted 5 lines

+
config ROCKCHIP_SPL_RESERVE_IRAM
    hex "Size of IRAM reserved in SPL"
    default 0

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/mach-rockchip/Kconfig | 1 +
 1 file changed, 1 insertion(+)

Signed-off-by Kever Yang <[email protected]>

---

arch/arm/mach-rockchip/Kconfig | 1 +

1 file changed, 1 insertion(+)

arch/arm/mach-rockchip/Kconfig +1 -0

index 98bf935..892d51e 100644
@@ -182,6 +182,7 @@ config ROCKCHIP_BOOT_MODE_REG
 	default 0x20004040 if ROCKCHIP_RK3188
 	default 0x110005c8 if ROCKCHIP_RK322X
 	default 0xff730094 if ROCKCHIP_RK3288
+	default 0xff1005c8 if ROCKCHIP_RK3328
 	default 0xff738200 if ROCKCHIP_RK3368
 	default 0xff320300 if ROCKCHIP_RK3399
 	default 0x10300580 if ROCKCHIP_RV1108

We can use arch timer instead of rockchip timer.

Signed-off-by Kever Yang <[email protected]>

---

 include/configs/rk322x_common.h | 3 ---
 1 file changed, 3 deletions(-)

We can use arch timer instead of rockchip timer.

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---

include/configs/rk322x_common.h | 3 ---

1 file changed, 3 deletions(-)

include/configs/rk322x_common.h +0 -3

index 832f037..29e222a 100644
@@ -14,9 +14,6 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/*  64M */
 
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE		0x110c00a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
 #define CONFIG_SYS_LOAD_ADDR		0x60800800

Do not need to use rockchip_udelay after we can use systimer.

Signed-off-by Kever Yang <[email protected]>

---

 drivers/ram/rockchip/sdram_rk322x.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

Do not need to use rockchip_udelay after we can use systimer.

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---

 drivers/ram/rockchip/sdram_rk322x.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

Move soc spec setting into rk322x.c and remove rk322x-board/board-spl.c

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/mach-rockchip/rk322x-board.c              | 155 ---------------------
 arch/arm/mach-rockchip/rk322x/Makefile             |   2 +-
 .../{rk322x-board-spl.c => rk322x/rk322x.c}        |  86 ++++--------
 3 files changed, 29 insertions(+), 214 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c
 rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%)

Move soc spec setting into rk322x.c and remove rk322x-board/board-spl.c

Signed-off-by Kever Yang <[email protected]>

---

arch/arm/mach-rockchip/rk322x-board.c              | 155 ---------------------
arch/arm/mach-rockchip/rk322x/Makefile             |   2 +-
.../{rk322x-board-spl.c => rk322x/rk322x.c}        |  86 ++++--------
3 files changed, 29 insertions(+), 214 deletions(-)

delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c
rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%)

arch/arm/mach-rockchip/rk322x-board.c deleted +0 -155

deleted file mode 100644
index 8642a90..0000000
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/grf_rk322x.h>
-#include <asm/arch/boot_mode.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-
-	return rk_board_late_init();
-}
-
-int board_init(void)
-{
-#include <asm/arch/grf_rk322x.h>
-	/* Enable early UART2 channel 1 on the RK322x */
-#define GRF_BASE	0x11000000
-	struct rk322x_grf * const grf = (void *)GRF_BASE;
-	enum {
-		GPIO1B2_SHIFT		= 4,
-		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
-		GPIO1B2_GPIO		= 0,
-		GPIO1B2_UART21_SIN,
-
-		GPIO1B1_SHIFT		= 2,
-		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
-		GPIO1B1_GPIO            = 0,
-		GPIO1B1_UART1_SOUT,
-		GPIO1B1_UART21_SOUT,
-	};
-	enum {
-		CON_IOMUX_UART2SEL_SHIFT= 8,
-		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
-		CON_IOMUX_UART2SEL_2	= 0,
-		CON_IOMUX_UART2SEL_21,
-	};
-
-	rk_clrsetreg(&grf->gpio1b_iomux,
-		     GPIO1B1_MASK | GPIO1B2_MASK,
-		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
-		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
-	/* Set channel C as UART2 input */
-	rk_clrsetreg(&grf->con_iomux,
-		     CON_IOMUX_UART2SEL_MASK,
-		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
-
-	/*
-	* The integrated macphy is enabled by default, disable it
-	* for saving power consuming.
-	*/
-	rk_clrsetreg(&grf->macphy_con[0],
-		     MACPHY_CFG_ENABLE_MASK,
-		     0 << MACPHY_CFG_ENABLE_SHIFT);
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = 0x8400000;
-	/* Reserve 0x200000 for OPTEE */
-	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-				+ gd->bd->bi_dram[0].size + 0x200000;
-	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-				+ gd->ram_size - gd->bd->bi_dram[1].start;
-
-	return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk322x_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk322x_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
-int fb_set_reboot_flag(void)
-{
-	struct rk322x_grf *grf;
-
-	printf("Setting reboot to fastboot flag ...\n");
-	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	/* Set boot mode to fastboot */
-	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
-
-	return 0;
-}
-#endif

arch/arm/mach-rockchip/rk322x/Makefile +0 -1

index ecb3e8d..89b0fed 100644
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-

obj-y += clk_rk322x.o
+obj-y += rk322x.o
obj-y += syscon_rk322x.o

arch/arm/mach-rockchip/rk322x/rk322x.c renamed from arch/arm/mach-rockchip/rk322x-board-spl.c +1 -8

similarity index 51%
rename from arch/arm/mach-rockchip/rk322x-board-spl.c
rename to arch/arm/mach-rockchip/rk322x/rk322x.c
index 206abfa..98b6ec3 100644
@@ -1,32 +1,41 @@
 /*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/bootrom.h>
-#include <asm/arch/cru_rk322x.h>

arch/arm/mach-rockchip/rk322x/rk322x.c renamed from arch/arm/mach-rockchip/rk322x-board-spl.c +22 -6

+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/sdhci at fe330000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc at fe320000",
+};
+
+#ifdef CONFIG_SPL_BUILD
+int arch_cpu_init(void)
 {
-	return BOOT_DEVICE_MMC1;
-}
-DECLARE_GLOBAL_DATA_PTR;
+	static struct rk322x_grf * const grf = (void *)GRF_BASE;
+	/* We do some SoC one time setting here. */
 
-#define GRF_BASE	0x11000000
-#define SGRF_BASE	0x10140000
+	/* Disable the ddr secure region setting to make it non-secure */
+	rk_clrreg(SGRF_DDR_CON0, 0x4000);
+
+	/*
+	 * The integrated macphy is enabled by default, disable it
+	 * for saving power consuming.
+	 */
+	rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK,
+		     0 << MACPHY_CFG_ENABLE_SHIFT);
 
-#define DEBUG_UART_BASE	0x11030000
+	return 0;
+}
+#endif
 
 void board_debug_uart_init(void)
 {

arch/arm/mach-rockchip/rk322x/rk322x.c renamed from arch/arm/mach-rockchip/rk322x-board-spl.c +0 -38

 		GPIO1B1_SHIFT		= 2,

@@ -61,41 +69,3 @@ void board_debug_uart_init(void)
 		     CON_IOMUX_UART2SEL_MASK,
 		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
 }
-
-#define SGRF_DDR_CON0 0x10150000
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	printascii("SPL Init");
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	rockchip_timer_init();
-	printf("timer init done\n");
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		printf("DRAM init failed: %d\n", ret);
-		return;
-	}
-
-	/* Disable the ddr secure region setting to make it non-secure */
-	rk_clrreg(SGRF_DDR_CON0, 0x4000);
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}

We need CONFIG_SPL_DRIVERS_MISC_SUPPORT to enable sysreset driver, which will fix missing do_reset() error in SPL build.

Signed-off-by Kever Yang <[email protected]>

---

 configs/evb-rk3229_defconfig | 1 +
 1 file changed, 1 insertion(+)

We need CONFIG_SPL_DRIVERS_MISC_SUPPORT to enable sysreset driver, which will fix missing do_reset() error in SPL build.

Signed-off-by Kever Yang <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---

 configs/evb-rk3229_defconfig | 1 +
 1 file changed, 1 insertion(+)

We are going to remove rockchip_udelay after enable arch timer.

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

We are going to remove rockchip_udelay after enable arch timer.

Signed-off-by Kever Yang <[email protected]>

---

arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 19 +++++++++----------

1 file changed, 9 insertions(+), 10 deletions(-)

arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +9 -10

index e5393ec..ce3f09a 100644
@@ -10,7 +10,6 @@
 #include <asm/arch/grf_rk3036.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sdram_rk3036.h>
-#include <asm/arch/timer.h>
 #include <asm/arch/uart.h>
 
 /*

@@ -346,7 +345,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
 
 	/* waiting for pll lock */
 	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
-		rockchip_udelay(1);
+		udelay(1);
 
 	/* PLL enter normal-mode */
 	rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,

@@ -374,25 +373,25 @@ void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
 			1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
 			1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
 
-	rockchip_udelay(10);
+	udelay(10);
 
 	rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
 						  1 << DDRPHY_SRST_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 
 	rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
 						  1 << DDRCTRL_SRST_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 
 	clrsetbits_le32(&ddr_phy->ddrphy_reg1,
 			SOFT_RESET_MASK << SOFT_RESET_SHIFT,
 			0 << SOFT_RESET_SHIFT);
-	rockchip_udelay(10);
+	udelay(10);
 	clrsetbits_le32(&ddr_phy->ddrphy_reg1,
 			SOFT_RESET_MASK << SOFT_RESET_SHIFT,
 			3 << SOFT_RESET_SHIFT);
 
-	rockchip_udelay(1);
+	udelay(1);
 }
 
 void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)

@@ -445,7 +444,7 @@ static void send_command(struct rk3036_ddr_pctl *pctl,
 			 u32 rank, u32 cmd, u32 arg)
 {
 	writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
-	rockchip_udelay(1);
+	udelay(1);
 	while (readl(&pctl->mcmd) & START_CMD)
 		;
 }

@@ -455,7 +454,7 @@ static void memory_init(struct rk3036_sdram_priv *priv)
 	struct rk3036_ddr_pctl *pctl = priv->pctl;
 
 	send_command(pctl, 3, DESELECT_CMD, 0);
-	rockchip_udelay(1);
+	udelay(1);
 	send_command(pctl, 3, PREA_CMD, 0);
 	send_command(pctl, 3, MRS_CMD,
 		     (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |

@@ -493,7 +492,7 @@ static void data_training(struct rk3036_sdram_priv *priv)
 	clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
 			DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
 
-	rockchip_udelay(1);
+	udelay(1);
 	while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
 		(HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
 		;

Use ARM arch timer instead.

Signed-off-by Kever Yang <[email protected]>

---

 include/configs/rk3036_common.h | 4 ----
 1 file changed, 4 deletions(-)

Use ARM arch timer instead.

Signed-off-by Kever Yang <[email protected]>

---

 include/configs/rk3036_common.h | 4 ----
 1 file changed, 4 deletions(-)

Move some soc spec setting into rk3036.c

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/mach-rockchip/rk3036-board.c              | 104 ---------------------
 arch/arm/mach-rockchip/rk3036/Makefile             |   2 +-
 .../{rk3036-board-spl.c => rk3036/rk3036.c}        |  41 ++------
 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c       |  14 +++
 4 files changed, 24 insertions(+), 137 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c
 rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%)

Move some soc spec setting into rk3036.c

Signed-off-by Kever Yang <[email protected]>

---

arch/arm/mach-rockchip/rk3036-board.c              | 104 ---------------------
arch/arm/mach-rockchip/rk3036/Makefile             |   2 +-
.../{rk3036-board-spl.c => rk3036/rk3036.c}        |  41 ++------
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c       |  14 +++
4 files changed, 24 insertions(+), 137 deletions(-)

delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c
rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%)

arch/arm/mach-rockchip/rk3036-board.c deleted +0 -104

deleted file mode 100644
index a5d2571..0000000
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/grf_rk3036.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/arch/sdram_rk3036.h>
-#include <asm/gpio.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-
-	return rk_board_late_init();
-}
-
-int board_init(void)
-{
-	return 0;
-}
-
-#if !CONFIG_IS_ENABLED(RAM)
-/*
- * When CONFIG_RAM is enabled, the dram_init() function is implemented
- * in sdram_common.c.
- */
-int dram_init(void)
-{
-	gd->ram_size = sdram_size();
-
-	return 0;
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3036_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3036_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif

arch/arm/mach-rockchip/rk3036/Makefile +1 -1

index 20d28f7..8a144d1 100644
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y += clk_rk3036.o
+obj-y += rk3036.o clk_rk3036.o
 

ifndef CONFIG_SPL_BUILD
obj-y += syscon_rk3036.o

arch/arm/mach-rockchip/rk3036/rk3036.c renamed from arch/arm/mach-rockchip/rk3036-board-spl.c +9 -32

similarity index 50%
rename from arch/arm/mach-rockchip/rk3036-board-spl.c
rename to arch/arm/mach-rockchip/rk3036/rk3036.c
index 550e3a1..39cc43b 100644
@@ -1,28 +1,22 @@
 /*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
-
-#include <common.h>
-#include <debug_uart.h>
 #include <asm/io.h>
 #include <asm/arch/bootrom.h>
-#include <asm/arch/grf_rk3036.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/sdram_rk3036.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
+#include <asm/arch/grf_rk3036.h>
 #define GRF_BASE	0x20008000
 
-#define DEBUG_UART_BASE	0x20068000
-
-void board_init_f(ulong dummy)
+#ifdef CONFIG_SPL_BUILD
+int arch_cpu_init(void)
+{
+	return 0;
+}
+#endif
+void board_debug_uart_init(void)
 {
-#ifdef EARLY_DEBUG
 	struct rk3036_grf * const grf = (void *)GRF_BASE;
 	/*
 	 * NOTE: sd card and debug uart use same iomux in rk3036,

@@ -34,22 +28,5 @@ void board_init_f(ulong dummy)
 		     GPIO1C2_MASK << GPIO1C2_SHIFT,
 		     GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
 		     GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
-	debug_uart_init();
-#endif
-	rockchip_timer_init();
-	sdram_init();
-
-	/* return to maskrom */
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
 
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-	/*
-	 * Function attribute is no-return
-	 * This Function never executes
-	 */
-	while (1)
-		;
 }

arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +14 -0

index ce3f09a..a4fb3ae 100644
@@ -11,6 +11,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/sdram_rk3036.h>
 #include <asm/arch/uart.h>
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
 * we can not fit the code to access the device tree in SPL

@@ -764,3 +765,16 @@ void sdram_init(void)
 	move_to_access_state(&sdram_priv);
 	dram_cfg_rbc(&sdram_priv);
 }
+
+#if !CONFIG_IS_ENABLED(RAM)
+/*
+ * When CONFIG_RAM is enabled, the dram_init() function is implemented
+ * in sdram_common.c.
+ */
+int dram_init(void)
+{
+	gd->ram_size = sdram_size();
+
+	return 0;
+}
+#endif

We need a dedicate sdram_init() function for those SoCS not using SPL_FRAMEWORK.

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/include/asm/arch-rockchip/sys_proto.h | 3 +++
 1 file changed, 3 insertions(+)

We need a dedicate sdram_init() function for those SoCS not using SPL_FRAMEWORK.

Signed-off-by Kever Yang <[email protected]>

---

arch/arm/include/asm/arch-rockchip/sys_proto.h | 3 +++

1 file changed, 3 insertions(+)

arch/arm/include/asm/arch-rockchip/sys_proto.h +0 -0

index 3617ac2..7b7e336 100644

arch/arm/include/asm/arch-rockchip/sys_proto.h +1 -0

+#endif
 
 #endif /* _ASM_ARCH_SYS_PROTO_H */

Trust OS decode this info like this:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19
We have to set a available value, or else we get error info from Trust OS like this:
"ERROR: over or zero region, nr=3145987, max=10"

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/include/asm/arch-rockchip/sdram_common.h |  4 ++++
 arch/arm/mach-rockchip/sdram_common.c             | 21 +++++++++++++++++++++
 2 files changed, 25 insertions(+)

Trust OS decode this info like this:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19
We have to set a available value, or else we get error info from Trust OS like this:
"ERROR: over or zero region, nr=3145987, max=10"

Signed-off-by Kever Yang <[email protected]>

---

arch/arm/include/asm/arch-rockchip/sdram_common.h | 4 ++++
arch/arm/mach-rockchip/sdram_common.c | 21 +++++++++++++++++++++

2 files changed, 25 insertions(+)

arch/arm/include/asm/arch-rockchip/sdram_common.h +4 -0

index fec8586..55c6b81 100644
@@ -55,4 +55,8 @@ size_t rockchip_sdram_size(phys_addr_t reg);
 
 /* Called by U-Boot board_init_r for Rockchip SoCs */
 int dram_init(void);
+
+/* Write ddr param to a known place for trustos */
+int rockchip_setup_ddr_param(struct ram_info *info);
+
 #endif

arch/arm/mach-rockchip/sdram_common.c +0 -0

index 76dbdc8..3a71f09 100644
@@ -12,6 +12,15 @@
 #include <dm/uclass-internal.h>

arch/arm/mach-rockchip/sdram_common.c +3 -0

+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
 	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;

@@ -81,3 +90,15 @@ ulong board_get_usable_ram_top(ulong total_size)
 
 	return (gd->ram_top > top) ? top : gd->ram_top;
 }
+
+int rockchip_setup_ddr_param(struct ram_info *info)

Quoted 6 lines · Kever Yang

Trust OS decode this info like this:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19

We have to set a available value, or else we get error info from Trust OS like this:
"ERROR:   over or zero region, nr=3145987, max=10"

Please describe what changes the patch makes.

Quoted 2 lines

Signed-off-by Kever Yang <[email protected]>

See below for requested changes.

Quoted 29 lines

---

arch/arm/include/asm/arch-rockchip/sdram_common.h |  4 ++++ arch/arm/mach-rockchip/sdram_common.c             | 21
+++++++++++++++++++++

2 files changed, 25 insertions(+)

arch/arm/include/asm/arch-rockchip/sdram_common.h +4 -0

index fec8586..55c6b81 100644
@@ -55,4 +55,8 @@ size_t rockchip_sdram_size(phys_addr_t reg);
 
 /* Called by U-Boot board_init_r for Rockchip SoCs */
 int dram_init(void);
+
+/* Write ddr param to a known place for trustos */
+int rockchip_setup_ddr_param(struct ram_info *info);
+
 #endif

arch/arm/mach-rockchip/sdram_common.c +0 -0

index 76dbdc8..3a71f09 100644
@@ -12,6 +12,15 @@
 #include <dm/uclass-internal.h>
 

arch/arm/mach-rockchip/sdram_common.c line 22

Quoted 9 lines

arch/arm/mach-rockchip/sdram_common.c +8 -0

 DECLARE_GLOBAL_DATA_PTR;
+struct ddr_param {
+    u32 count;
+    u32 reserved;
+    u64 bank_addr;
+    u64 bank_size;
+};
+
+#define PARAM_DRAM_INFO_OFFSET 0x2000000

Having this a fixed offset feels a bit hackish... especially as this is now implemented for all SOCs.

Quoted 15 lines

arch/arm/mach-rockchip/sdram_common.c +5 -0

+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
     u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;

@@ -81,3 +90,15 @@ ulong board_get_usable_ram_top(ulong total_size)
 
     return (gd->ram_top > top) ? top : gd->ram_top;
 }
+
+int rockchip_setup_ddr_param(struct ram_info *info)
+{
+    struct ddr_param *dinfo = (struct ddr_param

*)CONFIG_SYS_SDRAM_BASE +
+                    PARAM_DRAM_INFO_OFFSET;

arch/arm/mach-rockchip/sdram_common.c ulong board_get_usable_ram_top(ulong total_size) · line 104

Quoted 7 lines

arch/arm/mach-rockchip/sdram_common.c +7 -0

+
+    dinfo->count = 1;
+    dinfo->bank_addr = info->base;
+    dinfo->bank_size = info->size;
+
+    return 0;
+}

This setup should only be performed when preparing the system to enter the ATF.  So you will need to hook it into path where the ATF is prepared for being jumped into.

I would further prefer (but this is a personal preference) to eventually move to using the FDT we inject into the ATF to convey this information.

Quoted 1 line