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drm/amdgpu/powerplay: fix smu7_get_memory_type for fiji

PATCH In review Alex Deucher 2 participants 2 messages Apr 11, 2018 – Apr 12, 2018 1 message not in the archive

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PATCH 1/1 drm/amdgpu/powerplay: fix smu7_get_memory_type for fiji

Fiji uses a different register than other smu7 asics, but we already have this info in the base driver so just use that.

---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +2 -6
index 21c021ba0f49..97b7c2333f19 100644
@@ -4150,13 +4150,9 @@ static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-	uint32_t temp;
-
-	temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
+	struct amdgpu_device *adev = hwmgr->adev;
 
-	data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
-			((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
-			 MC_SEQ_MISC0_GDDR5_SHIFT));
+	data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
 
 	return 0;
 }
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2.13.6

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A message that is not in the archive (sent off-list or not yet received): 20180411225908.409-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org

Reviewed-by
#2 lore raw

Best Regards

Rex

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Alex Deucher <[email protected]>
Sent: Thursday, April 12, 2018 6:59 AM
To: [email protected]
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/powerplay: fix smu7_get_memory_type for fiji

Fiji uses a different register than other smu7 asics, but we already have this info in the base driver so just use that.

---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +2 -6
index 21c021ba0f49..97b7c2333f19 100644
@@ -4150,13 +4150,9 @@ static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
 {
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-       uint32_t temp;
-
-       temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
+       struct amdgpu_device *adev = hwmgr->adev;
 
-       data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
-                       ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
-                        MC_SEQ_MISC0_GDDR5_SHIFT));
+       data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
 
         return 0;
 }

--
2.13.6

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