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clk: imx6ull: use OSC clock during AXI rate change

PATCH In review Stefan Agner 4 participants 9 messages Apr 18, 2018 – May 10, 2018

Subsystems (3)
Arm i.MX and Layerscape Common clk NXP i.MX clock drivers
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Stefan Agner

author
#0 lore raw

PATCH 1/1 clk: imx6ull: use OSC clock during AXI rate change

On i.MX6 ULL using PLL3 seems to cause a freeze when setting the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux"), probably because the clock is now forced to be on.

Fixes 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
Signed-off-by Stefan Agner <[email protected]>

---
This addresses a regression ssen on v4.17-rc1 where the kernel boots during clock initialization, see also:
https://patchwork.kernel.org/patch/10295927/

 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/imx/clk-imx6ul.c +1 -1
index 114ecbb94ec5..12320118f8de 100644
@@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
 
 	/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
-	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
+	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
Signature · 1 line
2.17.0
#1 lore raw

Hi Jacky,

Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?

Shawn

Quoted 32 lines · Stefan Agner

On i.MX6 ULL using PLL3 seems to cause a freeze when setting the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux"), probably because the clock is now forced to be on.

Fixes 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
Signed-off-by Stefan Agner <[email protected]>

---
This addresses a regression ssen on v4.17-rc1 where the kernel boots during clock initialization, see also:
https://patchwork.kernel.org/patch/10295927/

 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/imx/clk-imx6ul.c +1 -1
index 114ecbb94ec5..12320118f8de 100644
@@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
 
 	/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
-	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
+	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
Signature · 1 line
2.17.0
author
#2 lore raw

Hi Jacky,

Quoted 3 lines · Shawn Guo

Hi Jacky,

Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?

Any comment to this?

It is 4.17.0-rc4 is out and i.MX 6ULL is still broken :-(

--
Stefan

Quoted 36 lines

Shawn

Quoted 32 lines · Stefan Agner

On i.MX6 ULL using PLL3 seems to cause a freeze when setting the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux"), probably because the clock is now forced to be on.

Fixes 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
Signed-off-by Stefan Agner <[email protected]>

---
This addresses a regression ssen on v4.17-rc1 where the kernel boots during clock initialization, see also:
https://patchwork.kernel.org/patch/10295927/

 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/imx/clk-imx6ul.c +1 -2
index 114ecbb94ec5..12320118f8de 100644
@@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
 
 	/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
-	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
+	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
--

2.17.0

#3 lore raw
Quoted 4 lines

Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

Hi Jacky,

Quoted 9 lines
Quoted 3 lines · Shawn Guo

Hi Jacky,

Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?

Any comment to this?

It is 4.17.0-rc4 is out and i.MX 6ULL is still broken :-(

Hi Stefan,

I have tried two 6ULL board, I don't meet such issue. System can boot up successfully with commit 6f9575e55632 included. Anyway, the change in this patch is ok for me. it is no harm to the BUS clock change flow.

Jacky

Quoted 59 lines

--
Stefan

Quoted 17 lines

Shawn

Quoted 13 lines · Stefan Agner

On i.MX6 ULL using PLL3 seems to cause a freeze when setting the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux"), probably because the clock is now forced to be on.

Fixes 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy

divider and busy mux")

Signed-off-by Stefan Agner <[email protected]>

---
This addresses a regression ssen on v4.17-rc1 where the kernel boots during clock initialization, see also:

https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa

Quoted 1 line
Quoted 1 line

tchwork.kernel.org%2Fpatch%2F10295927%2F&data=02%7C01%7Cping.bai% 40nx

Quoted 1 line
Quoted 1 line

p.com%7C023287ec65034c4db45f08d5b419effb%7C686ea1d3bc2b4c6fa92cd9 9c5c

Quoted 1 line
Quoted 1 line

301635%7C0%7C0%7C636612945852594725&sdata=U0ZGid9ZBey0FXfId2dhZb hVl8p

Quoted 11 lines

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct

Quoted 11 lines

CcjTiexG3JHYwCA4%3D&reserved=0

 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
(quoted diff) +0 -0

b/drivers/clk/imx/clk-imx6ul.c index 114ecbb94ec5..12320118f8de 100644

drivers/clk/imx/clk-imx6ul.c +0 -0
@@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct

device_node *ccm_node)

Quoted 3 lines

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct device_node *ccm_node)

Quoted 3 lines
drivers/clk/imx/clk-imx6ul.c +0 -0
 	clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
 
 	/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz

*/

Quoted 1 line

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct · line 467

Quoted 1 line
drivers/clk/imx/clk-imx6ul.c +0 -1
-	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL],

clks[IMX6UL_CLK_PLL3_USB_OTG]);

Quoted 3 lines

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct · line 469

Quoted 3 lines
drivers/clk/imx/clk-imx6ul.c +2 -0
+	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL],
+clks[IMX6UL_CLK_OSC]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH],

clks[IMX6UL_CLK_PERIPH_CLK2]);

Quoted 1 line

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct · line 470

Quoted 1 line
drivers/clk/imx/clk-imx6ul.c +0 -0
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE],

clks[IMX6UL_CLK_PLL2_BUS]);

Quoted 5 lines
Quoted 5 lines

clk_set_parent(clks[IMX6UL_CLK_PERIPH],
clks[IMX6UL_CLK_PERIPH_PRE]);
--
2.17.0

author
#4 lore raw
Quoted 11 lines · Jacky Bai
Quoted 11 lines

Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

Hi Jacky,

Quoted 3 lines · Shawn Guo

Hi Jacky,

Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?

Any comment to this?

Quoted 8 lines
Quoted 2 lines

It is 4.17.0-rc4 is out and i.MX 6ULL is still broken :-(

Hi Stefan,

I have tried two 6ULL board, I don't meet such issue. System can boot up successfully with commit 6f9575e55632 included.
Anyway, the change in this patch is ok for me. it is no harm to the BUS clock change flow.

Hm, that is interesting, maybe it is because we use a different SKU? Or maybe bootloader?

I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL using U-Boot 2016.11.

--
Stefan

Quoted 61 lines

Jacky

Quoted 59 lines

--
Stefan

Quoted 17 lines

Shawn

Quoted 13 lines · Stefan Agner

On i.MX6 ULL using PLL3 seems to cause a freeze when setting the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux"), probably because the clock is now forced to be on.

Fixes 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy

divider and busy mux")

Signed-off-by Stefan Agner <[email protected]>

---
This addresses a regression ssen on v4.17-rc1 where the kernel boots during clock initialization, see also:

https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa

Quoted 1 line
Quoted 1 line

tchwork.kernel.org%2Fpatch%2F10295927%2F&data=02%7C01%7Cping.bai% 40nx

Quoted 1 line
Quoted 1 line

p.com%7C023287ec65034c4db45f08d5b419effb%7C686ea1d3bc2b4c6fa92cd9 9c5c

Quoted 1 line
Quoted 1 line

301635%7C0%7C0%7C636612945852594725&sdata=U0ZGid9ZBey0FXfId2dhZb hVl8p

Quoted 11 lines

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct

Quoted 11 lines

CcjTiexG3JHYwCA4%3D&reserved=0

 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
(quoted diff) +0 -0

b/drivers/clk/imx/clk-imx6ul.c index 114ecbb94ec5..12320118f8de 100644

drivers/clk/imx/clk-imx6ul.c +0 -0
@@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct

device_node *ccm_node)

Quoted 3 lines

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct device_node *ccm_node)

Quoted 3 lines
drivers/clk/imx/clk-imx6ul.c +0 -0
 	clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
 
 	/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz

*/

Quoted 1 line

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct · line 467

Quoted 1 line
drivers/clk/imx/clk-imx6ul.c +0 -1
-	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL],

clks[IMX6UL_CLK_PLL3_USB_OTG]);

Quoted 3 lines

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct · line 469

Quoted 3 lines
drivers/clk/imx/clk-imx6ul.c +2 -0
+	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL],
+clks[IMX6UL_CLK_OSC]);
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH],

clks[IMX6UL_CLK_PERIPH_CLK2]);

Quoted 1 line

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct · line 470

Quoted 1 line
drivers/clk/imx/clk-imx6ul.c +0 -0
 	clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE],

clks[IMX6UL_CLK_PLL2_BUS]);

Quoted 5 lines
Quoted 5 lines

clk_set_parent(clks[IMX6UL_CLK_PERIPH],
clks[IMX6UL_CLK_PERIPH_PRE]);
--
2.17.0

maintainer
#5 lore raw

Quoting Stefan Agner (2018-05-08 06:20:03)

Quoted 7 lines · Jacky Bai
Quoted 5 lines

I have tried two 6ULL board, I don't meet such issue. System can boot up successfully with commit 6f9575e55632 included.
Anyway, the change in this patch is ok for me. it is no harm to the BUS clock change flow.

Quoted 6 lines

Hm, that is interesting, maybe it is because we use a different SKU? Or maybe bootloader?

I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL using U-Boot 2016.11.

I'll throw this into fixes today because it fixes something to be useful. It's still interesting to see what's different between the two setups though.

#6 lore raw
Quoted 13 lines

Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

Quoting Stefan Agner (2018-05-08 06:20:03)

Quoted 10 lines · Jacky Bai
Quoted 5 lines

I have tried two 6ULL board, I don't meet such issue. System can boot up successfully with commit 6f9575e55632 included. Anyway, the change in this patch is ok for me. it is no harm to the BUS clock change flow.

Hm, that is interesting, maybe it is because we use a different SKU? Or maybe bootloader?

Quoted 6 lines
Quoted 3 lines

I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL using U-Boot 2016.11.

I'll throw this into fixes today because it fixes something to be useful. It's still interesting to see what's different between the two setups though.

Thanks.

I will find some 800MHz parts and have a try with different bootloader later. Will let you know, when I have some results.

Jacky

author
#7 lore raw
Quoted 17 lines · Jacky Bai
Quoted 17 lines

Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

Quoting Stefan Agner (2018-05-08 06:20:03)

Quoted 13 lines · Jacky Bai
Quoted 5 lines

I have tried two 6ULL board, I don't meet such issue. System can boot up successfully with commit 6f9575e55632 included. Anyway, the change in this patch is ok for me. it is no harm to the BUS clock change flow.

Hm, that is interesting, maybe it is because we use a different SKU? Or maybe bootloader?

I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL using U-Boot 2016.11.

Quoted 8 lines
Quoted 2 lines

I'll throw this into fixes today because it fixes something to be useful. It's still interesting to see what's different between the two setups though.

Thanks.

I will find some 800MHz parts and have a try with different bootloader later. Will let you know, when I have some results.

FWIW, I tried two SKUs here:
MCIMX6Z2DVM05AA (528Mhz)
MCIMX6Z2CVM08AA (800MHz)

Both run at 396MHz in U-Boot, and both freeze and the same location.

--
Stefan

#8 lore raw
Quoted 27 lines

Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

Quoted 14 lines · Jacky Bai
Quoted 14 lines

Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change

Quoting Stefan Agner (2018-05-08 06:20:03)

Quoted 10 lines · Jacky Bai
Quoted 5 lines

I have tried two 6ULL board, I don't meet such issue. System can boot up successfully with commit 6f9575e55632 included. Anyway, the change in this patch is ok for me. it is no harm to the BUS clock change flow.

Hm, that is interesting, maybe it is because we use a different SKU? Or maybe bootloader?

Quoted 6 lines
Quoted 6 lines
Quoted 3 lines

I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL using U-Boot 2016.11.

I'll throw this into fixes today because it fixes something to be useful. It's still interesting to see what's different between the two setups

though.

Quoted 3 lines

Thanks.

Quoted 8 lines
Quoted 3 lines

I will find some 800MHz parts and have a try with different bootloader later. Will let you know, when I have some results.

FWIW, I tried two SKUs here:
MCIMX6Z2DVM05AA (528Mhz)
MCIMX6Z2CVM08AA (800MHz)

MCIMX6Z or MCIMX6Y ? I think i.MX6ULL should be 6Y.

Jacky

Quoted 4 lines

Both run at 396MHz in U-Boot, and both freeze and the same location.

--
Stefan