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drm/amd/amdgpu: Add missing DCN CMx_TEST_DEBUG bitfields

PATCH New Tom St Denis 1 participant 1 message Apr 18, 2018

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DRM drivers Radeon and amdgpu DRM drivers
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Tom St Denis

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PATCH 1/1 drm/amd/amdgpu: Add missing DCN CMx_TEST_DEBUG bitfields

Only the bitfields for CM0 were initially added. This adds the rest for CM1..CM3 that way umr can pick up the bitfields for all of the debug registers.

Signed-off-by Tom St Denis <[email protected]>
---
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h    | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h +15 -0
index e7c0cad41081..9d860e4fff0b 100644
@@ -14054,6 +14054,21 @@
 #define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
 #define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
 #define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
 //CM0_CM_TEST_DEBUG_DATA
 #define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
 #define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
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2.14.3

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