agp/intel-gtt: Drop the code for gen > 1

index c6271ce250b3..82459b886868 100644
@@ -40,12 +40,6 @@
 #endif
 
 struct intel_gtt_driver {
-	unsigned int gen : 8;
-	unsigned int is_g33 : 1;
-	unsigned int is_pineview : 1;
-	unsigned int is_ironlake : 1;
-	unsigned int has_pgtbl_enable : 1;
-	unsigned int dma_mask_size : 8;
 	/* Chipset specific GTT setup */
 	int (*setup)(void);
 	/* This should undo anything done in ->setup() save the unmapping

@@ -88,12 +82,6 @@ static struct _intel_private {
 	unsigned int gtt_mappable_entries;
 } intel_private;
 
-#define INTEL_GTT_GEN	intel_private.driver->gen
-#define IS_G33		intel_private.driver->is_g33
-#define IS_PINEVIEW	intel_private.driver->is_pineview
-#define IS_IRONLAKE	intel_private.driver->is_ironlake
-#define HAS_PGTBL_EN	intel_private.driver->has_pgtbl_enable
-
 #if IS_ENABLED(CONFIG_AGP_INTEL)
 static int intel_gtt_map_memory(struct page **pages,
 				unsigned int num_entries,

@@ -335,212 +323,27 @@ static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 
 static resource_size_t intel_gtt_stolen_size(void)
 {
-	u16 gmch_ctrl;
-	u8 rdct;
-	int local = 0;
-	static const int ddt[4] = { 0, 16, 32, 64 };
-	resource_size_t stolen_size = 0;
-
-	if (INTEL_GTT_GEN == 1)
-		return 0; /* no stolen mem on i81x */
-
-	pci_read_config_word(intel_private.bridge_dev,
-			     I830_GMCH_CTRL, &gmch_ctrl);
-
-	if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
-	    intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
-		switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
-		case I830_GMCH_GMS_STOLEN_512:
-			stolen_size = KB(512);
-			break;
-		case I830_GMCH_GMS_STOLEN_1024:
-			stolen_size = MB(1);
-			break;
-		case I830_GMCH_GMS_STOLEN_8192:
-			stolen_size = MB(8);
-			break;
-		case I830_GMCH_GMS_LOCAL:
-			rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
-			stolen_size = (I830_RDRAM_ND(rdct) + 1) *
-					MB(ddt[I830_RDRAM_DDT(rdct)]);
-			local = 1;
-			break;
-		default:
-			stolen_size = 0;
-			break;
-		}
-	} else {
-		switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
-		case I855_GMCH_GMS_STOLEN_1M:
-			stolen_size = MB(1);
-			break;
-		case I855_GMCH_GMS_STOLEN_4M:
-			stolen_size = MB(4);
-			break;
-		case I855_GMCH_GMS_STOLEN_8M:
-			stolen_size = MB(8);
-			break;
-		case I855_GMCH_GMS_STOLEN_16M:
-			stolen_size = MB(16);
-			break;
-		case I855_GMCH_GMS_STOLEN_32M:
-			stolen_size = MB(32);
-			break;
-		case I915_GMCH_GMS_STOLEN_48M:
-			stolen_size = MB(48);
-			break;
-		case I915_GMCH_GMS_STOLEN_64M:
-			stolen_size = MB(64);
-			break;
-		case G33_GMCH_GMS_STOLEN_128M:
-			stolen_size = MB(128);
-			break;
-		case G33_GMCH_GMS_STOLEN_256M:
-			stolen_size = MB(256);
-			break;
-		case INTEL_GMCH_GMS_STOLEN_96M:
-			stolen_size = MB(96);
-			break;
-		case INTEL_GMCH_GMS_STOLEN_160M:
-			stolen_size = MB(160);
-			break;
-		case INTEL_GMCH_GMS_STOLEN_224M:
-			stolen_size = MB(224);
-			break;
-		case INTEL_GMCH_GMS_STOLEN_352M:
-			stolen_size = MB(352);
-			break;
-		default:
-			stolen_size = 0;
-			break;
-		}
-	}
-
-	if (stolen_size > 0) {
-		dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n",
-		       (u64)stolen_size / KB(1), local ? "local" : "stolen");
-	} else {
-		dev_info(&intel_private.bridge_dev->dev,
-		       "no pre-allocated video memory detected\n");
-		stolen_size = 0;
-	}
-
-	return stolen_size;
-}
-
-static void i965_adjust_pgetbl_size(unsigned int size_flag)
-{
-	u32 pgetbl_ctl, pgetbl_ctl2;
-
-	/* ensure that ppgtt is disabled */
-	pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
-	pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
-	writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
-
-	/* write the new ggtt size */
-	pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
-	pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
-	pgetbl_ctl |= size_flag;
-	writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
-}
-
-static unsigned int i965_gtt_total_entries(void)
-{
-	int size;
-	u32 pgetbl_ctl;
-	u16 gmch_ctl;
-
-	pci_read_config_word(intel_private.bridge_dev,
-			     I830_GMCH_CTRL, &gmch_ctl);
-
-	if (INTEL_GTT_GEN == 5) {
-		switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
-		case G4x_GMCH_SIZE_1M:
-		case G4x_GMCH_SIZE_VT_1M:
-			i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
-			break;
-		case G4x_GMCH_SIZE_VT_1_5M:
-			i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
-			break;
-		case G4x_GMCH_SIZE_2M:
-		case G4x_GMCH_SIZE_VT_2M:
-			i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
-			break;
-		}
-	}
-
-	pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
-
-	switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
-	case I965_PGETBL_SIZE_128KB:
-		size = KB(128);
-		break;
-	case I965_PGETBL_SIZE_256KB:
-		size = KB(256);
-		break;
-	case I965_PGETBL_SIZE_512KB:
-		size = KB(512);
-		break;
-	/* GTT pagetable sizes bigger than 512KB are not possible on G33! */
-	case I965_PGETBL_SIZE_1MB:
-		size = KB(1024);
-		break;
-	case I965_PGETBL_SIZE_2MB:
-		size = KB(2048);
-		break;
-	case I965_PGETBL_SIZE_1_5MB:
-		size = KB(1024 + 512);
-		break;
-	default:
-		dev_info(&intel_private.pcidev->dev,
-			 "unknown page table size, assuming 512KB\n");
-		size = KB(512);
-	}
-
-	return size/4;
+	return 0; /* no stolen mem on i81x */
 }
 
 static unsigned int intel_gtt_total_entries(void)
 {
-	if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
-		return i965_gtt_total_entries();
-	else {
-		/* On previous hardware, the GTT size was just what was
-		 * required to map the aperture.
-		 */
-		return intel_private.gtt_mappable_entries;
-	}
+	return intel_private.gtt_mappable_entries;
 }
 
 static unsigned int intel_gtt_mappable_entries(void)
 {
 	unsigned int aperture_size;
+	u32 smram_miscc;
 
-	if (INTEL_GTT_GEN == 1) {
-		u32 smram_miscc;
+	pci_read_config_dword(intel_private.bridge_dev,
+			      I810_SMRAM_MISCC, &smram_miscc);
 
-		pci_read_config_dword(intel_private.bridge_dev,
-				      I810_SMRAM_MISCC, &smram_miscc);
-
-		if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
-				== I810_GFX_MEM_WIN_32M)
-			aperture_size = MB(32);
-		else
-			aperture_size = MB(64);
-	} else if (INTEL_GTT_GEN == 2) {
-		u16 gmch_ctrl;
-
-		pci_read_config_word(intel_private.bridge_dev,
-				     I830_GMCH_CTRL, &gmch_ctrl);
-
-		if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
-			aperture_size = MB(64);
-		else
-			aperture_size = MB(128);
-	} else {
-		/* 9xx supports large sizes, just look at the length */
-		aperture_size = pci_resource_len(intel_private.pcidev, 2);
-	}
+	if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
+			== I810_GFX_MEM_WIN_32M)
+		aperture_size = MB(32);
+	else
+		aperture_size = MB(64);
 
 	return aperture_size >> PAGE_SHIFT;
 }

@@ -586,17 +389,7 @@ static inline int needs_ilk_vtd_wa(void)
 
 static bool intel_gtt_can_wc(void)
 {
-	if (INTEL_GTT_GEN <= 2)
-		return false;
-
-	if (INTEL_GTT_GEN >= 6)
-		return false;
-
-	/* Reports of major corruption with ILK vt'd enabled */
-	if (needs_ilk_vtd_wa())
-		return false;
-
-	return true;
+	return false;
 }
 
 static int intel_gtt_init(void)

@@ -616,8 +409,7 @@ static int intel_gtt_init(void)
 		readl(intel_private.registers+I810_PGETBL_CTL)
 			& ~I810_PGETBL_ENABLED;
 	/* we only ever restore the register when enabling the PGTBL... */
-	if (HAS_PGTBL_EN)
-		intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
+        intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 
 	dev_info(&intel_private.bridge_dev->dev,
 			"detected gtt size: %dK total, %dK mappable\n",

@@ -645,7 +437,7 @@ static int intel_gtt_init(void)
 
 	intel_private.stolen_size = intel_gtt_stolen_size();
 
-	intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
+	intel_private.needs_dmar = 0; /* XXX */
 
 	ret = intel_gtt_setup_scratch_page();
 	if (ret != 0) {

@@ -653,10 +445,7 @@ static int intel_gtt_init(void)
 		return ret;
 	}
 
-	if (INTEL_GTT_GEN <= 2)
-		bar = I810_GMADR_BAR;
-	else
-		bar = I915_GMADR_BAR;
+	bar = I810_GMADR_BAR;
 
 	intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
 	return 0;

@@ -691,116 +480,23 @@ static int intel_fake_agp_fetch_size(void)
 }
 #endif
 
-static void i830_cleanup(void)
-{
-}
-
-/* The chipset_flush interface needs to get data that has already been
- * flushed out of the CPU all the way out to main memory, because the GPU
- * doesn't snoop those buffers.
- *
- * The 8xx series doesn't have the same lovely interface for flushing the
- * chipset write buffers that the later chips do. According to the 865
- * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
- * that buffer out, we just fill 1KB and clflush it out, on the assumption
- * that it'll push whatever was in there out.  It appears to work.
- */
-static void i830_chipset_flush(void)
-{
-	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
-
-	/* Forcibly evict everything from the CPU write buffers.
-	 * clflush appears to be insufficient.
-	 */
-	wbinvd_on_all_cpus();
-
-	/* Now we've only seen documents for this magic bit on 855GM,
-	 * we hope it exists for the other gen2 chipsets...
-	 *
-	 * Also works as advertised on my 845G.
-	 */
-	writel(readl(intel_private.registers+I830_HIC) | (1<<31),
-	       intel_private.registers+I830_HIC);
-
-	while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
-		if (time_after(jiffies, timeout))
-			break;
-
-		udelay(50);
-	}
-}
-
-static void i830_write_entry(dma_addr_t addr, unsigned int entry,
-			     unsigned int flags)
-{
-	u32 pte_flags = I810_PTE_VALID;
-
-	if (flags ==  AGP_USER_CACHED_MEMORY)
-		pte_flags |= I830_PTE_SYSTEM_CACHED;
-
-	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
-}
-
 bool intel_enable_gtt(void)
 {
 	u8 __iomem *reg;
 
-	if (INTEL_GTT_GEN == 2) {
-		u16 gmch_ctrl;
-
-		pci_read_config_word(intel_private.bridge_dev,
-				     I830_GMCH_CTRL, &gmch_ctrl);
-		gmch_ctrl |= I830_GMCH_ENABLED;
-		pci_write_config_word(intel_private.bridge_dev,
-				      I830_GMCH_CTRL, gmch_ctrl);
-
-		pci_read_config_word(intel_private.bridge_dev,
-				     I830_GMCH_CTRL, &gmch_ctrl);
-		if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
-			dev_err(&intel_private.pcidev->dev,
-				"failed to enable the GTT: GMCH_CTRL=%x\n",
-				gmch_ctrl);
-			return false;
-		}
-	}
-
-	/* On the resume path we may be adjusting the PGTBL value, so
-	 * be paranoid and flush all chipset write buffers...
-	 */
-	if (INTEL_GTT_GEN >= 3)
-		writel(0, intel_private.registers+GFX_FLSH_CNTL);
-
 	reg = intel_private.registers+I810_PGETBL_CTL;
 	writel(intel_private.PGETBL_save, reg);
-	if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
+	if ((readl(reg) & I810_PGETBL_ENABLED) == 0) {
 		dev_err(&intel_private.pcidev->dev,
 			"failed to enable the GTT: PGETBL=%x [expected %x]\n",
 			readl(reg), intel_private.PGETBL_save);
 		return false;
 	}
 
-	if (INTEL_GTT_GEN >= 3)
-		writel(0, intel_private.registers+GFX_FLSH_CNTL);
-
 	return true;
 }
 EXPORT_SYMBOL(intel_enable_gtt);
 
-static int i830_setup(void)
-{
-	phys_addr_t reg_addr;
-
-	reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
-
-	intel_private.registers = ioremap(reg_addr, KB(64));
-	if (!intel_private.registers)
-		return -ENOMEM;
-
-	intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
-
-	return 0;
-}
-
 #if IS_ENABLED(CONFIG_AGP_INTEL)
 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 {

@@ -905,7 +601,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 		intel_private.clear_fake_agp = false;
 	}
 
-	if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
+	if (type == AGP_DCACHE_MEMORY)
 		return i810_insert_dcache_entries(mem, pg_start, type);
 
 	if (mem->page_count == 0)

@@ -980,7 +676,7 @@ static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
 {
 	struct agp_memory *new;
 
-	if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
+	if (type == AGP_DCACHE_MEMORY) {
 		if (pg_count != intel_private.num_dcache_entries)
 			return NULL;
 

@@ -1001,158 +697,6 @@ static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
 }
 #endif
 
-static int intel_alloc_chipset_flush_resource(void)
-{
-	int ret;
-	ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
-				     PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
-				     pcibios_align_resource, intel_private.bridge_dev);
-
-	return ret;
-}
-
-static void intel_i915_setup_chipset_flush(void)
-{
-	int ret;
-	u32 temp;
-
-	pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
-	if (!(temp & 0x1)) {
-		intel_alloc_chipset_flush_resource();
-		intel_private.resource_valid = 1;
-		pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
-	} else {
-		temp &= ~1;
-
-		intel_private.resource_valid = 1;
-		intel_private.ifp_resource.start = temp;
-		intel_private.ifp_resource.end = temp + PAGE_SIZE;
-		ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
-		/* some BIOSes reserve this area in a pnp some don't */
-		if (ret)
-			intel_private.resource_valid = 0;
-	}
-}
-
-static void intel_i965_g33_setup_chipset_flush(void)
-{
-	u32 temp_hi, temp_lo;
-	int ret;
-
-	pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
-	pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
-
-	if (!(temp_lo & 0x1)) {
-
-		intel_alloc_chipset_flush_resource();
-
-		intel_private.resource_valid = 1;
-		pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
-			upper_32_bits(intel_private.ifp_resource.start));
-		pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
-	} else {
-		u64 l64;
-
-		temp_lo &= ~0x1;
-		l64 = ((u64)temp_hi << 32) | temp_lo;
-
-		intel_private.resource_valid = 1;
-		intel_private.ifp_resource.start = l64;
-		intel_private.ifp_resource.end = l64 + PAGE_SIZE;
-		ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
-		/* some BIOSes reserve this area in a pnp some don't */
-		if (ret)
-			intel_private.resource_valid = 0;
-	}
-}
-
-static void intel_i9xx_setup_flush(void)
-{
-	/* return if already configured */
-	if (intel_private.ifp_resource.start)
-		return;
-
-	if (INTEL_GTT_GEN == 6)
-		return;
-
-	/* setup a resource for this object */
-	intel_private.ifp_resource.name = "Intel Flush Page";
-	intel_private.ifp_resource.flags = IORESOURCE_MEM;
-
-	/* Setup chipset flush for 915 */
-	if (IS_G33 || INTEL_GTT_GEN >= 4) {
-		intel_i965_g33_setup_chipset_flush();
-	} else {
-		intel_i915_setup_chipset_flush();
-	}
-
-	if (intel_private.ifp_resource.start)
-		intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
-	if (!intel_private.i9xx_flush_page)
-		dev_err(&intel_private.pcidev->dev,
-			"can't ioremap flush page - no chipset flushing\n");
-}
-
-static void i9xx_cleanup(void)
-{
-	if (intel_private.i9xx_flush_page)
-		iounmap(intel_private.i9xx_flush_page);
-	if (intel_private.resource_valid)
-		release_resource(&intel_private.ifp_resource);
-	intel_private.ifp_resource.start = 0;
-	intel_private.resource_valid = 0;
-}
-
-static void i9xx_chipset_flush(void)
-{
-	if (intel_private.i9xx_flush_page)
-		writel(1, intel_private.i9xx_flush_page);
-}
-
-static void i965_write_entry(dma_addr_t addr,
-			     unsigned int entry,
-			     unsigned int flags)
-{
-	u32 pte_flags;
-
-	pte_flags = I810_PTE_VALID;
-	if (flags == AGP_USER_CACHED_MEMORY)
-		pte_flags |= I830_PTE_SYSTEM_CACHED;
-
-	/* Shift high bits down */
-	addr |= (addr >> 28) & 0xf0;
-	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
-}
-
-static int i9xx_setup(void)
-{
-	phys_addr_t reg_addr;
-	int size = KB(512);
-
-	reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
-
-	intel_private.registers = ioremap(reg_addr, size);
-	if (!intel_private.registers)
-		return -ENOMEM;
-
-	switch (INTEL_GTT_GEN) {
-	case 3:
-		intel_private.gtt_phys_addr =
-			pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
-		break;
-	case 5:
-		intel_private.gtt_phys_addr = reg_addr + MB(2);
-		break;
-	default:
-		intel_private.gtt_phys_addr = reg_addr + KB(512);
-		break;
-	}
-
-	intel_i9xx_setup_flush();
-
-	return 0;
-}
-
 #if IS_ENABLED(CONFIG_AGP_INTEL)
 static const struct agp_bridge_driver intel_fake_agp_driver = {
 	.owner			= THIS_MODULE,

@@ -1178,84 +722,11 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
 #endif
 
 static const struct intel_gtt_driver i81x_gtt_driver = {
-	.gen = 1,
-	.has_pgtbl_enable = 1,
-	.dma_mask_size = 32,
 	.setup = i810_setup,
 	.cleanup = i810_cleanup,
 	.check_flags = i830_check_flags,
 	.write_entry = i810_write_entry,
 };
-static const struct intel_gtt_driver i8xx_gtt_driver = {
-	.gen = 2,
-	.has_pgtbl_enable = 1,
-	.setup = i830_setup,
-	.cleanup = i830_cleanup,
-	.write_entry = i830_write_entry,
-	.dma_mask_size = 32,
-	.check_flags = i830_check_flags,
-	.chipset_flush = i830_chipset_flush,
-};
-static const struct intel_gtt_driver i915_gtt_driver = {
-	.gen = 3,
-	.has_pgtbl_enable = 1,
-	.setup = i9xx_setup,
-	.cleanup = i9xx_cleanup,
-	/* i945 is the last gpu to need phys mem (for overlay and cursors). */
-	.write_entry = i830_write_entry,
-	.dma_mask_size = 32,
-	.check_flags = i830_check_flags,
-	.chipset_flush = i9xx_chipset_flush,
-};
-static const struct intel_gtt_driver g33_gtt_driver = {
-	.gen = 3,
-	.is_g33 = 1,
-	.setup = i9xx_setup,
-	.cleanup = i9xx_cleanup,
-	.write_entry = i965_write_entry,
-	.dma_mask_size = 36,
-	.check_flags = i830_check_flags,
-	.chipset_flush = i9xx_chipset_flush,
-};
-static const struct intel_gtt_driver pineview_gtt_driver = {
-	.gen = 3,
-	.is_pineview = 1, .is_g33 = 1,
-	.setup = i9xx_setup,
-	.cleanup = i9xx_cleanup,
-	.write_entry = i965_write_entry,
-	.dma_mask_size = 36,
-	.check_flags = i830_check_flags,
-	.chipset_flush = i9xx_chipset_flush,
-};
-static const struct intel_gtt_driver i965_gtt_driver = {
-	.gen = 4,
-	.has_pgtbl_enable = 1,
-	.setup = i9xx_setup,
-	.cleanup = i9xx_cleanup,
-	.write_entry = i965_write_entry,
-	.dma_mask_size = 36,
-	.check_flags = i830_check_flags,
-	.chipset_flush = i9xx_chipset_flush,
-};
-static const struct intel_gtt_driver g4x_gtt_driver = {
-	.gen = 5,
-	.setup = i9xx_setup,
-	.cleanup = i9xx_cleanup,
-	.write_entry = i965_write_entry,
-	.dma_mask_size = 36,
-	.check_flags = i830_check_flags,
-	.chipset_flush = i9xx_chipset_flush,
-};
-static const struct intel_gtt_driver ironlake_gtt_driver = {
-	.gen = 5,
-	.is_ironlake = 1,
-	.setup = i9xx_setup,
-	.cleanup = i9xx_cleanup,
-	.write_entry = i965_write_entry,
-	.dma_mask_size = 36,
-	.check_flags = i830_check_flags,
-	.chipset_flush = i9xx_chipset_flush,
-};
 
 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
  * driver and gmch_driver must be non-null, and find_gmch will determine

@@ -1274,68 +745,6 @@ static const struct intel_gtt_driver_description {
 		&i81x_gtt_driver},
 	{ PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
 		&i81x_gtt_driver},
-	{ PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
-		&i8xx_gtt_driver},
-	{ PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
-		&i8xx_gtt_driver},
-	{ PCI_DEVICE_ID_INTEL_82854_IG, "854",
-		&i8xx_gtt_driver},
-	{ PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
-		&i8xx_gtt_driver},
-	{ PCI_DEVICE_ID_INTEL_82865_IG, "865",
-		&i8xx_gtt_driver},
-	{ PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
-		&i915_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
-		&i915_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
-		&i915_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
-		&i915_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
-		&i915_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
-		&i915_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
-		&i965_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
-		&i965_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
-		&i965_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
-		&i965_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
-		&i965_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
-		&i965_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_G33_IG, "G33",
-		&g33_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
-		&g33_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
-		&g33_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
-		&pineview_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
-		&pineview_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
-		&g4x_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
-		&g4x_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
-		&g4x_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
-		&g4x_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_B43_IG, "B43",
-		&g4x_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
-		&g4x_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_G41_IG, "G41",
-		&g4x_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
-	    "HD Graphics", &ironlake_gtt_driver },
-	{ PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
-	    "HD Graphics", &ironlake_gtt_driver },
 	{ 0, NULL, NULL }
 };
 

@@ -1383,16 +792,12 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
 
 #if IS_ENABLED(CONFIG_AGP_INTEL)
 	if (bridge) {
-		if (INTEL_GTT_GEN > 1)
-			return 0;
-
 		bridge->driver = &intel_fake_agp_driver;
 		bridge->dev_private_data = &intel_private;
 		bridge->dev = bridge_pdev;
 	}
 #endif
 
-
 	/*
 	 * Can be called from the fake agp driver but also directly from
 	 * drm/i915.ko. Hence we need to check whether everything is set up

@@ -1405,7 +810,7 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
 
 	dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
 
-	mask = intel_private.driver->dma_mask_size;
+	mask = 32;
 	if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
 		dev_err(&intel_private.pcidev->dev,
 			"set gfx device dma mask %d-bit failed!\n", mask);