drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing
Subsystems (3)
PATCH 1/1 drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing
commit 5e1df40f40ee45a97bb1066c3d71f0ae920a9672 upstream.
Currently we see sporadic timeouts during CDCLK changing both on BXT and GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by changing the frequency in a tight loop after blanking the display. The upper bound for the completion time is 800us based on my tests, so increase it from the current 500us to 2ms; with that I couldn't trigger the problem either on BXT or GLK.
Note that timeouts happened during both the change notification and the voltage level setting PCODE request. (For the latter one BSpec doesn't require us to wait for completion before further HW programming.)
This issue is similar to
commit 2c7d0602c815 ("drm/i915/gen9: Fix PCODE polling during CDCLK change notification")
but there the PCODE request does complete (as shown by the mbox busy flag), only the reply we get from PCODE indicates a failure. So there we keep resending the request until a success reply, here we just have to increase the timeout for the one PCODE request we send.
v2:
- s/snb_pcode_request/sandybridge_pcode_write_timeout/ (Ville)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103326
(Rebased for v4.9 stable tree due to upstream intel_cdclk.c, cdclk_state and pcu_lock change)
--- drivers/gpu/drm/i915/i915_drv.h | 6 +++++- drivers/gpu/drm/i915/intel_display.c | 9 +++++---- drivers/gpu/drm/i915/intel_pm.c | 6 +++--- 3 files changed, 13 insertions(+), 8 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +5 -1
@@ -3681,7 +3681,11 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, struct intel_display_error_state *error);int sandybridge_pcode_read (struct drm_i915_private *dev_priv,u32 mbox,u32 *val); -int sandybridge_pcode_write (struct drm_i915_private *dev_priv,u32 mbox,u32 val); +int sandybridge_pcode_write_timeout (struct drm_i915_private *dev_priv,u32 mbox, +u32 val,int timeout_us); +#define sandybridge_pcode_write (dev_priv, mbox, val) \ + sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500) +int skl_pcode_request (struct drm_i915_private *dev_priv,u32 mbox,u32 request,u32 reply_mask,u32 reply,int timeout_base_ms);
drivers/gpu/drm/i915/intel_display.c +5 -4
@@ -6012,8 +6012,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)/* Inform power controller of upcoming frequency change */ mutex_lock (&dev_priv->rps.hw_lock); - ret =sandybridge_pcode_write (dev_priv,HSW_PCODE_DE_WRITE_FREQ_REQ , -0x80000000 ); + ret =sandybridge_pcode_write_timeout (dev_priv,HSW_PCODE_DE_WRITE_FREQ_REQ , +0x80000000 ,2000 );mutex_unlock (&dev_priv->rps.hw_lock);if (ret) {
@@ -6044,8 +6044,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)I915_WRITE (CDCLK_CTL , val);mutex_lock (&dev_priv->rps.hw_lock); - ret =sandybridge_pcode_write (dev_priv,HSW_PCODE_DE_WRITE_FREQ_REQ , -DIV_ROUND_UP (cdclk,25000 )); + ret =sandybridge_pcode_write_timeout (dev_priv, +HSW_PCODE_DE_WRITE_FREQ_REQ , +DIV_ROUND_UP (cdclk,25000 ),2000 );mutex_unlock (&dev_priv->rps.hw_lock);if (ret) {
drivers/gpu/drm/i915/intel_pm.c +3 -3
@@ -7913,8 +7913,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *valreturn 0 ; } -int sandybridge_pcode_write (struct drm_i915_private *dev_priv, -u32 mbox,u32 val) +int sandybridge_pcode_write_timeout (struct drm_i915_private *dev_priv, +u32 mbox,u32 val,int timeout_us) {int status;
@@ -7935,7 +7935,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv,if (intel_wait_for_register_fw (dev_priv,GEN6_PCODE_MAILBOX ,GEN6_PCODE_READY ,0 , -500 )) { + timeout_us)) {DRM_ERROR ("timeout waiting for pcode write (%d) to finish\n" , mbox);return -ETIMEDOUT ; }
Signature · 1 line
2.13.2
Greg Kroah-Hartman
maintainerQuoted 34 lines · Imre Deak
commit
5e1df40f40ee45a97bb1066c3d71f0ae920a9672upstream.Currently we see sporadic timeouts during CDCLK changing both on BXT and GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by changing the frequency in a tight loop after blanking the display. The upper bound for the completion time is 800us based on my tests, so increase it from the current 500us to 2ms; with that I couldn't trigger the problem either on BXT or GLK.
Note that timeouts happened during both the change notification and the voltage level setting PCODE request. (For the latter one BSpec doesn't require us to wait for completion before further HW programming.)
This issue is similar to
commit2c7d0602c815("drm/i915/gen9: Fix PCODE polling during CDCLK change notification")
but there the PCODE request does complete (as shown by the mbox busy flag), only the reply we get from PCODE indicates a failure. So there we keep resending the request until a success reply, here we just have to increase the timeout for the one PCODE request we send.v2:
- s/snb_pcode_request/sandybridge_pcode_write_timeout/ (Ville)Cc Chris Wilson <[email protected]>Cc Ville Syrj�l� <[email protected]>Cc <[email protected]> # v4.9Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103326
Reviewed-by Ville Syrj�l� <[email protected]>Signed-off-by Imre Deak <[email protected]>(cherry picked from commit e76019a81921e87a4d9e7b3d86102bc708a6c227)Signed-off-by Rodrigo Vivi <[email protected]>
Quoted 7 lines
(Rebased for v4.9 stable tree due to upstream
intel_cdclk.c,cdclk_stateandpcu_lockchange)Signed-off-by Imre Deak <[email protected]>--- drivers/gpu/drm/i915/i915_drv.h | 6 +++++- drivers/gpu/drm/i915/intel_display.c | 9 +++++---- drivers/gpu/drm/i915/intel_pm.c | 6 +++--- 3 files changed, 13 insertions(+), 8 deletions(-)
Now queued up, thanks.
greg k-h