Linux Patch #5
Subsystems (4)
PATCH v6 5/10 Linux Patch #5
It does not do much except show the words 'Vulnerable' for recent x86 cores. Intel cores prior to Nehalem are known not to be vulnerable, and so are some Atoms and some Xeon Phi.
It assumes that older Cyrix, Centaur, etc. cores are immune.
xReviewed-by Borislav Petkov <[email protected]>
Signed-off-by Konrad Rzeszutek Wilk <[email protected]>
---
v1.3: Remove AMD
s/md/mdd/
v1.4: s/mdd/sbb/
v3: s/SSB/SPEC_STORE_BYPASS
Rework the logic in cpu_set_bug_bits to be inverse.
v4: Expanded the not affected array
- s/X86_BUG_CPU_SPEC_STORE_BYPASS/X86_BUG_SPEC_STORE_BYPASS/
v6: Added Reviewed-by
--- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/bugs.c | 5 +++++ arch/x86/kernel/cpu/common.c | 20 ++++++++++++++++++++ drivers/base/cpu.c | 8 ++++++++ include/linux/cpu.h | 2 ++ 5 files changed, 36 insertions(+)
arch/x86/include/asm/cpufeatures.h +1 -0
@@ -362,5 +362,6 @@#define X86_BUG_CPU_MELTDOWN X86_BUG(14)/* CPU is affected by meltdown attack and needs kernel page table isolation */ #define X86_BUG_SPECTRE_V1 X86_BUG(15)/* CPU is affected by Spectre variant 1 attack with conditional branches */ #define X86_BUG_SPECTRE_V2 X86_BUG(16)/* CPU is affected by Spectre variant 2 attack with indirect branches */ +#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17)/* CPU is affected by speculative store bypass attack */ #endif /* _ASM_X86_CPUFEATURES_H */
arch/x86/kernel/cpu/bugs.c +5 -0
@@ -404,4 +404,9 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c {return cpu_show_common (dev, attr, buf,X86_BUG_SPECTRE_V2 ); } + +ssize_t cpu_show_spec_store_bypass (struct device *dev,struct device_attribute *attr,char *buf) +{ +return cpu_show_common (dev, attr, buf,X86_BUG_SPEC_STORE_BYPASS ); +}#endif
arch/x86/kernel/cpu/common.c +20 -0
@@ -923,10 +923,30 @@ static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { {} }; +static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = { + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_ATOM_PINEVIEW }, + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_ATOM_LINCROFT }, + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_ATOM_PENWELL }, + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_ATOM_CLOVERVIEW }, + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_ATOM_CEDARVIEW }, + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_ATOM_SILVERMONT1 }, + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_ATOM_AIRMONT }, + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_XEON_PHI_KNL }, + {X86_VENDOR_INTEL ,6 ,INTEL_FAM6_XEON_PHI_KNM }, + {X86_VENDOR_CENTAUR ,5 }, + {X86_VENDOR_INTEL ,5 }, + {X86_VENDOR_NSC ,5 }, + {X86_VENDOR_ANY ,4 }, + {} +}; +static void __init cpu_set_bug_bits (struct cpuinfo_x86 *c) {u64 ia32_cap =0 ; +if (!x86_match_cpu (cpu_no_spec_store_bypass)) +setup_force_cpu_bug (X86_BUG_SPEC_STORE_BYPASS ); +if (x86_match_cpu (cpu_no_speculation))return ;
drivers/base/cpu.c +8 -0
@@ -534,14 +534,22 @@ ssize_t __weak cpu_show_spectre_v2(struct device *dev,return sprintf (buf,"Not affected\n" ); } +ssize_t __weak cpu_show_spec_store_bypass (struct device *dev, +struct device_attribute *attr,char *buf) +{ +return sprintf (buf,"Not affected\n" ); +} + static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL); static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL); static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL); +static DEVICE_ATTR(spec_store_bypass, 0444, cpu_show_spec_store_bypass, NULL);static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_meltdown.attr, &dev_attr_spectre_v1.attr, &dev_attr_spectre_v2.attr, + &dev_attr_spec_store_bypass.attr,NULL };
include/linux/cpu.h +2 -0
@@ -53,6 +53,8 @@ extern ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf);extern ssize_t cpu_show_spectre_v2 (struct device *dev,struct device_attribute *attr,char *buf); +extern ssize_t cpu_show_spec_store_bypass (struct device *dev, +struct device_attribute *attr,char *buf); extern __printf(4, 5) struct device *cpu_device_create(struct device *parent, void *drvdata,
Signature · 1 line
2.14.3