Linux Patch #9

PATCH In review [email protected] 1 participant 1 message Apr 27, 2018

Subsystems (2)

x86 x86 hardware vulnerabilities

lore

Share & tools

lore

[email protected]

author

2018-04-27 00:01 UTC #0 lore raw

PATCH v6 9/10 Linux Patch #9

AMD does not need the Speculative Store Bypass mitigation to be enabled.

But the parameters for this are already available and can be done via MSR C001_1020. Each family uses a different bit in that MSR for this.

xReviewed-by Borislav Petkov <[email protected]>

Signed-off-by Konrad Rzeszutek Wilk <[email protected]>

---
v2: New patch
v3: Use the right CPU features
Move the whole logic in early_init_amd and init_amd
v5: Set X86_FEATURE_RDS on Fam16->17h
Change title to have 'bugs' in it.
v6: Added Reviewed-by

---
 arch/x86/kernel/cpu/amd.c  | 16 ++++++++++++++++
 arch/x86/kernel/cpu/bugs.c | 10 ++++++++--
 2 files changed, 24 insertions(+), 2 deletions(-)

arch/x86/kernel/cpu/amd.c +16 -0

index 12bc0a1139da..6d6a03aa1870 100644
@@ -10,6 +10,7 @@
 #include <asm/processor.h>
 #include <asm/apic.h>
 #include <asm/cpu.h>
+#include <asm/nospec-branch.h>
 #include <asm/smp.h>
 #include <asm/pci-direct.h>
 #include <asm/delay.h>

@@ -673,6 +674,9 @@ static void early_init_amd(struct cpuinfo_x86 *c)
 		set_cpu_bug(c, X86_BUG_AMD_E400);
 
 	early_detect_mem_encrypt(c);
+
+	if (c->x86 >= 0x15 && c->x86 <= 0x17)
+		set_cpu_cap(c, X86_FEATURE_RDS);
 }
 
 static void init_amd_k8(struct cpuinfo_x86 *c)

@@ -787,6 +791,8 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
 			wrmsrl_safe(MSR_F15H_IC_CFG, value);
 		}
 	}
+	if (cpu_has(c, X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
+		msr_set_bit(MSR_AMD64_LS_CFG, 54);
 }
 
 static void init_amd_zn(struct cpuinfo_x86 *c)

@@ -797,6 +803,15 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
 	 */
 	if (c->x86_model <= 1 && c->x86_stepping <= 1)
 		set_cpu_cap(c, X86_FEATURE_CPB);
+
+	if (cpu_has(c, X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
+		msr_set_bit(MSR_AMD64_LS_CFG, 10);
+}
+
+static void init_amd_jg(struct cpuinfo_x86 *c)
+{
+	if (cpu_has(c, X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
+		msr_set_bit(MSR_AMD64_LS_CFG, 33);
 }
 
 static void init_amd(struct cpuinfo_x86 *c)

@@ -827,6 +842,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	case 0x10: init_amd_gh(c); break;
 	case 0x12: init_amd_ln(c); break;
 	case 0x15: init_amd_bd(c); break;
+	case 0x16: init_amd_jg(c); break;
 	case 0x17: init_amd_zn(c); break;
 	}

arch/x86/kernel/cpu/bugs.c +8 -2

index e7338b04770f..191293e18676 100644
@@ -411,7 +411,7 @@ static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 
 	/*
 	 * On Intel it is exposed in CPUID as Reduced Data Speculation
-	 * bit.
+	 * bit. On AMD it is via an MSR, but only on certain families.
 	 */
 	if (!boot_cpu_has(X86_FEATURE_RDS))
 		return SPEC_STORE_BYPASS_CMD_NONE;

@@ -453,6 +453,11 @@ static void __init ssb_select_mitigation(void)
 
 	switch (cmd) {
 	case SPEC_STORE_BYPASS_CMD_AUTO:
+		/*
+		 * AMD platforms by default don't need SSB mitigation.
+		 */
+		if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+			break;
 	case SPEC_STORE_BYPASS_CMD_ON:
 		mode = SPEC_STORE_BYPASS_DISABLE;
 		break;

@@ -472,7 +477,8 @@ static void __init ssb_select_mitigation(void)
 	if (mode != SPEC_STORE_BYPASS_NONE) {
 		setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 		/*
-		 * Intel uses the SPEC CTRL MSR Bit(2) for this.
+		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
+		 * a completely different MSR.
 		 */
 		if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
 			x86_spec_ctrl_base |= SPEC_CTRL_RDS;

Signature · 1 line

2.14.3