Support for Trenz TE0820 on Sundance EMC2-DP-V2
Subsystems (2)
v2 cover Support for Trenz TE0820 on Sundance EMC2-DP-V2
I updated the patch according to the review of Michal Simek. I understand the concern about the maintenance of the support, so I added people from Sundance and Trenz to this patch serie.
If any one of you wants to take over the integration of the patch, feel free to do so.
Changes in v2:
- Renamed a lot from Xilinx ZynqMP to Trenz
- The device tree for the TE0820 is now a DTSI file included by a carrier board+SOM DTS file
Vladimir Svoboda (1):
arm: Add support for Trenz TE0820 on Sundance EMC2-DP-V2
arch/arm/dts/Makefile | 1 + .../sundance-emc2-dp-v2-rev1-te0820-rev2.dts | 19 + arch/arm/dts/trenz-te0820-rev2.dtsi | 213 ++++++ .../zynqmp/trenz-te0820-rev2/psu_init_gpl.c | 623 ++++++++++++++++++ ...ance_emc2-dp-v2_rev1_te0820_rev2_defconfig | 105 +++ include/configs/trenz_te0820.h | 49 ++ 6 files changed, 1010 insertions(+) create mode 100644 arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts create mode 100644 arch/arm/dts/trenz-te0820-rev2.dtsi create mode 100644 board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c create mode 100644 configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig create mode 100644 include/configs/trenz_te0820.h
Signature · 1 line
2.17.0
PATCH v2 1/1 arm: Add support for Trenz TE0820 on Sundance EMC2-DP-V2
Add support for Trenz TE0820 revision 2 MPSoC module. The TE0820 is a System-On-Module (SOM).
This has been tested with a Sundance EMC2-DP-V2 Revision 1 carrier board.
The tested variant of the TE0820 is TE0820-02-03EG-1EA.
Signed-off-by Vladimir Svoboda <[email protected]>
---
Changes in v2:
- Renamed a lot from Xilinx ZynqMP to Trenz
- The device tree for the TE0820 is now a DTSI file included by a carrier board+SOM DTS file
arch/arm/dts/Makefile | 1 + .../sundance-emc2-dp-v2-rev1-te0820-rev2.dts | 19 + arch/arm/dts/trenz-te0820-rev2.dtsi | 213 ++++++ .../zynqmp/trenz-te0820-rev2/psu_init_gpl.c | 623 ++++++++++++++++++ ...ance_emc2-dp-v2_rev1_te0820_rev2_defconfig | 105 +++ include/configs/trenz_te0820.h | 49 ++ 6 files changed, 1010 insertions(+) create mode 100644 arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts create mode 100644 arch/arm/dts/trenz-te0820-rev2.dtsi create mode 100644 board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c create mode 100644 configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig create mode 100644 include/configs/trenz_te0820.h
arch/arm/dts/Makefile +1 -0
@@ -146,6 +146,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zturn.dtb \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ + sundance-emc2-dp-v2-rev1-te0820-rev2.dtb \ zynqmp-mini-emmc.dtb \ zynqmp-mini-nand.dtb \ zynqmp-zcu100-revC.dtb \
arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts new file +19 -0
@@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Sundance EMC2-DP-V2 Rev1 carrier board with Trenz TE0820 Rev2 + * SOM + * + * (C) Copyright 2018, HIPPEROS. + * + * Vladimir Svoboda <[email protected]> + */ + +/dts-v1/; + +#include "trenz-te0820-rev2.dtsi" + +/ { + model = "Sundance EMC2-DP-V2 Rev1 Trenz TE0820 Rev2"; + compatible = "trenz,zynqmp-te0820-rev2", "trenz,zynqmp-te0820", + "trenz,zynqmp"; +};
arch/arm/dts/trenz-te0820-rev2.dtsi new file +213 -0
213 lines not on this page · raw message
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +623 -0
623 lines not on this page · raw message
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +105 -0
105 lines not on this page · raw message
include/configs/trenz_te0820.h new file +49 -0
49 lines not on this page · raw message
Signature · 1 line
2.17.0
PATCH v2 1/1 arm: Add support for Trenz TE0820 on Sundance EMC2-DP-V2
Quoted 46 lines · Vladimir Svoboda
Add support for Trenz TE0820 revision 2 MPSoC module. The TE0820 is a System-On-Module (SOM).
This has been tested with a Sundance EMC2-DP-V2 Revision 1 carrier board.The tested variant of the TE0820 is TE0820-02-03EG-1EA.
Signed-off-by Vladimir Svoboda <[email protected]>---
Changes in v2:
- Renamed a lot from Xilinx ZynqMP to Trenz
- The device tree for the TE0820 is now a DTSI file included by a carrier board+SOM DTS filearch/arm/dts/Makefile | 1 + .../sundance-emc2-dp-v2-rev1-te0820-rev2.dts | 19 + arch/arm/dts/trenz-te0820-rev2.dtsi | 213 ++++++ .../zynqmp/trenz-te0820-rev2/psu_init_gpl.c | 623 ++++++++++++++++++ ...ance_emc2-dp-v2_rev1_te0820_rev2_defconfig | 105 +++ include/configs/trenz_te0820.h | 49 ++ 6 files changed, 1010 insertions(+) create mode 100644 arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts create mode 100644 arch/arm/dts/trenz-te0820-rev2.dtsi create mode 100644 board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c create mode 100644 configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig create mode 100644 include/configs/trenz_te0820.harch/arm/dts/Makefile +1
-0@@ -146,6 +146,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zturn.dtb \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ + sundance-emc2-dp-v2-rev1-te0820-rev2.dtb \ zynqmp-mini-emmc.dtb \ zynqmp-mini-nand.dtb \ zynqmp-zcu100-revC.dtb \arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts new file +0
-0
arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts line 3
Quoted 3 lines
arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts new file +3
-0@@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Sundance EMC2-DP-V2 Rev1 carrier board with Trenz TE0820 Rev2
NIT: remove file and you will fit to 80 chars.
Quoted 5 lines
arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts new file +5
-0+ * SOM + * + * (C) Copyright 2018, HIPPEROS. + * + * Vladimir Svoboda <[email protected]>
arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts line 18
Quoted 10 lines
arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts new file +10
-0+ */ + +/dts-v1/; + +#include "trenz-te0820-rev2.dtsi" + +/ { + model = "Sundance EMC2-DP-V2 Rev1 Trenz TE0820 Rev2"; + compatible = "trenz,zynqmp-te0820-rev2", "trenz,zynqmp-te0820", + "trenz,zynqmp";
This is definitely not enough. This is carrier board which should contain all components which are only on this board. It means a lot of things from SOM below should be moved here.
Also compatible string should contains sundance and record it in vendor-prefix in the linux kernel.
These prefixes needs to be at least in linux-next to be able to apply these patches.
I would even like to hear Rob's opinion on these SoM division.
Quoted 15 lines
arch/arm/dts/sundance-emc2-dp-v2-rev1-te0820-rev2.dts new file +1
-0+};arch/arm/dts/trenz-te0820-rev2.dtsi new file +8
-0@@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Trenz TE0820 Rev2 + * + * (C) Copyright 2018, HIPPEROS. + * + * Vladimir Svoboda <[email protected]> + */
arch/arm/dts/trenz-te0820-rev2.dtsi line 18
Quoted 10 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +10
-0+ +/dts-v1/; + +/include/ "zynqmp.dtsi" +/include/ "zynqmp-clk-ccf.dtsi" + +/ { + model = "Trenz TE0820 Rev2"; + compatible = "trenz,zynqmp-te0820-rev2", "trenz,zynqmp-te0820", + "trenz,zynqmp";
you can keep xlnx,zynqmp here too.
arch/arm/dts/trenz-te0820-rev2.dtsi line 26
Quoted 8 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +8
-0+ + aliases { + ethernet0 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1;
Don't know this module but if there is no hardwired MIOs for these IPs then they should be in sundance dts not here.
arch/arm/dts/trenz-te0820-rev2.dtsi line 27
Quoted 1 line
arch/arm/dts/trenz-te0820-rev2.dtsi new file +1
-0+ serial2 = &dcc;
If jtag is on trenz board you can keep this here.
arch/arm/dts/trenz-te0820-rev2.dtsi line 33
Quoted 6 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +6
-0+ }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + };
sundance.
arch/arm/dts/trenz-te0820-rev2.dtsi line 38
Quoted 5 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +5
-0+ + memory at 0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + };
This memory is on this module that's why it needs to be here.
arch/arm/dts/trenz-te0820-rev2.dtsi line 43
Quoted 5 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +5
-0+}; + +&can1 { + status = "okay"; +};
I would put this to sundance if there is physical hw for can.
Quoted 26 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +26
-0+ +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 {
arch/arm/dts/trenz-te0820-rev2.dtsi line 79
Quoted 10 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +10
-0+ status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +};
you can keep these here.
arch/arm/dts/trenz-te0820-rev2.dtsi line 91
Quoted 12 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +12
-0+ +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy at 21 { + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; + ethernet_phy0: ethernet-phy at 0 {
This is completely bogus. Do you have there 1 phy or two phys? It should be phy at 1.
arch/arm/dts/trenz-te0820-rev2.dtsi line 96
Quoted 5 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +5
-0+ compatible = "marvell,88e1510"; + device_type = "ethernet-phy"; + reg = <1>; + }; +};
This is not on SOM.
arch/arm/dts/trenz-te0820-rev2.dtsi line 104
Quoted 8 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +8
-0+ +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +};
You can keep these two here.
arch/arm/dts/trenz-te0820-rev2.dtsi line 114
Quoted 10 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +10
-0+ +&i2c0 { + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +};
Probably on sundance unless there are dedicated pins where it is exactly said pins XX/YY have to be i2c.
arch/arm/dts/trenz-te0820-rev2.dtsi line 118
Quoted 4 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +4
-0+ +&pcie { + status = "okay"; +};
As above.
arch/arm/dts/trenz-te0820-rev2.dtsi line 130
Quoted 12 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +12
-0+ +&qspi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + flash0: flash at 0 { + compatible = "n25q256a"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + }; +};
This is on SOM that's why this is fine.
arch/arm/dts/trenz-te0820-rev2.dtsi line 134
Quoted 4 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +4
-0+ +&rtc { + status = "okay"; +};
this is ok.
arch/arm/dts/trenz-te0820-rev2.dtsi line 142
Quoted 8 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +8
-0+ +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; + disable-wp; +};
Again if no hardwired in spec then sundance.
arch/arm/dts/trenz-te0820-rev2.dtsi line 146
Quoted 4 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +4
-0+ +&serdes { + status = "okay"; +};
in SOM is fine.
Quoted 12 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +12
-0+ +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay";
arch/arm/dts/trenz-te0820-rev2.dtsi line 168
Quoted 10 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +10
-0+}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + maximum-speed = "high-speed"; + /delete-property/phy-names; + /delete-property/phys; + /delete-property/snps,usb3_lpm_capable; +};
The same for all of these above.
Quoted 6 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +6
-0+ +&watchdog0 { + status = "okay"; +}; + +&xilinx_ams {
arch/arm/dts/trenz-te0820-rev2.dtsi line 184
Quoted 10 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +10
-0+ status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +};
These are internal one that's why fine.
Quoted 19 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +19
-0+ +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dp_sub { + status = "okay"; + xlnx,vid-clk-pl; +}; + +&xlnx_dp_snd_pcm0 { + status = "okay"; +}; + +&xlnx_dp_snd_pcm1 { + status = "okay"; +}; + +&xlnx_dp_snd_card {
arch/arm/dts/trenz-te0820-rev2.dtsi line 213
Quoted 10 lines
arch/arm/dts/trenz-te0820-rev2.dtsi new file +10
-0+ status = "okay"; +}; + +&xlnx_dp_snd_codec0 { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +};
I can't see DP on SOM that's why if you have there DP then to sundance.
Quoted 482 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +476
-0@@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* (c) Copyright 2015 Xilinx, Inc. All rights reserved. +*/ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data (void ) +{ +psu_mask_write (0xFF5E0034 ,0xFE7FEDEFU ,0x7E60EC6CU ); +psu_mask_write (0xFF5E0030 ,0x00717F00U ,0x00013000U ); +psu_mask_write (0xFF5E0030 ,0x00000008U ,0x00000008U ); +psu_mask_write (0xFF5E0030 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFF5E0030 ,0x00000001U ,0x00000000U ); + +mask_poll (0xFF5E0040 ,0x00000002U ); +psu_mask_write (0xFF5E0030 ,0x00000008U ,0x00000000U ); +psu_mask_write (0xFF5E0048 ,0x00003F00U ,0x00000200U ); +psu_mask_write (0xFF5E0024 ,0xFE7FEDEFU ,0x7E4B0C82U ); +psu_mask_write (0xFF5E0020 ,0x00717F00U ,0x00015A00U ); +psu_mask_write (0xFF5E0020 ,0x00000008U ,0x00000008U ); +psu_mask_write (0xFF5E0020 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFF5E0020 ,0x00000001U ,0x00000000U ); + +mask_poll (0xFF5E0040 ,0x00000001U ); +psu_mask_write (0xFF5E0020 ,0x00000008U ,0x00000000U ); +psu_mask_write (0xFF5E0044 ,0x00003F00U ,0x00000300U ); +psu_mask_write (0xFD1A0024 ,0xFE7FEDEFU ,0x7E4B0C62U ); +psu_mask_write (0xFD1A0020 ,0x00717F00U ,0x00014800U ); +psu_mask_write (0xFD1A0020 ,0x00000008U ,0x00000008U ); +psu_mask_write (0xFD1A0020 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD1A0020 ,0x00000001U ,0x00000000U ); + +mask_poll (0xFD1A0044 ,0x00000001U ); +psu_mask_write (0xFD1A0020 ,0x00000008U ,0x00000000U ); +psu_mask_write (0xFD1A0048 ,0x00003F00U ,0x00000300U ); +psu_mask_write (0xFD1A0030 ,0xFE7FEDEFU ,0x7E4B0C62U ); +psu_mask_write (0xFD1A002C ,0x00717F00U ,0x00014800U ); +psu_mask_write (0xFD1A002C ,0x00000008U ,0x00000008U ); +psu_mask_write (0xFD1A002C ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD1A002C ,0x00000001U ,0x00000000U ); + +mask_poll (0xFD1A0044 ,0x00000002U ); +psu_mask_write (0xFD1A002C ,0x00000008U ,0x00000000U ); +psu_mask_write (0xFD1A004C ,0x00003F00U ,0x00000300U ); +psu_mask_write (0xFD1A003C ,0xFE7FEDEFU ,0x7E4B0C62U ); +psu_mask_write (0xFD1A0038 ,0x00717F00U ,0x00013F00U ); +psu_mask_write (0xFD1A0038 ,0x00000008U ,0x00000008U ); +psu_mask_write (0xFD1A0038 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD1A0038 ,0x00000001U ,0x00000000U ); + +mask_poll (0xFD1A0044 ,0x00000004U ); +psu_mask_write (0xFD1A0038 ,0x00000008U ,0x00000000U ); +psu_mask_write (0xFD1A0050 ,0x00003F00U ,0x00000200U ); + +return 1 ; +} + +static unsigned long psu_clock_init_data (void ) +{ +psu_mask_write (0xFF5E005C ,0x063F3F07U ,0x06010C00U ); +psu_mask_write (0xFF5E0100 ,0x013F3F07U ,0x01010600U ); +psu_mask_write (0xFF5E0060 ,0x023F3F07U ,0x02010600U ); +psu_mask_write (0xFF5E0068 ,0x013F3F07U ,0x01010500U ); +psu_mask_write (0xFF5E006C ,0x013F3F07U ,0x01010402U ); +psu_mask_write (0xFF5E0070 ,0x013F3F07U ,0x01010402U ); +psu_mask_write (0xFF18030C ,0x00020003U ,0x00000000U ); +psu_mask_write (0xFF5E0074 ,0x013F3F07U ,0x01010F00U ); +psu_mask_write (0xFF5E0120 ,0x013F3F07U ,0x01010F00U ); +psu_mask_write (0xFF5E0090 ,0x01003F07U ,0x01000302U ); +psu_mask_write (0xFF5E009C ,0x01003F07U ,0x01000300U ); +psu_mask_write (0xFF5E00A4 ,0x01003F07U ,0x01000800U ); +psu_mask_write (0xFF5E00A8 ,0x01003F07U ,0x01000302U ); +psu_mask_write (0xFF5E00AC ,0x01003F07U ,0x01000F02U ); +psu_mask_write (0xFF5E00B0 ,0x01003F07U ,0x01000602U ); +psu_mask_write (0xFF5E00B8 ,0x01003F07U ,0x01000302U ); +psu_mask_write (0xFF5E00C0 ,0x013F3F07U ,0x01010802U ); +psu_mask_write (0xFF5E0108 ,0x013F3F07U ,0x01011E02U ); +psu_mask_write (0xFF5E0104 ,0x00000007U ,0x00000000U ); +psu_mask_write (0xFF5E0128 ,0x01003F07U ,0x01000104U ); +psu_mask_write (0xFD1A0060 ,0x03003F07U ,0x03000100U ); +psu_mask_write (0xFD1A0068 ,0x01003F07U ,0x01000200U ); +psu_mask_write (0xFD1A0080 ,0x00003F07U ,0x00000200U ); +psu_mask_write (0xFD1A0084 ,0x07003F07U ,0x07000203U ); +psu_mask_write (0xFD1A00B8 ,0x01003F07U ,0x01000203U ); +psu_mask_write (0xFD1A00BC ,0x01003F07U ,0x01000203U ); +psu_mask_write (0xFD1A00C0 ,0x01003F07U ,0x01000202U ); +psu_mask_write (0xFD1A00C4 ,0x01003F07U ,0x01000502U ); +psu_mask_write (0xFD1A00F8 ,0x00003F07U ,0x00000200U ); +psu_mask_write (0xFF180380 ,0x000000FFU ,0x00000000U ); +psu_mask_write (0xFD610100 ,0x00000001U ,0x00000000U ); +psu_mask_write (0xFF180300 ,0x00000001U ,0x00000000U ); +psu_mask_write (0xFF410050 ,0x00000001U ,0x00000000U ); + +return 1 ; +} + +static unsigned long psu_ddr_init_data (void ) +{ +psu_mask_write (0xFD1A0108 ,0x00000008U ,0x00000008U ); +psu_mask_write (0xFD070000 ,0xE30FBE3DU ,0x81041010U ); +psu_mask_write (0xFD070010 ,0x8000F03FU ,0x00000030U ); +psu_mask_write (0xFD070020 ,0x000003F3U ,0x00000300U ); +psu_mask_write (0xFD070024 ,0xFFFFFFFFU ,0x00800000U ); +psu_mask_write (0xFD070030 ,0x0000007FU ,0x00000000U ); +psu_mask_write (0xFD070034 ,0x00FFFF1FU ,0x00409410U ); +psu_mask_write (0xFD070050 ,0x00F1F1F4U ,0x00210000U ); +psu_mask_write (0xFD070054 ,0x0FFF0FFFU ,0x00000000U ); +psu_mask_write (0xFD070060 ,0x00000073U ,0x00000001U ); +psu_mask_write (0xFD070064 ,0x0FFF83FFU ,0x0092809DU ); +psu_mask_write (0xFD070070 ,0x00000017U ,0x00000010U ); +psu_mask_write (0xFD070074 ,0x00000003U ,0x00000000U ); +psu_mask_write (0xFD0700C4 ,0x3F000391U ,0x10000200U ); +psu_mask_write (0xFD0700C8 ,0x01FF1F3FU ,0x0048051FU ); +psu_mask_write (0xFD0700D0 ,0xC3FF0FFFU ,0x00020126U ); +psu_mask_write (0xFD0700D4 ,0x01FF7F0FU ,0x00020000U ); +psu_mask_write (0xFD0700D8 ,0x0000FF0FU ,0x00002705U ); +psu_mask_write (0xFD0700DC ,0xFFFFFFFFU ,0x0B340301U ); +psu_mask_write (0xFD0700E0 ,0xFFFFFFFFU ,0x00180200U ); +psu_mask_write (0xFD0700E4 ,0x00FF03FFU ,0x00210004U ); +psu_mask_write (0xFD0700E8 ,0xFFFFFFFFU ,0x000806C0U ); +psu_mask_write (0xFD0700EC ,0xFFFF0000U ,0x08190000U ); +psu_mask_write (0xFD0700F0 ,0x0000003FU ,0x00000010U ); +psu_mask_write (0xFD0700F4 ,0x00000FFFU ,0x0000066FU ); +psu_mask_write (0xFD070100 ,0x7F3F7F3FU ,0x11122813U ); +psu_mask_write (0xFD070104 ,0x001F1F7FU ,0x0004051CU ); +psu_mask_write (0xFD070108 ,0x3F3F3F3FU ,0x0608070DU ); +psu_mask_write (0xFD07010C ,0x3FF3F3FFU ,0x0050400CU ); +psu_mask_write (0xFD070110 ,0x1F0F0F1FU ,0x08030409U ); +psu_mask_write (0xFD070114 ,0x0F0F3F1FU ,0x07070403U ); +psu_mask_write (0xFD070118 ,0x0F0F000FU ,0x01010004U ); +psu_mask_write (0xFD07011C ,0x00000F0FU ,0x00000707U ); +psu_mask_write (0xFD070120 ,0x7F7F7F7FU ,0x04040D07U ); +psu_mask_write (0xFD070124 ,0x40070F3FU ,0x0002040AU ); +psu_mask_write (0xFD07012C ,0x7F1F031FU ,0x4708010EU ); +psu_mask_write (0xFD070130 ,0x00030F1FU ,0x00020608U ); +psu_mask_write (0xFD070180 ,0xF7FF03FFU ,0x81000040U ); +psu_mask_write (0xFD070184 ,0x3FFFFFFFU ,0x0201C9C3U ); +psu_mask_write (0xFD070190 ,0x1FBFBF3FU ,0x048C8209U ); +psu_mask_write (0xFD070194 ,0xF31F0F0FU ,0x00030304U ); +psu_mask_write (0xFD070198 ,0x0FF1F1F1U ,0x07000101U ); +psu_mask_write (0xFD07019C ,0x000000F1U ,0x00000021U ); +psu_mask_write (0xFD0701A0 ,0xC3FF03FFU ,0x00400003U ); +psu_mask_write (0xFD0701A4 ,0x00FF00FFU ,0x00A9007EU ); +psu_mask_write (0xFD0701B0 ,0x00000007U ,0x00000000U ); +psu_mask_write (0xFD0701B4 ,0x00003F3FU ,0x00000A04U ); +psu_mask_write (0xFD0701C0 ,0x00000007U ,0x00000001U ); +psu_mask_write (0xFD070200 ,0x0000001FU ,0x0000001FU ); +psu_mask_write (0xFD070204 ,0x001F1F1FU ,0x001F0808U ); +psu_mask_write (0xFD070208 ,0x0F0F0F0FU ,0x01010101U ); +psu_mask_write (0xFD07020C ,0x0F0F0F0FU ,0x0F010101U ); +psu_mask_write (0xFD070210 ,0x00000F0FU ,0x00000F0FU ); +psu_mask_write (0xFD070214 ,0x0F0F0F0FU ,0x060F0606U ); +psu_mask_write (0xFD070218 ,0x8F0F0F0FU ,0x0F060606U ); +psu_mask_write (0xFD07021C ,0x00000F0FU ,0x00000F0FU ); +psu_mask_write (0xFD070220 ,0x00001F1FU ,0x00001F00U ); +psu_mask_write (0xFD070224 ,0x0F0F0F0FU ,0x06060606U ); +psu_mask_write (0xFD070228 ,0x0F0F0F0FU ,0x06060606U ); +psu_mask_write (0xFD07022C ,0x0000000FU ,0x00000006U ); +psu_mask_write (0xFD070240 ,0x0F1F0F7CU ,0x0600060CU ); +psu_mask_write (0xFD070244 ,0x00003333U ,0x00000001U ); +psu_mask_write (0xFD070250 ,0x7FFF3F07U ,0x01002001U ); +psu_mask_write (0xFD070264 ,0xFF00FFFFU ,0x08000040U ); +psu_mask_write (0xFD07026C ,0xFF00FFFFU ,0x08000040U ); +psu_mask_write (0xFD070280 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD070284 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD070288 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD07028C ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD070290 ,0x0000FFFFU ,0x00000000U ); +psu_mask_write (0xFD070294 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD070300 ,0x00000011U ,0x00000001U ); +psu_mask_write (0xFD07030C ,0x80000033U ,0x00000000U ); +psu_mask_write (0xFD070320 ,0x00000001U ,0x00000000U ); +psu_mask_write (0xFD070400 ,0x00000111U ,0x00000101U ); +psu_mask_write (0xFD070404 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD070408 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD070490 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD070494 ,0x0033000FU ,0x0020000BU ); +psu_mask_write (0xFD070498 ,0x07FF07FFU ,0x00000000U ); +psu_mask_write (0xFD0704B4 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD0704B8 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD070540 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD070544 ,0x03330F0FU ,0x02000B03U ); +psu_mask_write (0xFD070548 ,0x07FF07FFU ,0x00000000U ); +psu_mask_write (0xFD070564 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD070568 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD0705F0 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD0705F4 ,0x03330F0FU ,0x02000B03U ); +psu_mask_write (0xFD0705F8 ,0x07FF07FFU ,0x00000000U ); +psu_mask_write (0xFD070614 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD070618 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD0706A0 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD0706A4 ,0x0033000FU ,0x00100003U ); +psu_mask_write (0xFD0706A8 ,0x07FF07FFU ,0x0000004FU ); +psu_mask_write (0xFD0706AC ,0x0033000FU ,0x00100003U ); +psu_mask_write (0xFD0706B0 ,0x000007FFU ,0x0000004FU ); +psu_mask_write (0xFD0706C4 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD0706C8 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD070750 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD070754 ,0x0033000FU ,0x00100003U ); +psu_mask_write (0xFD070758 ,0x07FF07FFU ,0x0000004FU ); +psu_mask_write (0xFD07075C ,0x0033000FU ,0x00100003U ); +psu_mask_write (0xFD070760 ,0x000007FFU ,0x0000004FU ); +psu_mask_write (0xFD070774 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD070778 ,0x000073FFU ,0x0000200FU ); +psu_mask_write (0xFD070800 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFD070804 ,0x0033000FU ,0x00100003U ); +psu_mask_write (0xFD070808 ,0x07FF07FFU ,0x0000004FU ); +psu_mask_write (0xFD07080C ,0x0033000FU ,0x00100003U ); +psu_mask_write (0xFD070810 ,0x000007FFU ,0x0000004FU ); +psu_mask_write (0xFD070F04 ,0x000001FFU ,0x00000000U ); +psu_mask_write (0xFD070F08 ,0x000000FFU ,0x00000000U ); +psu_mask_write (0xFD070F0C ,0x000001FFU ,0x00000010U ); +psu_mask_write (0xFD070F10 ,0x000000FFU ,0x0000000FU ); +psu_mask_write (0xFD072190 ,0x1FBFBF3FU ,0x07828002U ); +psu_mask_write (0xFD1A0108 ,0x0000000CU ,0x00000000U ); +psu_mask_write (0xFD080010 ,0xFFFFFFFFU ,0x07001E00U ); +psu_mask_write (0xFD080018 ,0xFFFFFFFFU ,0x00F12098U ); +psu_mask_write (0xFD08001C ,0xFFFFFFFFU ,0x55AA5480U ); +psu_mask_write (0xFD080024 ,0xFFFFFFFFU ,0x010100F4U ); +psu_mask_write (0xFD080040 ,0xFFFFFFFFU ,0x2C096010U ); +psu_mask_write (0xFD080044 ,0xFFFFFFFFU ,0xA9801460U ); +psu_mask_write (0xFD080068 ,0xFFFFFFFFU ,0x000E0000U ); +psu_mask_write (0xFD080090 ,0xFFFFFFFFU ,0x02A041A1U ); +psu_mask_write (0xFD0800C0 ,0xFFFFFFFFU ,0x000000D3U ); +psu_mask_write (0xFD080100 ,0xFFFFFFFFU ,0x0800040CU ); +psu_mask_write (0xFD080110 ,0xFFFFFFFFU ,0x0826100AU ); +psu_mask_write (0xFD080114 ,0xFFFFFFFFU ,0x28240008U ); +psu_mask_write (0xFD080118 ,0xFFFFFFFFU ,0x00080300U ); +psu_mask_write (0xFD08011C ,0xFFFFFFFFU ,0x83000800U ); +psu_mask_write (0xFD080120 ,0xFFFFFFFFU ,0x01382B08U ); +psu_mask_write (0xFD080124 ,0xFFFFFFFFU ,0x00371009U ); +psu_mask_write (0xFD080128 ,0xFFFFFFFFU ,0x00000C10U ); +psu_mask_write (0xFD080140 ,0xFFFFFFFFU ,0x08400020U ); +psu_mask_write (0xFD080144 ,0xFFFFFFFFU ,0x00000C80U ); +psu_mask_write (0xFD080150 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD080154 ,0xFFFFFFFFU ,0x00000300U ); +psu_mask_write (0xFD080180 ,0xFFFFFFFFU ,0x00000A34U ); +psu_mask_write (0xFD080184 ,0xFFFFFFFFU ,0x00000301U ); +psu_mask_write (0xFD080188 ,0xFFFFFFFFU ,0x00000018U ); +psu_mask_write (0xFD08018C ,0xFFFFFFFFU ,0x00000200U ); +psu_mask_write (0xFD080190 ,0xFFFFFFFFU ,0x00000008U ); +psu_mask_write (0xFD080194 ,0xFFFFFFFFU ,0x000006C0U ); +psu_mask_write (0xFD080198 ,0xFFFFFFFFU ,0x00000819U ); +psu_mask_write (0xFD0801AC ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD0801B0 ,0xFFFFFFFFU ,0x0000004DU ); +psu_mask_write (0xFD0801B4 ,0xFFFFFFFFU ,0x00000008U ); +psu_mask_write (0xFD0801B8 ,0xFFFFFFFFU ,0x0000004DU ); +psu_mask_write (0xFD0801D8 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD080200 ,0xFFFFFFFFU ,0x800091C7U ); +psu_mask_write (0xFD080204 ,0xFFFFFFFFU ,0x00010236U ); +psu_mask_write (0xFD080240 ,0xFFFFFFFFU ,0x00141054U ); +psu_mask_write (0xFD080250 ,0xFFFFFFFFU ,0x00088000U ); +psu_mask_write (0xFD080414 ,0xFFFFFFFFU ,0x12340400U ); +psu_mask_write (0xFD0804F4 ,0xFFFFFFFFU ,0x00000005U ); +psu_mask_write (0xFD080500 ,0xFFFFFFFFU ,0x30000028U ); +psu_mask_write (0xFD080508 ,0xFFFFFFFFU ,0x0A000000U ); +psu_mask_write (0xFD08050C ,0xFFFFFFFFU ,0x00000009U ); +psu_mask_write (0xFD080510 ,0xFFFFFFFFU ,0x0A000000U ); +psu_mask_write (0xFD080520 ,0xFFFFFFFFU ,0x0300B0CEU ); +psu_mask_write (0xFD080528 ,0xFFFFFFFFU ,0xF9032019U ); +psu_mask_write (0xFD08052C ,0xFFFFFFFFU ,0x07F001E3U ); +psu_mask_write (0xFD080544 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD080548 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD080558 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD08055C ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD080560 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD080564 ,0xFFFFFFFFU ,0x00000000U ); +psu_mask_write (0xFD080680 ,0xFFFFFFFFU ,0x008B0A58U ); +psu_mask_write (0xFD080684 ,0xFFFFFFFFU ,0x000079DDU ); +psu_mask_write (0xFD080694 ,0xFFFFFFFFU ,0x01E10210U ); +psu_mask_write (0xFD080698 ,0xFFFFFFFFU ,0x01E10000U ); +psu_mask_write (0xFD0806A4 ,0xFFFFFFFFU ,0x00087BDBU ); +psu_mask_write (0xFD080700 ,0xFFFFFFFFU ,0x40800604U ); +psu_mask_write (0xFD080710 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080714 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080718 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD080800 ,0xFFFFFFFFU ,0x40800604U ); +psu_mask_write (0xFD080810 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080814 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080818 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD080900 ,0xFFFFFFFFU ,0x40800604U ); +psu_mask_write (0xFD080904 ,0xFFFFFFFFU ,0x00007FFFU ); +psu_mask_write (0xFD080910 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080914 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080918 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD080A00 ,0xFFFFFFFFU ,0x40800604U ); +psu_mask_write (0xFD080A04 ,0xFFFFFFFFU ,0x00007FFFU ); +psu_mask_write (0xFD080A10 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080A14 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080A18 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD080B00 ,0xFFFFFFFFU ,0x40800604U ); +psu_mask_write (0xFD080B04 ,0xFFFFFFFFU ,0x00007F00U ); +psu_mask_write (0xFD080B10 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080B14 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080B18 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD080C00 ,0xFFFFFFFFU ,0x40800604U ); +psu_mask_write (0xFD080C04 ,0xFFFFFFFFU ,0x00007F00U ); +psu_mask_write (0xFD080C10 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080C14 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080C18 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD080D00 ,0xFFFFFFFFU ,0x40800604U ); +psu_mask_write (0xFD080D04 ,0xFFFFFFFFU ,0x00007F00U ); +psu_mask_write (0xFD080D10 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080D14 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080D18 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD080E00 ,0xFFFFFFFFU ,0x40800604U ); +psu_mask_write (0xFD080E04 ,0xFFFFFFFFU ,0x00007F00U ); +psu_mask_write (0xFD080E10 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080E14 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080E18 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD080F00 ,0xFFFFFFFFU ,0x40800624U ); +psu_mask_write (0xFD080F04 ,0xFFFFFFFFU ,0x00007F00U ); +psu_mask_write (0xFD080F10 ,0xFFFFFFFFU ,0x0E00B03CU ); +psu_mask_write (0xFD080F14 ,0xFFFFFFFFU ,0x09094F4FU ); +psu_mask_write (0xFD080F18 ,0xFFFFFFFFU ,0x09092B2BU ); +psu_mask_write (0xFD081400 ,0xFFFFFFFFU ,0x2A019FFEU ); +psu_mask_write (0xFD081404 ,0xFFFFFFFFU ,0x000E0000U ); +psu_mask_write (0xFD08141C ,0xFFFFFFFFU ,0x01264300U ); +psu_mask_write (0xFD08142C ,0xFFFFFFFFU ,0x00041800U ); +psu_mask_write (0xFD081430 ,0xFFFFFFFFU ,0x70800000U ); +psu_mask_write (0xFD081440 ,0xFFFFFFFFU ,0x2A019FFEU ); +psu_mask_write (0xFD081444 ,0xFFFFFFFFU ,0x000E0000U ); +psu_mask_write (0xFD08145C ,0xFFFFFFFFU ,0x01264300U ); +psu_mask_write (0xFD08146C ,0xFFFFFFFFU ,0x00041800U ); +psu_mask_write (0xFD081470 ,0xFFFFFFFFU ,0x70800000U ); +psu_mask_write (0xFD081480 ,0xFFFFFFFFU ,0x2A019FFEU ); +psu_mask_write (0xFD081484 ,0xFFFFFFFFU ,0x000E0000U ); +psu_mask_write (0xFD08149C ,0xFFFFFFFFU ,0x01264300U ); +psu_mask_write (0xFD0814AC ,0xFFFFFFFFU ,0x00041800U ); +psu_mask_write (0xFD0814B0 ,0xFFFFFFFFU ,0x70800000U ); +psu_mask_write (0xFD0814C0 ,0xFFFFFFFFU ,0x2A019FFEU ); +psu_mask_write (0xFD0814C4 ,0xFFFFFFFFU ,0x000E0000U ); +psu_mask_write (0xFD0814DC ,0xFFFFFFFFU ,0x01264300U ); +psu_mask_write (0xFD0814EC ,0xFFFFFFFFU ,0x00041800U ); +psu_mask_write (0xFD0814F0 ,0xFFFFFFFFU ,0x70800000U ); +psu_mask_write (0xFD081500 ,0xFFFFFFFFU ,0x2A019FFEU ); +psu_mask_write (0xFD081504 ,0xFFFFFFFFU ,0x000E0000U ); +psu_mask_write (0xFD08151C ,0xFFFFFFFFU ,0x01264300U ); +psu_mask_write (0xFD08152C ,0xFFFFFFFFU ,0x00041800U ); +psu_mask_write (0xFD081530 ,0xFFFFFFFFU ,0x70800000U ); +psu_mask_write (0xFD0817C4 ,0xFFFFFFFFU ,0x000E0000U ); +psu_mask_write (0xFD0817DC ,0xFFFFFFFFU ,0x012643C4U ); + +return 1 ; +} + +static unsigned long psu_mio_init_data (void ) +{ +psu_mask_write (0xFF180000 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180004 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180008 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF18000C ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180010 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180014 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180018 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF18001C ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180020 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180024 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180028 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF18002C ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180030 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180034 ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF180038 ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF18003C ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF180040 ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF180044 ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF180048 ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF18004C ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF180050 ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF180054 ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF180058 ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF18005C ,0x000000FEU ,0x00000008U ); +psu_mask_write (0xFF180060 ,0x000000FEU ,0x00000000U ); +psu_mask_write (0xFF180064 ,0x000000FEU ,0x00000000U ); +psu_mask_write (0xFF180078 ,0x000000FEU ,0x000000C0U ); +psu_mask_write (0xFF18007C ,0x000000FEU ,0x000000C0U ); +psu_mask_write (0xFF180098 ,0x000000FEU ,0x00000040U ); +psu_mask_write (0xFF18009C ,0x000000FEU ,0x00000040U ); +psu_mask_write (0xFF1800B8 ,0x000000FEU ,0x00000010U ); +psu_mask_write (0xFF1800BC ,0x000000FEU ,0x00000010U ); +psu_mask_write (0xFF1800C0 ,0x000000FEU ,0x00000010U ); +psu_mask_write (0xFF1800C4 ,0x000000FEU ,0x00000010U ); +psu_mask_write (0xFF1800C8 ,0x000000FEU ,0x00000010U ); +psu_mask_write (0xFF1800CC ,0x000000FEU ,0x00000010U ); +psu_mask_write (0xFF1800D0 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800D4 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800D8 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800DC ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800E0 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800E4 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800E8 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800EC ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800F0 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800F4 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800F8 ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF1800FC ,0x000000FEU ,0x00000004U ); +psu_mask_write (0xFF180100 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180104 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180108 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF18010C ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180110 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180114 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180118 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF18011C ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180120 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180124 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180128 ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF18012C ,0x000000FEU ,0x00000002U ); +psu_mask_write (0xFF180130 ,0x000000FEU ,0x000000C0U ); +psu_mask_write (0xFF180134 ,0x000000FEU ,0x000000C0U ); +psu_mask_write (0xFF180204 ,0xC3FFFFFFU ,0x40000000U ); +psu_mask_write (0xFF180208 ,0xFFFFC0C0U ,0x00B00000U ); +psu_mask_write (0xFF18020C ,0x00003FFFU ,0x00000FC0U ); +psu_mask_write (0xFF180138 ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF18013C ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF180140 ,0x03FFFFFFU ,0x00000000U ); +psu_mask_write (0xFF180144 ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF180148 ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF18014C ,0x03FFFFFFU ,0x00000000U ); +psu_mask_write (0xFF180154 ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF180158 ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF18015C ,0x03FFFFFFU ,0x01F00000U ); +psu_mask_write (0xFF180160 ,0x000FFFFFU ,0x000FFFFFU ); +psu_mask_write (0xFF180164 ,0x03FFFFFFU ,0x03FFF03FU ); +psu_mask_write (0xFF180168 ,0x03FFFFFFU ,0x00000000U ); +psu_mask_write (0xFF180170 ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF180174 ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF180178 ,0x03FFFFFFU ,0x00000000U ); +psu_mask_write (0xFF18017C ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF180180 ,0x03FFFFFFU ,0x03FFFFFFU ); +psu_mask_write (0xFF180184 ,0x03FFFFFFU ,0x00000000U ); +psu_mask_write (0xFF180200 ,0x0000000FU ,0x00000000U ); + +return 1 ; +} + +static unsigned long psu_peripherals_init_data (void ) +{ +psu_mask_write (0xFD1A0100 ,0x0000807CU ,0x00000000U ); +psu_mask_write (0xFF5E0238 ,0x001A0000U ,0x00000000U ); +psu_mask_write (0xFF5E023C ,0x0093C018U ,0x00000000U ); +psu_mask_write (0xFF5E0230 ,0x00000008U ,0x00000000U ); +psu_mask_write (0xFF5E0238 ,0x00000001U ,0x00000000U ); +psu_mask_write (0xFF180390 ,0x00000004U ,0x00000000U ); +psu_mask_write (0xFF5E023C ,0x00000540U ,0x00000000U ); +psu_mask_write (0xFF9D0080 ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFF9D007C ,0x00000001U ,0x00000001U ); +psu_mask_write (0xFF5E0238 ,0x00000060U ,0x00000000U ); +psu_mask_write (0xFF180310 ,0x00008001U ,0x00000001U ); +psu_mask_write (0xFF180320 ,0x33803380U ,0x00801280U ); +psu_mask_write (0xFF18031C ,0x00007FFEU ,0x00006450U ); +psu_mask_write (0xFF180358 ,0x00080000U ,0x00080000U ); +psu_mask_write (0xFF18031C ,0x7FFE0000U ,0x64500000U ); +psu_mask_write (0xFF180358 ,0x00000008U ,0x00000008U ); +psu_mask_write (0xFF180324 ,0x000003C0U ,0x00000000U ); +psu_mask_write (0xFF180324 ,0x03C00000U ,0x00000000U ); +psu_mask_write (0xFF5E0238 ,0x00000200U ,0x00000000U ); +psu_mask_write (0xFF5E0238 ,0x00008000U ,0x00000000U ); +psu_mask_write (0xFF5E0238 ,0x00007800U ,0x00000000U ); +psu_mask_write (0xFF5E0238 ,0x00000002U ,0x00000000U ); +psu_mask_write (0xFF000034 ,0x000000FFU ,0x00000006U ); +psu_mask_write (0xFF000018 ,0x0000FFFFU ,0x0000007CU ); +psu_mask_write (0xFF000000 ,0x000001FFU ,0x00000017U ); +psu_mask_write (0xFF000004 ,0x000003FFU ,0x00000020U ); +psu_mask_write (0xFF5E0238 ,0x00040000U ,0x00000000U ); +psu_mask_write (0xFF4B0024 ,0x000000FFU ,0x000000FFU ); +psu_mask_write (0xFFCA5000 ,0x00001FFFU ,0x00000000U ); +psu_mask_write (0xFD5C0060 ,0x000F000FU ,0x00000000U ); +psu_mask_write (0xFFA60040 ,0x80000000U ,0x80000000U ); +psu_mask_write (0xFF260020 ,0xFFFFFFFFU ,0x01FCA051U ); +psu_mask_write (0xFF260000 ,0x00000001U ,0x00000001U ); + +return 1 ; +}
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c line 486
Quoted 10 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +10
-0+ +static unsigned long psu_peripherals_powerdwn_data (void ) +{ +return 1 ; +} + +static unsigned long psu_serdes_init_data (void ) +{ +return 1 ; +}
You don't have any serdes setting. It means above there shouldn't be serdes node, dp, usb3.0 and pcie.
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c line 498
Quoted 12 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +12
-0+ +static unsigned long psu_resetout_init_data (void ) +{ +psu_mask_write (0xFD480064 ,0x00000200U ,0x00000200U ); + +return 1 ; +} + +static unsigned long psu_resetin_init_data (void ) +{ +return 1 ; +}
you can remove these empty functions.
Quoted 4 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +4
-0+ +static unsigned long psu_afi_config (void ) +{ +psu_mask_write (0xFD1A0100 ,0x00001F80U ,0x00000000U );
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c line 512
Quoted 10 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +10
-0+psu_mask_write (0xFF5E023C ,0x00080000U ,0x00000000U ); +psu_mask_write (0xFF419000 ,0x00000300U ,0x00000000U ); + +return 1 ; +} + +static unsigned long psu_ddr_phybringup_data (void ) +{ +unsigned int regval =0 ; +
nit remove empty line.
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c line 514
Quoted 2 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +2
-0+unsigned int pll_retry =10 ; +
nit remove empty line.
Quoted 73 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +73
-0+unsigned int pll_locked =0 ; + +while ((pll_retry >0 ) && (!pll_locked)) { +Xil_Out32 (0xFD080004 ,0x00040010 ); +Xil_Out32 (0xFD080004 ,0x00040011 ); + +while ((Xil_In32 (0xFD080030 ) &0x1 ) !=1 ) + ; + + pll_locked = (Xil_In32 (0xFD080030 ) &0x80000000 ) >>31 ; + pll_locked &= (Xil_In32 (0xFD0807E0 ) &0x10000 ) >>16 ; + pll_locked &= (Xil_In32 (0xFD0809E0 ) &0x10000 ) >>16 ; + pll_retry--; + } +Xil_Out32 (0xFD0800C0 ,Xil_In32 (0xFD0800C0 ) | (pll_retry <<16 )); +Xil_Out32 (0xFD080004U ,0x00040063U ); + +while ((Xil_In32 (0xFD080030U ) &0x0000000FU ) !=0x0000000FU ) + ; + +prog_reg (0xFD080004U ,0x00000001U ,0x00000000U ,0x00000001U ); + +while ((Xil_In32 (0xFD080030U ) &0x000000FFU ) !=0x0000001FU ) + ; + +Xil_Out32 (0xFD0701B0U ,0x00000001U ); +Xil_Out32 (0xFD070320U ,0x00000001U ); +while ((Xil_In32 (0xFD070004U ) &0x0000000FU ) !=0x00000001U ) + ; + +prog_reg (0xFD080014U ,0x00000040U ,0x00000006U ,0x00000001U ); +Xil_Out32 (0xFD080004 ,0x0004FE01 ); + regval =Xil_In32 (0xFD080030 ); +while (regval !=0x80000FFF ) + regval =Xil_In32 (0xFD080030 ); + +Xil_Out32 (0xFD080200U ,0x100091C7U ); +Xil_Out32 (0xFD080018U ,0x00F02300U ); +prog_reg (0xFD08001CU ,0x00000018U ,0x00000003U ,0x00000003U ); +prog_reg (0xFD08142CU ,0x00000030U ,0x00000004U ,0x00000003U ); +prog_reg (0xFD08146CU ,0x00000030U ,0x00000004U ,0x00000003U ); +prog_reg (0xFD0814ACU ,0x00000030U ,0x00000004U ,0x00000003U ); +prog_reg (0xFD0814ECU ,0x00000030U ,0x00000004U ,0x00000003U ); +prog_reg (0xFD08152CU ,0x00000030U ,0x00000004U ,0x00000003U ); + +Xil_Out32 (0xFD080004 ,0x00060001 ); + regval =Xil_In32 (0xFD080030 ); +while ((regval &0x80004001 ) !=0x80004001 ) + regval =Xil_In32 (0xFD080030 ); + +prog_reg (0xFD08001CU ,0x00000018U ,0x00000003U ,0x00000000U ); +prog_reg (0xFD08142CU ,0x00000030U ,0x00000004U ,0x00000000U ); +prog_reg (0xFD08146CU ,0x00000030U ,0x00000004U ,0x00000000U ); +prog_reg (0xFD0814ACU ,0x00000030U ,0x00000004U ,0x00000000U ); +prog_reg (0xFD0814ECU ,0x00000030U ,0x00000004U ,0x00000000U ); +prog_reg (0xFD08152CU ,0x00000030U ,0x00000004U ,0x00000000U ); + +Xil_Out32 (0xFD080200U ,0x800091C7U ); +Xil_Out32 (0xFD080018U ,0x00F14780U ); + +Xil_Out32 (0xFD080004 ,0x0000C001 ); + regval =Xil_In32 (0xFD080030 ); +while ((regval &0x80000C01 ) !=0x80000C01 ) + regval =Xil_In32 (0xFD080030 ); + +Xil_Out32 (0xFD070180U ,0x01000040U ); +Xil_Out32 (0xFD070060U ,0x00000000U ); +prog_reg (0xFD080014U ,0x00000040U ,0x00000006U ,0x00000000U ); + +return 1 ; +} + +static int init_serdes (void )
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c line 597
Quoted 10 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +10
-0+{ +int status =1 ; + + status &=psu_resetin_init_data (); + + status &=psu_serdes_init_data (); + status &=psu_resetout_init_data (); + +return status; +}
Not sure what's that one write does without looking at regs but check if you can remove this function completely.
Quoted 32 lines
board/xilinx/zynqmp/trenz-te0820-rev2/psu_init_gpl.c new file +26
-0+ +static void init_peripheral (void ) +{ +psu_mask_write (0xFD5F0018 ,0x8000001FU ,0x8000001FU ); +} + +int psu_init (void ) +{ +int status =1 ; + + status &=psu_mio_init_data (); + status &=psu_pll_init_data (); + status &=psu_clock_init_data (); + status &=psu_ddr_init_data (); + status &=psu_ddr_phybringup_data (); + status &=psu_peripherals_init_data (); + status &=init_serdes (); +init_peripheral (); + + status &=psu_peripherals_powerdwn_data (); + status &=psu_afi_config (); + +if (status ==0 ) +return 1 ; +return 0 ; +}configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +0
-0
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig line 2
Quoted 2 lines
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +2
-0@@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="trenz_te0820"
look below.
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig line 7
Quoted 5 lines
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +5
-0+CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Sundance EMC2-DP-V2 Rev1 Trenz TE0820 Rev2"
you don't need to use this string - enable cpuinfo and it will be taken from DT directly.
Quoted 35 lines
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +35
-0+CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="sundance-emc2-dp-v2-rev1-te0820-rev2" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig line 52
Quoted 10 lines
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +10
-0+CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y
Did you test sata without serdes?
Quoted 10 lines
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +10
-0+CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C0=y +CONFIG_ZYNQ_I2C1=y +CONFIG_MISC=y
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig line 72
Quoted 10 lines
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +10
-0+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y
On Xilinx boards I am enabling all these flashes because Xilinx has these boards with different qspi vendors for testing. You should have this only flash vendor which is used on the SoM or better compatible SoMs.
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig line 79
Quoted 7 lines
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +7
-0+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y
the same here.
include/configs/trenz_te0820.h
Quoted 31 lines
configs/sundance_emc2-dp-v2_rev1_te0820_rev2_defconfig new file +26
-0+CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_OF_LIBFDT=yinclude/configs/trenz_te0820.h new file +0
-0
I would use sundance instead of trenz because below is nothing SoM specific but only carrier board specific.
include/configs/trenz_te0820.h line 2
Quoted 3 lines
include/configs/trenz_te0820.h new file +2
-0@@ -0,0 +1,49 @@ +/* +* Configuration for Xilinx ZynqMP TE0820
Trenz? Or better Sundance with Trenz.
include/configs/trenz_te0820.h line 15
Quoted 13 lines
include/configs/trenz_te0820.h new file +13
-0+* +* Inspired from xilinx_zynqmp_zcu102.h +* +* (C) Copyright 2018, HIPPEROS. +* Vladimir Svoboda <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __CONFIG_ZYNQMP_TE0820_H +#define __CONFIG_ZYNQMP_TE0820_H + +#define CONFIG_ZYNQ_SDHCI1
if you don't have 2 SDs you can remove this macro.
Quoted 14 lines
include/configs/trenz_te0820.h new file +14
-0+#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 18 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ + {1, {I2C_NULL_HOP} }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
include/configs/trenz_te0820.h line 39
Quoted 10 lines
include/configs/trenz_te0820.h new file +10
-0+ {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_PCA953X
You didn't list any i2c devices that's why this is most likely just c&p from zcu102.
include/configs/trenz_te0820.h line 44
Quoted 5 lines
include/configs/trenz_te0820.h new file +5
-0+ +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_ZYNQ_EEPROM_BUS 5
I didn't see eemprom with mac above that's why likely c&p error.
include/configs/trenz_te0820.h line 45
Quoted 1 line
include/configs/trenz_te0820.h new file +1
-0+#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
Are you really going to use ATAGS?
include/configs/trenz_te0820.h line 49
Quoted 5 lines
include/configs/trenz_te0820.h new file +4
-0+ +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_TE0820_H */
Thanks,
Michal
Signature · 14 lines
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: OpenPGP digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180503/fa5f3d3a/attachment.sig>