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arm: mach-omap2: cache: Explicitly enable I cache

PATCH In review Lokesh Vutla 3 participants 4 messages May 3, 2018 – May 6, 2018

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Arm (32-bit) Arm sub-architectures OMAP2+ support
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Lokesh Vutla

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#0 lore raw

PATCH 1/1 arm: mach-omap2: cache: Explicitly enable I cache

omap-common cache enabling sequence relies on cpu_init_cp15() (inside start.S) for enabling I-caches. But cpu_init_cp15() can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So enable I-caches if not enabled already.

Debugged-by Jean-Jacques Hiblot <[email protected]>
Tested-by Steve Kipisz <[email protected]>
Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/mach-omap2/omap-cache.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
arch/arm/mach-omap2/omap-cache.c +5 -1
index b37163a4f3..975ee1b020 100644
@@ -44,7 +44,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void enable_caches(void)
 {
-	/* Enable D-cache. I-cache is already enabled in start.S */
+
+	/* Enable I cache if not enabled */
+	if (!icache_status())
+		icache_enable();
+
 	dcache_enable();
 }
Signature · 1 line
2.17.0
#1 lore raw

PATCH 1/1 arm: mach-omap2: cache: Explicitly enable I cache

Quoted 19 lines · Lokesh Vutla

omap-common cache enabling sequence relies on cpu_init_cp15() (inside start.S) for enabling I-caches. But cpu_init_cp15() can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So enable I-caches if not enabled already.

Debugged-by Jean-Jacques Hiblot <[email protected]>
Tested-by Steve Kipisz <[email protected]>
Signed-off-by Lokesh Vutla <[email protected]>
---
  arch/arm/mach-omap2/omap-cache.c | 6 +++++-
  1 file changed, 5 insertions(+), 1 deletion(-)
arch/arm/mach-omap2/omap-cache.c +0 -0
index b37163a4f3..975ee1b020 100644
@@ -44,7 +44,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
  void enable_caches(void)

arch/arm/mach-omap2/omap-cache.c DECLARE_GLOBAL_DATA_PTR; · line 54

Quoted 10 lines
arch/arm/mach-omap2/omap-cache.c +5 -1
  {
-	/* Enable D-cache. I-cache is already enabled in start.S */
+
+	/* Enable I cache if not enabled */
+	if (!icache_status())
+		icache_enable();
+
  	dcache_enable();
  }
Tested-by Jean-Jacques Hiblot <[email protected]>
#2 lore raw

PATCH 1/1 arm: mach-omap2: cache: Explicitly enable I cache

In reply to Lokesh Vutla
Quoted 8 lines · Lokesh Vutla

omap-common cache enabling sequence relies on cpu_init_cp15() (inside start.S) for enabling I-caches. But cpu_init_cp15() can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So enable I-caches if not enabled already.

Debugged-by Jean-Jacques Hiblot <[email protected]>
Tested-by Steve Kipisz <[email protected]>
Signed-off-by Lokesh Vutla <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Signature · 8 lines
Tom
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#3 lore raw
In reply to Lokesh Vutla
Quoted 10 lines · Lokesh Vutla

omap-common cache enabling sequence relies on cpu_init_cp15() (inside start.S) for enabling I-caches. But cpu_init_cp15() can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So enable I-caches if not enabled already.

Debugged-by Jean-Jacques Hiblot <[email protected]>
Tested-by Steve Kipisz <[email protected]>
Signed-off-by Lokesh Vutla <[email protected]>
Tested-by Jean-Jacques Hiblot <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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