phy: sunxi: Add Allwinner sun4i USB PHY

PATCH Superseded Jagan Teki 5 participants 55 messages May 7, 2018 – May 22, 2018

Subsystems (7)

Arm (32-bit) USB Arm sub-architectures Arm/Allwinner sunXi SoC support +3 more subsystems

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Jagan Teki

author

2018-05-07 07:33 UTC #0 lore raw

v7 cover phy: sunxi: Add Allwinner sun4i USB PHY

This series rework of previous version where it removes legacy usb phy handling and added phy driver on generic-phy framework.

Current implementation phy driver is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future.

Changes for v7:
- rebase on master

Changes for v6:
- Create private config for passing through driver_data instead directly passing musb_config. This make room for adding new configs in coming patches.
- memset to pdata in musb-new/sunxi.c

Changes for v5:
- Rework of previous series
- Used driver_data on sunxi.c since dt supported
- tested on bpi-m2-plus, orangepi_pc2/prime, bananapi-m64

Changes for v4:
- Rework of previous series
- Add Allwinner sun4i USB PHY driver
- Drop legacy arch/arm/mach-sunxi/usb_phy.c and related code

Chen-Yu Tsai (1):
sunxi: clock: Fix OHCI clock gating for H3/H5

Jagan Teki (33):
usb: sunxi: Simplify ccm reg base code
musb: sunxi: Add proper macros instead of numericals
musb: sunxi: Use simple way to fill musb_hdrc pdata
musb: sunxi: Add fifo config
sunxi: clock: Fix clock gating for H3/H5/A64
musb: sunxi: Add OTG device clkgate and reset for H3/H5
musb: sunxi: Use BIT instead of numerical shift
musb: sunxi: Add support for H3/H5A64
phy: Add Allwinner A64 USB PHY driver
phy: sun4i-usb: Add id_detect and vbus_detect ops
phy: sun4i-usb: Add H3/H5 PHY config
phy: sun4i-usb: Add V3S PHY config
phy: sun4i-usb: Add A83T USB PHY config
phy: sun4i-usb: Add A10/A13/A20 PHY config
phy: sun4i-usb: Add A31 PHY config
phy: sun4i-usb: Add A33 USB PHY config
phy: sun4i-usb: Add A23 USB PHY config
device-tree-bindings: phy: Sync sun4i-usb-phy bindings
board: sunxi: Use generic-phy for board_usb_cable_connected
phy: sun4i-usb: Add a sunxi specific function for setting
squelch-detect
usb: sunxi: Switch to use generic-phy
sunxi: Drop legacy usb_phy.c
arm64: allwinner: a64: bananapi-m64: Sync usb_otg node from Linux
configs: bananapi-m64: Enable USB OTG peripheral mode
ARM: dts: sun8i: a83t: Sync usbphy node from Linux
arm64: allwinner: a64: bananapi-m64: Sync usb host nodes from Linux
ARM: dts: sun8i-h3: bananapi-m2-plus: Sync usb otg nodes from Linux
configs: bananapi-m2-plus: Enable USB OTG peripheral mode
arm64: allwinner: h5: orangepi-pc2: Order nodes in alphabetic
arm64: allwinner: h5: orangepi-pc2: Sync usb otg nodes from Linux
configs: orangepi-pc2: Enable USB OTG peripheral mode
arm64: allwinner: h5: orangepi-prime: Sync usb otg nodes from Linux
configs: orangepi-prime: Enable USB OTG peripheral mode

Jun Nie (1):
sunxi: h3: Sync OTG and HCI nodes from Linux DT

 arch/arm/dts/sun50i-a64-bananapi-m64.dts       |  26 ++
 arch/arm/dts/sun50i-h5-orangepi-pc2.dts        |  59 ++-
 arch/arm/dts/sun50i-h5-orangepi-prime.dts      |  13 +
 arch/arm/dts/sun8i-a83t.dtsi                   |  20 +
 arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts     |  13 +
 arch/arm/dts/sun8i-h3.dtsi                     |  32 ++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h  |  23 +-
 arch/arm/include/asm/arch-sunxi/usb_phy.h      |  21 -
 arch/arm/mach-sunxi/Kconfig                    |   9 +
 arch/arm/mach-sunxi/Makefile                   |   3 -
 arch/arm/mach-sunxi/usb_phy.c                  | 407 -----------------
 board/sunxi/board.c                            |  40 +-
 configs/Sinovoip_BPI_M2_Plus_defconfig         |   1 +
 configs/bananapi_m64_defconfig                 |   1 +
 configs/orangepi_pc2_defconfig                 |   1 +
 configs/orangepi_prime_defconfig               |   1 +
 doc/device-tree-bindings/phy/sun4i-usb-phy.txt |  65 +++
 drivers/Kconfig                                |   2 +
 drivers/Makefile                               |   1 +
 drivers/phy/allwinner/Kconfig                  |  13 +
 drivers/phy/allwinner/Makefile                 |   6 +
 drivers/phy/allwinner/phy-sun4i-usb.c          | 575 +++++++++++++++++++++++++
 drivers/usb/host/ehci-sunxi.c                  |  66 ++-
 drivers/usb/host/ohci-sunxi.c                  |  72 +++-
 drivers/usb/musb-new/musb_core.h               |   4 +
 drivers/usb/musb-new/musb_regs.h               |   3 +-
 drivers/usb/musb-new/musb_uboot.c              |  22 +-
 drivers/usb/musb-new/sunxi.c                   | 228 ++++++++--
 include/phy-sun4i-usb.h                        |  34 ++
 29 files changed, 1191 insertions(+), 570 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-sunxi/usb_phy.h
 delete mode 100644 arch/arm/mach-sunxi/usb_phy.c
 create mode 100644 doc/device-tree-bindings/phy/sun4i-usb-phy.txt
 create mode 100644 drivers/phy/allwinner/Kconfig
 create mode 100644 drivers/phy/allwinner/Makefile
 create mode 100644 drivers/phy/allwinner/phy-sun4i-usb.c
 create mode 100644 include/phy-sun4i-usb.h

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #1 lore raw

PATCH v7 1/35 usb: sunxi: Simplify ccm reg base code

Move struct sunxi_ccm_reg pointer to private structure so-that accessing ccm reg base become more proper way and avoid local initialization in each function.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/host/ehci-sunxi.c | 15 +++++++++------
 drivers/usb/host/ohci-sunxi.c | 19 +++++++++++--------
 drivers/usb/musb-new/sunxi.c  | 34 +++++++++++++++++++++++-----------
 3 files changed, 43 insertions(+), 25 deletions(-)

drivers/usb/host/ehci-sunxi.c +9 -6

index 6ecb7c4d12..ed9763c63d 100644
@@ -27,19 +27,23 @@
 
 struct ehci_sunxi_priv {
 	struct ehci_ctrl ehci;
+	struct sunxi_ccm_reg *ccm;
 	int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
 	int phy_index;     /* Index of the usb-phy attached to this hcd */
 };
 
 static int ehci_usb_probe(struct udevice *dev)
 {
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct usb_platdata *plat = dev_get_platdata(dev);
 	struct ehci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ehci_hccr *hccr = (struct ehci_hccr *)devfdt_get_addr(dev);
 	struct ehci_hcor *hcor;
 	int extra_ahb_gate_mask = 0;
 
+	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	if (IS_ERR(priv->ccm))
+		return PTR_ERR(priv->ccm);
+
 	/*
 	 * This should go away once we've moved to the driver model for
 	 * clocks resp. phys.

@@ -53,10 +57,10 @@ static int ehci_usb_probe(struct udevice *dev)
 	extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
 	priv->phy_index++; /* Non otg phys start at 1 */
 
-	setbits_le32(&ccm->ahb_gate0,
+	setbits_le32(&priv->ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg,
+	setbits_le32(&priv->ccm->ahb_reset0_cfg,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
 #endif

@@ -71,7 +75,6 @@ static int ehci_usb_probe(struct udevice *dev)
 
 static int ehci_usb_remove(struct udevice *dev)
 {
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct ehci_sunxi_priv *priv = dev_get_priv(dev);
 	int ret;

@@ -82,9 +85,9 @@ static int ehci_usb_remove(struct udevice *dev)
 	sunxi_usb_phy_exit(priv->phy_index);
 
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
+	clrbits_le32(&priv->ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
 #endif
-	clrbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
+	clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask);
 
 	return 0;
 }

drivers/usb/host/ohci-sunxi.c +11 -8

index 133774f6e6..35efa88795 100644
@@ -26,6 +26,7 @@
 #endif
 
 struct ohci_sunxi_priv {
+	struct sunxi_ccm_reg *ccm;
 	ohci_t ohci;
 	int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
 	int usb_gate_mask; /* Mask of usb_clk_cfg clk gate bits for this hcd */

@@ -34,12 +35,15 @@ struct ohci_sunxi_priv {
 
 static int ohci_usb_probe(struct udevice *dev)
 {
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
 	int extra_ahb_gate_mask = 0;
 
+	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	if (IS_ERR(priv->ccm))
+		return PTR_ERR(priv->ccm);
+
 	bus_priv->companion = true;
 
 	/*

@@ -57,11 +61,11 @@ static int ohci_usb_probe(struct udevice *dev)
 	priv->usb_gate_mask <<= priv->phy_index;
 	priv->phy_index++; /* Non otg phys start at 1 */
 
-	setbits_le32(&ccm->ahb_gate0,
+	setbits_le32(&priv->ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
-	setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
+	setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg,
+	setbits_le32(&priv->ccm->ahb_reset0_cfg,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
 #endif

@@ -73,7 +77,6 @@ static int ohci_usb_probe(struct udevice *dev)
 
 static int ohci_usb_remove(struct udevice *dev)
 {
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
 	int ret;

@@ -84,10 +87,10 @@ static int ohci_usb_remove(struct udevice *dev)
 	sunxi_usb_phy_exit(priv->phy_index);
 
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
+	clrbits_le32(&priv->ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
 #endif
-	clrbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
-	clrbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
+	clrbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+	clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask);
 
 	return 0;
 }

drivers/usb/musb-new/sunxi.c +23 ~~-11~~

index aedc24b937..c77bde0354 100644
@@ -76,6 +76,13 @@
  * From usbc/usbc.c
  ******************************************************************************/
 
+struct sunxi_glue {
+	struct musb_host_data mdata;
+	struct sunxi_ccm_reg *ccm;
+	struct device dev;
+};
+#define to_sunxi_glue(d)	container_of(d, struct sunxi_glue, dev)
+
 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
 {
 	u32 temp = reg_val;

@@ -256,15 +263,15 @@ static void sunxi_musb_disable(struct musb *musb)
 
 static int sunxi_musb_init(struct musb *musb)
 {
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
 
 	pr_debug("%s():\n", __func__);
 
 	musb->isr = sunxi_musb_interrupt;
 
-	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+	setbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+	setbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
 #endif
 	sunxi_usb_phy_init(0);

@@ -310,7 +317,8 @@ static struct musb_hdrc_platform_data musb_plat = {
 
 static int musb_usb_probe(struct udevice *dev)
 {
-	struct musb_host_data *host = dev_get_priv(dev);
+	struct sunxi_glue *glue = dev_get_priv(dev);
+	struct musb_host_data *host = &glue->mdata;
 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
 	void *base = dev_read_addr_ptr(dev);
 	int ret;

@@ -318,10 +326,14 @@ static int musb_usb_probe(struct udevice *dev)
 	if (!base)
 		return -EINVAL;
 
+	glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	if (IS_ERR(glue->ccm))
+		return PTR_ERR(glue->ccm);
+
 	priv->desc_before_addr = true;
 
 #ifdef CONFIG_USB_MUSB_HOST
-	host->host = musb_init_controller(&musb_plat, NULL, base);
+	host->host = musb_init_controller(&musb_plat, &glue->dev, base);
 	if (!host->host)
 		return -EIO;

@@ -329,7 +341,7 @@ static int musb_usb_probe(struct udevice *dev)
 	if (!ret)
 		printf("Allwinner mUSB OTG (Host)\n");
 #else
-	ret = musb_register(&musb_plat, NULL, base);
+	ret = musb_register(&musb_plat, &glue->dev, base);
 	if (!ret)
 		printf("Allwinner mUSB OTG (Peripheral)\n");
 #endif

@@ -339,16 +351,16 @@ static int musb_usb_probe(struct udevice *dev)
 
 static int musb_usb_remove(struct udevice *dev)
 {
-	struct musb_host_data *host = dev_get_priv(dev);
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_glue *glue = dev_get_priv(dev);
+	struct musb_host_data *host = &glue->mdata;
 
 	musb_stop(host->host);
 
 	sunxi_usb_phy_exit(0);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+	clrbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
 #endif
-	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+	clrbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
 
 	free(host->host);
 	host->host = NULL;

@@ -378,5 +390,5 @@ U_BOOT_DRIVER(usb_musb) = {
 	.ops		= &musb_usb_ops,
 #endif
 	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
-	.priv_auto_alloc_size = sizeof(struct musb_host_data),
+	.priv_auto_alloc_size = sizeof(struct sunxi_glue),
 };

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #2 lore raw

PATCH v7 2/35 musb: sunxi: Add proper macros instead of numericals

In reply to Jagan Teki

- add proper macros for musb_config members
- use bool 'true' for multipoint and dyn_fifo instead of numerical 1

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/musb-new/sunxi.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

drivers/usb/musb-new/sunxi.c +8 -4

index c77bde0354..3f3b89886a 100644
@@ -297,11 +297,15 @@ static const struct musb_platform_ops sunxi_musb_ops = {
 	.disable	= sunxi_musb_disable,
 };
 
+/* Allwinner OTG supports up to 5 endpoints */
+#define SUNXI_MUSB_MAX_EP_NUM		6
+#define SUNXI_MUSB_RAM_BITS		11
+
 static struct musb_hdrc_config musb_config = {
-	.multipoint     = 1,
-	.dyn_fifo       = 1,
-	.num_eps        = 6,
-	.ram_bits       = 11,
+	.multipoint	= true,
+	.dyn_fifo	= true,
+	.num_eps	= SUNXI_MUSB_MAX_EP_NUM,
+	.ram_bits	= SUNXI_MUSB_RAM_BITS,
 };
 
 static struct musb_hdrc_platform_data musb_plat = {

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #3 lore raw

PATCH v7 3/35 musb: sunxi: Use simple way to fill musb_hdrc pdata

In reply to Jagan Teki

Filling musb_hdrc pdata using structure will unnecessary add extra ifdefs, so fill them inside probe call for better code understanding and get rid ifdefs using devicetree compatible.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/musb-new/sunxi.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

drivers/usb/musb-new/sunxi.c +10 ~~-13~~

index 3f3b89886a..637e8b9b52 100644
@@ -308,22 +308,12 @@ static struct musb_hdrc_config musb_config = {
 	.ram_bits	= SUNXI_MUSB_RAM_BITS,
 };
 
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HOST)
-	.mode           = MUSB_HOST,
-#else
-	.mode		= MUSB_PERIPHERAL,
-#endif
-	.config         = &musb_config,
-	.power          = 250,
-	.platform_ops	= &sunxi_musb_ops,
-};
-
 static int musb_usb_probe(struct udevice *dev)
 {
 	struct sunxi_glue *glue = dev_get_priv(dev);
 	struct musb_host_data *host = &glue->mdata;
 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+	struct musb_hdrc_platform_data pdata;
 	void *base = dev_read_addr_ptr(dev);
 	int ret;

@@ -336,8 +326,14 @@ static int musb_usb_probe(struct udevice *dev)
 
 	priv->desc_before_addr = true;
 
+	memset(&pdata, 0, sizeof(pdata));
+	pdata.power = 250;
+	pdata.platform_ops = &sunxi_musb_ops;
+	pdata.config = &musb_config;
+
 #ifdef CONFIG_USB_MUSB_HOST
-	host->host = musb_init_controller(&musb_plat, &glue->dev, base);
+	pdata.mode = MUSB_HOST;
+	host->host = musb_init_controller(&pdata, &glue->dev, base);
 	if (!host->host)
 		return -EIO;

@@ -345,7 +341,8 @@ static int musb_usb_probe(struct udevice *dev)
 	if (!ret)
 		printf("Allwinner mUSB OTG (Host)\n");
 #else
-	ret = musb_register(&musb_plat, &glue->dev, base);
+	pdata.mode = MUSB_PERIPHERAL;
+	ret = musb_register(&pdata, &glue->dev, base);
 	if (!ret)
 		printf("Allwinner mUSB OTG (Peripheral)\n");
 #endif

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #4 lore raw

PATCH v7 4/35 musb: sunxi: Add fifo config

In reply to Jagan Teki

Unlike other Allwinner SOC's H3/H5/V3s OTG support 4 endpoints with relevant fifo configs, rest all have 5 endpoints. So add the fifo configs and defer them based on driver_data.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/musb-new/sunxi.c | 70 ++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 65 insertions(+), 5 deletions(-)

drivers/usb/musb-new/sunxi.c +65 -5

index 637e8b9b52..af0dbc5a20 100644
@@ -76,9 +76,14 @@
  * From usbc/usbc.c
  ******************************************************************************/
 
+struct sunxi_musb_config {
+	struct musb_hdrc_config *config;
+};
+
 struct sunxi_glue {
 	struct musb_host_data mdata;
 	struct sunxi_ccm_reg *ccm;
+	struct sunxi_musb_config *cfg;
 	struct device dev;
 };
 #define to_sunxi_glue(d)	container_of(d, struct sunxi_glue, dev)

@@ -301,13 +306,52 @@ static const struct musb_platform_ops sunxi_musb_ops = {
 #define SUNXI_MUSB_MAX_EP_NUM		6
 #define SUNXI_MUSB_RAM_BITS		11
 
+static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
+	MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
+};
+
+/* H3/V3s OTG supports only 4 endpoints */
+#define SUNXI_MUSB_MAX_EP_NUM_H3	5
+
+static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
+	MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
+};
+
 static struct musb_hdrc_config musb_config = {
+	.fifo_cfg       = sunxi_musb_mode_cfg,
+	.fifo_cfg_size  = ARRAY_SIZE(sunxi_musb_mode_cfg),
 	.multipoint	= true,
 	.dyn_fifo	= true,
 	.num_eps	= SUNXI_MUSB_MAX_EP_NUM,
 	.ram_bits	= SUNXI_MUSB_RAM_BITS,
 };
 
+static struct musb_hdrc_config musb_config_h3 = {
+	.fifo_cfg       = sunxi_musb_mode_cfg_h3,
+	.fifo_cfg_size  = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
+	.multipoint	= true,
+	.dyn_fifo	= true,
+	.soft_con       = true,
+	.num_eps	= SUNXI_MUSB_MAX_EP_NUM_H3,
+	.ram_bits	= SUNXI_MUSB_RAM_BITS,
+};
+
 static int musb_usb_probe(struct udevice *dev)
 {
 	struct sunxi_glue *glue = dev_get_priv(dev);

@@ -320,6 +364,10 @@ static int musb_usb_probe(struct udevice *dev)
 	if (!base)
 		return -EINVAL;
 
+	glue->cfg = (struct sunxi_musb_config *)dev_get_driver_data(dev);
+	if (!glue->cfg)
+		return -EINVAL;
+
 	glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	if (IS_ERR(glue->ccm))
 		return PTR_ERR(glue->ccm);

@@ -329,7 +377,7 @@ static int musb_usb_probe(struct udevice *dev)
 	memset(&pdata, 0, sizeof(pdata));
 	pdata.power = 250;
 	pdata.platform_ops = &sunxi_musb_ops;
-	pdata.config = &musb_config;
+	pdata.config = glue->cfg->config;
 
 #ifdef CONFIG_USB_MUSB_HOST
 	pdata.mode = MUSB_HOST;

@@ -369,11 +417,23 @@ static int musb_usb_remove(struct udevice *dev)
 	return 0;
 }
 
+static const struct sunxi_musb_config sun4i_a10_cfg = {
+	.config = &musb_config,
+};
+
+static const struct sunxi_musb_config sun8i_h3_cfg = {
+	.config = &musb_config_h3,
+};
+
 static const struct udevice_id sunxi_musb_ids[] = {
-	{ .compatible = "allwinner,sun4i-a10-musb" },
-	{ .compatible = "allwinner,sun6i-a31-musb" },
-	{ .compatible = "allwinner,sun8i-a33-musb" },
-	{ .compatible = "allwinner,sun8i-h3-musb" },
+	{ .compatible = "allwinner,sun4i-a10-musb",
+			.data = (ulong)&sun4i_a10_cfg },
+	{ .compatible = "allwinner,sun6i-a31-musb",
+			.data = (ulong)&sun4i_a10_cfg },
+	{ .compatible = "allwinner,sun8i-a33-musb",
+			.data = (ulong)&sun4i_a10_cfg },
+	{ .compatible = "allwinner,sun8i-h3-musb",
+			.data = (ulong)&sun8i_h3_cfg },
 	{ }
 };

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #5 lore raw

PATCH v7 5/35 sunxi: clock: Fix clock gating for H3/H5/A64

In reply to Jagan Teki

clock gating bits on a64 are different than H3_H5, so fixed only required bits on clock_sun6i.h.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +9 -3

index d35aa479f7..c5dea45985 100644
@@ -271,21 +271,27 @@ struct sunxi_ccm_reg {
 #define AXI_GATE_OFFSET_DRAM		0
 
 /* ahb_gate0 offsets */
-#define AHB_GATE_OFFSET_USB_OHCI1	30
-#define AHB_GATE_OFFSET_USB_OHCI0	29
 #ifdef CONFIG_MACH_SUNXI_H3_H5
 /*
  * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
  * them 0 - 2 like they were called on older SoCs.
  */
+#define AHB_GATE_OFFSET_USB_OHCI0	28
 #define AHB_GATE_OFFSET_USB_EHCI2	27
 #define AHB_GATE_OFFSET_USB_EHCI1	26
+#define AHB_GATE_OFFSET_USB_EHCI0	24
+#elif defined(CONFIG_MACH_SUN50I)
+#define AHB_GATE_OFFSET_USB_OHCI0	29
 #define AHB_GATE_OFFSET_USB_EHCI0	25
 #else
+#define AHB_GATE_OFFSET_USB_OHCI1	30
+#define AHB_GATE_OFFSET_USB_OHCI0	29
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
 #endif
-#ifndef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN50I
+#define AHB_GATE_OFFSET_USB0		23
+#elif !defined(CONFIG_MACH_SUN8I_R40)
 #define AHB_GATE_OFFSET_USB0		24
 #else
 #define AHB_GATE_OFFSET_USB0		25

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #6 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

In reply to Jagan Teki

Add OTG device clkgate and reset for H3/H5 through driver_data.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/musb-new/sunxi.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

drivers/usb/musb-new/sunxi.c +17 -0

index af0dbc5a20..e79d7a2774 100644
@@ -78,6 +78,8 @@
 
 struct sunxi_musb_config {
 	struct musb_hdrc_config *config;
+	u8 rst_bit;
+	u8 clkgate_bit;
 };
 
 struct sunxi_glue {

@@ -275,9 +277,16 @@ static int sunxi_musb_init(struct musb *musb)
 	musb->isr = sunxi_musb_interrupt;
 
 	setbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+	if (glue->cfg->clkgate_bit)
+		setbits_le32(&glue->ccm->ahb_gate0,
+			     1 << glue->cfg->clkgate_bit);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	setbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+	if (glue->cfg->rst_bit)
+		setbits_le32(&glue->ccm->ahb_reset0_cfg,
+			     1 << glue->cfg->rst_bit);
 #endif
+
 	sunxi_usb_phy_init(0);
 
 	USBC_ConfigFIFO_Base();

@@ -408,8 +417,14 @@ static int musb_usb_remove(struct udevice *dev)
 	sunxi_usb_phy_exit(0);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	clrbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+	if (glue->cfg->rst_bit)
+		clrbits_le32(&glue->ccm->ahb_reset0_cfg,
+			     1 << glue->cfg->rst_bit);
 #endif
 	clrbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+	if (glue->cfg->clkgate_bit)
+		clrbits_le32(&glue->ccm->ahb_gate0,
+			     1 << glue->cfg->clkgate_bit);
 
 	free(host->host);
 	host->host = NULL;

@@ -423,6 +438,8 @@ static const struct sunxi_musb_config sun4i_a10_cfg = {
 
 static const struct sunxi_musb_config sun8i_h3_cfg = {
 	.config = &musb_config_h3,
+	.rst_bit = 23,
+	.clkgate_bit = 23,
 };
 
 static const struct udevice_id sunxi_musb_ids[] = {

Signature · 1 line

2.14.3

Marek Vasut

2018-05-07 11:47 UTC #7 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 3 lines · Jagan Teki

Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by Jagan Teki <[email protected]>

Why don't you implement a clock driver for this SoC instead ?

Signature · 2 lines

Best regards,
Marek Vasut

Maxime Ripard

2018-05-07 14:52 UTC #8 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 6 lines · Marek Vasut

Quoted 3 lines · Jagan Teki
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by Jagan Teki <[email protected]>
Why don't you implement a clock driver for this SoC instead ?

Aren't you asking a bit too much?

Since the first post of these patches, you've asked to rework in a significant manner the driver already, including doing a new PHY driver to use the device model, and making other substantial changes to it.

Jagan complied to all your requests so far, but this one is going to create yet another ton of patches on top of an (already) 35 patches series. And this request comes out of nowhere at the 7th version.

Creating a new clock driver will take a lot of effort, and this really surprise me given that we've had strictly no feedback from you on this considering all the previous SoCs bringups we've done so far.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Marek Vasut

2018-05-07 15:32 UTC #9 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 9 lines · Maxime Ripard

Quoted 6 lines · Marek Vasut
Quoted 3 lines · Jagan Teki
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by Jagan Teki <[email protected]>
Why don't you implement a clock driver for this SoC instead ?
Aren't you asking a bit too much?

I am not asking for anything, this is a question, not a request.

I asked why not implement a clock driver and use it just like any other civilized modern driver would instead of digging in the clock controller registers from a USB framework driver (which is icky).

I think that if we are doing some sort of conversion, we should do it completely and properly instead of leaving in hacks like this. A clock driver which allows enabling/disabling clock is probably like what, 2 hour work ? So maybe it's worth investing that time up front to save maintenance burden in the future.

Quoted 4 lines

Since the first post of these patches, you've asked to rework in a significant manner the driver already, including doing a new PHY driver to use the device model, and making other substantial changes to it.

Well yes, because it was crap at the beginning and I don't want to see the crap accumulating. It has become much better since, as you can see I only had a few minor comments.

Quoted 3 lines

Jagan complied to all your requests so far, but this one is going to create yet another ton of patches on top of an (already) 35 patches series. And this request comes out of nowhere at the 7th version.

I disagree, one clock driver patch and a tweak to the series, unless I missed something obvious.

Quoted 3 lines

Creating a new clock driver will take a lot of effort, and this really surprise me given that we've had strictly no feedback from you on this considering all the previous SoCs bringups we've done so far.

What do you mean by "this" ? I think i did review the previous iterations of this series ? If not, was I on CC ?

I have to admit, I don't really care about the rest of the Allwinner SoC code or what you do there, I only care about the USB part and this poking of clock controller registers seems wrong in a DM/DT driver.

I also don't mind if the clock driver comes later, but I would like to see it happen at some point (soon) to remove this register poking.

Signature · 2 lines

Best regards,
Marek Vasut

Maxime Ripard

2018-05-07 20:11 UTC #10 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 5 lines · Marek Vasut

Quoted 4 lines · Maxime Ripard
Quoted 3 lines · Marek Vasut
Quoted 2 lines · Jagan Teki
Add OTG device clkgate and reset for H3/H5 through driver_data.

Quoted 7 lines

Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Jagan Teki <[email protected]>
Why don't you implement a clock driver for this SoC instead ?
Aren't you asking a bit too much?
I am not asking for anything, this is a question, not a request.

My bad then, this definitely sounded like a request to me.

Quoted 3 lines

I asked why not implement a clock driver and use it just like any other civilized modern driver would instead of digging in the clock controller registers from a USB framework driver (which is icky).

From an absolute point of view, I agree. But we are where we are.

Quoted 5 lines

I think that if we are doing some sort of conversion, we should do it completely and properly instead of leaving in hacks like this. A clock driver which allows enabling/disabling clock is probably like what, 2 hour work ? So maybe it's worth investing that time up front to save maintenance burden in the future.

This is definitely not a 2 hours job. More like 2 weeks if you want to do it properly, and by which I mean creating the clock driver, converting all the users to it, and then making sure you don't have any regressions.

This is on our radar, but this won't happen overnight.

Quoted 8 lines

Quoted 4 lines
Since the first post of these patches, you've asked to rework in a significant manner the driver already, including doing a new PHY driver to use the device model, and making other substantial changes to it.
Well yes, because it was crap at the beginning and I don't want to see the crap accumulating. It has become much better since, as you can see I only had a few minor comments.

And that's totally your role, but at the same time, the point of this series is not to fix the whole world, but rather add support for one particular SoC that is using pretty much the same design than any of our other SoCs' USB phy before. And here we are, 35 patches and counting.

Quoted 6 lines

Quoted 3 lines
Jagan complied to all your requests so far, but this one is going to create yet another ton of patches on top of an (already) 35 patches series. And this request comes out of nowhere at the 7th version.
I disagree, one clock driver patch and a tweak to the series, unless I missed something obvious.

This won't be one clock driver patch. Seriously.

Quoted 6 lines

Quoted 3 lines
Creating a new clock driver will take a lot of effort, and this really surprise me given that we've had strictly no feedback from you on this considering all the previous SoCs bringups we've done so far.
What do you mean by "this" ? I think i did review the previous iterations of this series ? If not, was I on CC ?

You did, and thanks a lot for that. The only thing I'm noting is that it's the first time you're being so picky about a series. I appreciate that you have to draw the line somewhere, and when things you want in your subsystem aren't moving as fast as you'd like them to be you have to enforce new rules. But if you were unhappy about something, you never told us, which doesn't seem like a good path forward either. Even in your previous reviews of that particular series.

Quoted 3 lines

I have to admit, I don't really care about the rest of the Allwinner SoC code or what you do there, I only care about the USB part and this poking of clock controller registers seems wrong in a DM/DT driver.

And I do agree on that. But we also have some history to carry.

Quoted 2 lines

I also don't mind if the clock driver comes later, but I would like to see it happen at some point (soon) to remove this register poking.

Awesome then :)

Maxime

Signature · 3 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Marek Vasut

2018-05-07 20:55 UTC #11 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 8 lines · Maxime Ripard

Quoted 7 lines · Marek Vasut
Quoted 6 lines · Maxime Ripard
Quoted 5 lines · Marek Vasut
Quoted 3 lines · Jagan Teki
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by Jagan Teki <[email protected]>

Quoted 7 lines

Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Why don't you implement a clock driver for this SoC instead ?
Aren't you asking a bit too much?
I am not asking for anything, this is a question, not a request.
My bad then, this definitely sounded like a request to me.

So uh, how do I make this NOT sound like a request to you ? Can you phrase it for me ?

Quoted 5 lines

Quoted 3 lines
I asked why not implement a clock driver and use it just like any other civilized modern driver would instead of digging in the clock controller registers from a USB framework driver (which is icky).
From an absolute point of view, I agree. But we are where we are.

Which is where exactly ?

Quoted 6 lines

Quoted 5 lines
I think that if we are doing some sort of conversion, we should do it completely and properly instead of leaving in hacks like this. A clock driver which allows enabling/disabling clock is probably like what, 2 hour work ? So maybe it's worth investing that time up front to save maintenance burden in the future.

Quoted 6 lines

This is definitely not a 2 hours job. More like 2 weeks if you want to do it properly, and by which I mean creating the clock driver, converting all the users to it, and then making sure you don't have any regressions.
This is on our radar, but this won't happen overnight.

Fine

Quoted 9 lines

Quoted 8 lines
Quoted 4 lines
Since the first post of these patches, you've asked to rework in a significant manner the driver already, including doing a new PHY driver to use the device model, and making other substantial changes to it.
Well yes, because it was crap at the beginning and I don't want to see the crap accumulating. It has become much better since, as you can see I only had a few minor comments.

Quoted 5 lines

And that's totally your role, but at the same time, the point of this series is not to fix the whole world, but rather add support for one particular SoC that is using pretty much the same design than any of our other SoCs' USB phy before. And here we are, 35 patches and counting.

If I said "yes" to every single patch adding just a minor additional bit of crap to the codebase, we'd be in the state in which we were in 2012, sinking under the boatload of ifdeffery and ad-hoc solutions. So I think some push is needed to avoid that situation.

Quoted 8 lines

Quoted 6 lines
Quoted 3 lines
Jagan complied to all your requests so far, but this one is going to create yet another ton of patches on top of an (already) 35 patches series. And this request comes out of nowhere at the 7th version.
I disagree, one clock driver patch and a tweak to the series, unless I missed something obvious.
This won't be one clock driver patch. Seriously.

Fine

Quoted 9 lines

Quoted 6 lines
Quoted 3 lines
Creating a new clock driver will take a lot of effort, and this really surprise me given that we've had strictly no feedback from you on this considering all the previous SoCs bringups we've done so far.
What do you mean by "this" ? I think i did review the previous iterations of this series ? If not, was I on CC ?
You did, and thanks a lot for that. The only thing I'm noting is that it's the first time you're being so picky about a series.

Er, no, I am always picky and hard.

Quoted 6 lines

I appreciate
that you have to draw the line somewhere, and when things you want in your subsystem aren't moving as fast as you'd like them to be you have to enforce new rules. But if you were unhappy about something, you never told us, which doesn't seem like a good path forward either. Even in your previous reviews of that particular series.

I think I pointed out pretty much all of it ? If I missed something, it's because it was hidden and didn't surface until the patchset got into some better shape.

Quoted 10 lines

Quoted 3 lines
I have to admit, I don't really care about the rest of the Allwinner SoC code or what you do there, I only care about the USB part and this poking of clock controller registers seems wrong in a DM/DT driver.
And I do agree on that. But we also have some history to carry.
Quoted 2 lines
I also don't mind if the clock driver comes later, but I would like to see it happen at some point (soon) to remove this register poking.
Awesome then :)

Is this going to happen at some point ?

Signature · 2 lines

Best regards,
Marek Vasut

Maxime Ripard

2018-05-11 21:29 UTC #12 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 11 lines · Marek Vasut

Quoted 10 lines · Maxime Ripard
Quoted 9 lines · Marek Vasut
Quoted 8 lines · Maxime Ripard
Quoted 6 lines · Marek Vasut
Quoted 3 lines · Jagan Teki
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by Jagan Teki <[email protected]>
Why don't you implement a clock driver for this SoC instead ?

Quoted 8 lines

Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Aren't you asking a bit too much?
I am not asking for anything, this is a question, not a request.
My bad then, this definitely sounded like a request to me.
So uh, how do I make this NOT sound like a request to you ? Can you phrase it for me ?

You are in a situation of power here. Asking the exact same question when you are the one in power or is a peer doesn't have the same impact, unless you make it clear that it is an actual question and not some way to have it fixed.

Something like "Would switching to a proper clock driver be an option?" for example would have carried the message better imo, if this was a genuine question and not a request.

Quoted 7 lines

Quoted 5 lines
Quoted 3 lines
I asked why not implement a clock driver and use it just like any other civilized modern driver would instead of digging in the clock controller registers from a USB framework driver (which is icky).
From an absolute point of view, I agree. But we are where we are.
Which is where exactly ?

Having to deal with code from 2012 everywhere.

Quoted 15 lines

Quoted 9 lines
Quoted 8 lines
Quoted 4 lines
Since the first post of these patches, you've asked to rework in a significant manner the driver already, including doing a new PHY driver to use the device model, and making other substantial changes to it.
Well yes, because it was crap at the beginning and I don't want to see the crap accumulating. It has become much better since, as you can see I only had a few minor comments.
Quoted 5 lines
And that's totally your role, but at the same time, the point of this series is not to fix the whole world, but rather add support for one particular SoC that is using pretty much the same design than any of our other SoCs' USB phy before. And here we are, 35 patches and counting.

Quoted 4 lines

If I said "yes" to every single patch adding just a minor additional bit of crap to the codebase, we'd be in the state in which we were in 2012, sinking under the boatload of ifdeffery and ad-hoc solutions. So I think some push is needed to avoid that situation.

I don't have any issue with the end goal, and your willingness to have the code ported over to new APIs. But if from one day to another every maintainer goes like this, this will simply not fly. This is not just about having just a simple clock driver, but also a pinctrl one, and converting all the consumer drivers to the device model, oh, and btw, the DM doesn't fit in the SPL anymore, so we would probably need to do an SPL driver as well. Probably with some painful Kconfig conversions all over the tree even.

This is no longer a simple request, but some huge spaghetti changes that need to be done, mostly by volunteers. And at some point, it just becomes easier to give up, fork, and just maintain our stuff like we were doing before. Or just stop maintaining it entirely. And I'm not sure either situation is something we want.

tl; dr: I'd like some moderation.

Quoted 19 lines

Quoted 9 lines
Quoted 6 lines
Quoted 3 lines
Creating a new clock driver will take a lot of effort, and this really surprise me given that we've had strictly no feedback from you on this considering all the previous SoCs bringups we've done so far.
What do you mean by "this" ? I think i did review the previous iterations of this series ? If not, was I on CC ?
You did, and thanks a lot for that. The only thing I'm noting is that it's the first time you're being so picky about a series.
Er, no, I am always picky and hard.
Quoted 6 lines
I appreciate that you have to draw the line somewhere, and when things you want in your subsystem aren't moving as fast as you'd like them to be you have to enforce new rules. But if you were unhappy about something, you never told us, which doesn't seem like a good path forward either. Even in your previous reviews of that particular series.

Quoted 3 lines

I think I pointed out pretty much all of it ? If I missed something, it's because it was hidden and didn't surface until the patchset got into some better shape.

And yet, this is the first time you bring up the phy and clock support.

Quoted 4 lines

Quoted 4 lines
Quoted 3 lines
I have to admit, I don't really care about the rest of the Allwinner SoC code or what you do there, I only care about the USB part and this poking of clock controller registers seems wrong in a DM/DT driver.

Quoted 8 lines

Quoted 6 lines
And I do agree on that. But we also have some history to carry.
Quoted 2 lines
I also don't mind if the clock driver comes later, but I would like to see it happen at some point (soon) to remove this register poking.
Awesome then :)
Is this going to happen at some point ?

At some point, yes, but I can't give you a deadline.

Maxime

Signature · 3 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

Marek Vasut

2018-05-12 12:12 UTC #13 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 21 lines · Maxime Ripard

Quoted 11 lines · Marek Vasut
Quoted 10 lines · Maxime Ripard
Quoted 9 lines · Marek Vasut
Quoted 8 lines · Maxime Ripard
Quoted 6 lines · Marek Vasut
Quoted 3 lines · Jagan Teki
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by Jagan Teki <[email protected]>
Why don't you implement a clock driver for this SoC instead ?
Quoted 8 lines
Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Aren't you asking a bit too much?
I am not asking for anything, this is a question, not a request.
My bad then, this definitely sounded like a request to me.
So uh, how do I make this NOT sound like a request to you ? Can you phrase it for me ?

Quoted 8 lines

You are in a situation of power here. Asking the exact same question when you are the one in power or is a peer doesn't have the same impact, unless you make it clear that it is an actual question and not some way to have it fixed.
Something like "Would switching to a proper clock driver be an option?" for example would have carried the message better imo, if this was a genuine question and not a request.

I have to admit, I prefer simple, frugal, direct and clear questions which can be answered equally clearly rather than long essays filled with verbal fluff.

I'll consider this, but given that I am not a native English speaker, I cannot guarantee the result to be to everyone's satisfaction.

Quoted 9 lines

Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
I asked why not implement a clock driver and use it just like any other civilized modern driver would instead of digging in the clock controller registers from a USB framework driver (which is icky).
From an absolute point of view, I agree. But we are where we are.
Which is where exactly ?
Having to deal with code from 2012 everywhere.

This sounds like a massive generalization and an incorrect one to me *.

Quoted 20 lines

Quoted 15 lines
Quoted 9 lines
Quoted 8 lines
Quoted 4 lines
Since the first post of these patches, you've asked to rework in a significant manner the driver already, including doing a new PHY driver to use the device model, and making other substantial changes to it.
Well yes, because it was crap at the beginning and I don't want to see the crap accumulating. It has become much better since, as you can see I only had a few minor comments.
Quoted 5 lines
And that's totally your role, but at the same time, the point of this series is not to fix the whole world, but rather add support for one particular SoC that is using pretty much the same design than any of our other SoCs' USB phy before. And here we are, 35 patches and counting.
Quoted 4 lines
If I said "yes" to every single patch adding just a minor additional bit of crap to the codebase, we'd be in the state in which we were in 2012, sinking under the boatload of ifdeffery and ad-hoc solutions. So I think some push is needed to avoid that situation.

Quoted 8 lines

I don't have any issue with the end goal, and your willingness to have the code ported over to new APIs. But if from one day to another every maintainer goes like this, this will simply not fly. This is not just about having just a simple clock driver, but also a pinctrl one, and converting all the consumer drivers to the device model, oh, and btw, the DM doesn't fit in the SPL anymore, so we would probably need to do an SPL driver as well. Probably with some painful Kconfig conversions all over the tree even.

You are massively exaggerating right there. I recently did such a conversion for a platform and it didn't take nearly as much effort as you describe and/or it could be well segmented.

Quoted 2 lines

This is no longer a simple request, but some huge spaghetti changes that need to be done, mostly by volunteers.

I am not sure this "volunteers" argument really works in this discussion, since this looks like a commercial contribution to me.

But if you want to discuss volunteering, did you ever consider that I also do the USB maintaining in my free time and the bulk of communication is random people demanding random stuff ? I also don't see people coming up saying "oh, hey, I'll spend some of my own free time to help out maintaining this piece of code". It tends to make people stressed and burnt out ...

Quoted 6 lines

And at some point, it just
becomes easier to give up, fork, and just maintain our stuff like we were doing before. Or just stop maintaining it entirely. And I'm not sure either situation is something we want.
tl; dr: I'd like some moderation.

So much dramatization for a simple question which could've had equally simple answer, really.

Quoted 19 lines

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Creating a new clock driver will take a lot of effort, and this really surprise me given that we've had strictly no feedback from you on this considering all the previous SoCs bringups we've done so far.
What do you mean by "this" ? I think i did review the previous iterations of this series ? If not, was I on CC ?
You did, and thanks a lot for that. The only thing I'm noting is that it's the first time you're being so picky about a series.
Er, no, I am always picky and hard.
Quoted 6 lines
I appreciate that you have to draw the line somewhere, and when things you want in your subsystem aren't moving as fast as you'd like them to be you have to enforce new rules. But if you were unhappy about something, you never told us, which doesn't seem like a good path forward either. Even in your previous reviews of that particular series.

Quoted 6 lines

Quoted 3 lines
I think I pointed out pretty much all of it ? If I missed something, it's because it was hidden and didn't surface until the patchset got into some better shape.
And yet, this is the first time you bring up the phy and clock support.

If I missed something, it's because it was hidden and didn't surface until the patchset got into some better shape.

Quoted 6 lines

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I have to admit, I don't really care about the rest of the Allwinner SoC code or what you do there, I only care about the USB part and this poking of clock controller registers seems wrong in a DM/DT driver.
And I do agree on that. But we also have some history to carry.

Quoted 8 lines

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I also don't mind if the clock driver comes later, but I would like to see it happen at some point (soon) to remove this register poking.
Awesome then :)
Is this going to happen at some point ?
At some point, yes, but I can't give you a deadline.

That usually means never, sadly (and see * above).

Signature · 2 lines

Best regards,
Marek Vasut

Maxime Ripard

2018-05-14 09:05 UTC #14 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 29 lines · Marek Vasut

Quoted 20 lines
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Since the first post of these patches, you've asked to rework in a significant manner the driver already, including doing a new PHY driver to use the device model, and making other substantial changes to it.
Well yes, because it was crap at the beginning and I don't want to see the crap accumulating. It has become much better since, as you can see I only had a few minor comments.
Quoted 5 lines
And that's totally your role, but at the same time, the point of this series is not to fix the whole world, but rather add support for one particular SoC that is using pretty much the same design than any of our other SoCs' USB phy before. And here we are, 35 patches and counting.
Quoted 4 lines
If I said "yes" to every single patch adding just a minor additional bit of crap to the codebase, we'd be in the state in which we were in 2012, sinking under the boatload of ifdeffery and ad-hoc solutions. So I think some push is needed to avoid that situation.
Quoted 8 lines
I don't have any issue with the end goal, and your willingness to have the code ported over to new APIs. But if from one day to another every maintainer goes like this, this will simply not fly. This is not just about having just a simple clock driver, but also a pinctrl one, and converting all the consumer drivers to the device model, oh, and btw, the DM doesn't fit in the SPL anymore, so we would probably need to do an SPL driver as well. Probably with some painful Kconfig conversions all over the tree even.

Quoted 3 lines

You are massively exaggerating right there. I recently did such a conversion for a platform and it didn't take nearly as much effort as you describe and/or it could be well segmented.

rmobile? The scale isn't quite the same. It looks like there's 4 similar SoCs, with a dozen of boards supported. We have a dozen of SoCs supported, and around 120-130 boards. The clock tree looks much simpler too, and it seems like it has less drivers.

And I don't really know what the constraints are on the SPL side, but it's really tight on our end. So maybe I'm exagerating, but you're definitely understating it too.

Quoted 5 lines

Quoted 2 lines
This is no longer a simple request, but some huge spaghetti changes that need to be done, mostly by volunteers.
I am not sure this "volunteers" argument really works in this discussion, since this looks like a commercial contribution to me.

I have no idea to be honest. The maintainance however is volunteering on my side, and I'm getting a bit tired to see that every one has an agenda without any consideration about who has the time and resources to actually do it.

Quoted 6 lines

But if you want to discuss volunteering, did you ever consider that I also do the USB maintaining in my free time and the bulk of communication is random people demanding random stuff ? I also don't see people coming up saying "oh, hey, I'll spend some of my own free time to help out maintaining this piece of code". It tends to make people stressed and burnt out ...

I definitely understand and appreciate that, trust me. But the point here is that you were asking too much, so I guess my point is that you should spend *less* time reviewing stuff, which tends to make people less stressed :)

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Marek Vasut

2018-05-14 09:13 UTC #15 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 30 lines · Maxime Ripard

Quoted 29 lines · Marek Vasut
Quoted 28 lines
Quoted 15 lines
Quoted 9 lines
Quoted 8 lines
Quoted 4 lines
Since the first post of these patches, you've asked to rework in a significant manner the driver already, including doing a new PHY driver to use the device model, and making other substantial changes to it.
Well yes, because it was crap at the beginning and I don't want to see the crap accumulating. It has become much better since, as you can see I only had a few minor comments.
Quoted 5 lines
And that's totally your role, but at the same time, the point of this series is not to fix the whole world, but rather add support for one particular SoC that is using pretty much the same design than any of our other SoCs' USB phy before. And here we are, 35 patches and counting.
Quoted 4 lines
If I said "yes" to every single patch adding just a minor additional bit of crap to the codebase, we'd be in the state in which we were in 2012, sinking under the boatload of ifdeffery and ad-hoc solutions. So I think some push is needed to avoid that situation.
I don't have any issue with the end goal, and your willingness to have the code ported over to new APIs. But if from one day to another every maintainer goes like this, this will simply not fly. This is not just about having just a simple clock driver, but also a pinctrl one, and converting all the consumer drivers to the device model, oh, and btw, the DM doesn't fit in the SPL anymore, so we would probably need to do an SPL driver as well. Probably with some painful Kconfig conversions all over the tree even.

Quoted 8 lines

Quoted 3 lines
You are massively exaggerating right there. I recently did such a conversion for a platform and it didn't take nearly as much effort as you describe and/or it could be well segmented.
rmobile? The scale isn't quite the same. It looks like there's 4 similar SoCs, with a dozen of boards supported. We have a dozen of SoCs supported, and around 120-130 boards. The clock tree looks much simpler too, and it seems like it has less drivers.

Aha :)

Quoted 3 lines

And I don't really know what the constraints are on the SPL side, but it's really tight on our end. So maybe I'm exagerating, but you're definitely understating it too.

You can fit into 16k , can you not ?

Quoted 10 lines

Quoted 5 lines
Quoted 2 lines
This is no longer a simple request, but some huge spaghetti changes that need to be done, mostly by volunteers.
I am not sure this "volunteers" argument really works in this discussion, since this looks like a commercial contribution to me.
I have no idea to be honest. The maintainance however is volunteering on my side, and I'm getting a bit tired to see that every one has an agenda without any consideration about who has the time and resources to actually do it.

My agenda is to make sure upstream doesn't become a swamp.

Quoted 9 lines

Quoted 6 lines
But if you want to discuss volunteering, did you ever consider that I also do the USB maintaining in my free time and the bulk of communication is random people demanding random stuff ? I also don't see people coming up saying "oh, hey, I'll spend some of my own free time to help out maintaining this piece of code". It tends to make people stressed and burnt out ...
I definitely understand and appreciate that, trust me. But the point here is that you were asking too much

I was asking a question, is that too much nowadays ? I thought we cleared that point in this thread before.

Quoted 3 lines

, so I guess my point is that you
should spend *less* time reviewing stuff, which tends to make people less stressed :)

Not sure I understand this remark. I guess it doesn't fit my agenda.

Signature · 2 lines

Best regards,
Marek Vasut

Maxime Ripard

2018-05-18 11:51 UTC #16 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 5 lines · Marek Vasut

Quoted 3 lines
And I don't really know what the constraints are on the SPL side, but it's really tight on our end. So maybe I'm exagerating, but you're definitely understating it too.
You can fit into 16k , can you not ?

We have 13k.

Quoted 6 lines

Quoted 6 lines
Quoted 5 lines
Quoted 2 lines
This is no longer a simple request, but some huge spaghetti changes that need to be done, mostly by volunteers.
I am not sure this "volunteers" argument really works in this discussion, since this looks like a commercial contribution to me.

Quoted 6 lines

Quoted 4 lines
I have no idea to be honest. The maintainance however is volunteering on my side, and I'm getting a bit tired to see that every one has an agenda without any consideration about who has the time and resources to actually do it.
My agenda is to make sure upstream doesn't become a swamp.

And it will become less of a swamp with those patches with the phy conversion, so you can tick that on your checklist I guess?

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Marek Vasut

2018-05-18 11:55 UTC #17 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 8 lines · Maxime Ripard

Quoted 5 lines · Marek Vasut
Quoted 3 lines
And I don't really know what the constraints are on the SPL side, but it's really tight on our end. So maybe I'm exagerating, but you're definitely understating it too.
You can fit into 16k , can you not ?
We have 13k.

Yuck, in total or for code/data ?
Seems very similar to CI20.

Quoted 11 lines

Quoted 11 lines
Quoted 10 lines
Quoted 5 lines
Quoted 2 lines
This is no longer a simple request, but some huge spaghetti changes that need to be done, mostly by volunteers.
I am not sure this "volunteers" argument really works in this discussion, since this looks like a commercial contribution to me.
I have no idea to be honest. The maintainance however is volunteering on my side, and I'm getting a bit tired to see that every one has an agenda without any consideration about who has the time and resources to actually do it.

Quoted 4 lines

Quoted 1 line
My agenda is to make sure upstream doesn't become a swamp.
And it will become less of a swamp with those patches with the phy conversion, so you can tick that on your checklist I guess?

I think so

Signature · 2 lines

Best regards,
Marek Vasut

Maxime Ripard

2018-05-18 15:32 UTC #18 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Maxime Ripard
Quoted 4 lines · Marek Vasut
Quoted 3 lines
And I don't really know what the constraints are on the SPL side, but it's really tight on our end. So maybe I'm exagerating, but you're definitely understating it too.

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
You can fit into 16k , can you not ?
We have 13k.
Yuck, in total or for code/data ?
Seems very similar to CI20.

It's the size of the SRAM, so total.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-05-08 06:26 UTC #19 lore raw

PATCH v7 6/35 musb: sunxi: Add OTG device clkgate and reset for H3/H5

In reply to Marek Vasut

Hi Marek,

Quoted 6 lines · Marek Vasut

Quoted 3 lines · Jagan Teki
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by Jagan Teki <[email protected]>
Why don't you implement a clock driver for this SoC instead ?

As of now we are unable to get pinctrl, clock and reset details from DT since the dm code on these will add it in future and the same I have mentioned in the cover-letter patch. Since Allwinner is big SOC's collection along with numerous amount of boards, and shortage of binary size (with few SOC's) we need to be careful while adding these features and which obviously taking some amount of time. Hope you understand.

Jagan.

Jagan Teki

author

2018-05-07 07:33 UTC #20 lore raw

PATCH v7 7/35 musb: sunxi: Use BIT instead of numerical shift

In reply to Jagan Teki

Use BIT is possible areas instead of numerical shift.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/musb-new/sunxi.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

drivers/usb/musb-new/sunxi.c +14 ~~-14~~

index e79d7a2774..16551c7cf8 100644
@@ -94,9 +94,9 @@ static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
 {
 	u32 temp = reg_val;
 
-	temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
-	temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
-	temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
+	temp &= ~BIT(USBC_BP_ISCR_VBUS_CHANGE_DETECT);
+	temp &= ~BIT(USBC_BP_ISCR_ID_CHANGE_DETECT);
+	temp &= ~BIT(USBC_BP_ISCR_DPDM_CHANGE_DETECT);
 
 	return temp;
 }

@@ -106,7 +106,7 @@ static void USBC_EnableIdPullUp(__iomem void *base)
 	u32 reg_val;
 
 	reg_val = musb_readl(base, USBC_REG_o_ISCR);
-	reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
+	reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN);
 	reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
 	musb_writel(base, USBC_REG_o_ISCR, reg_val);
 }

@@ -116,7 +116,7 @@ static void USBC_EnableDpDmPullUp(__iomem void *base)
 	u32 reg_val;
 
 	reg_val = musb_readl(base, USBC_REG_o_ISCR);
-	reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
+	reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN);
 	reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
 	musb_writel(base, USBC_REG_o_ISCR, reg_val);
 }

@@ -172,7 +172,7 @@ static void USBC_ConfigFIFO_Base(void)
 	/* config usb fifo, 8kb mode */
 	reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
 	reg_value &= ~(0x03 << 0);
-	reg_value |= (1 << 0);
+	reg_value |= BIT(0);
 	writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
 }

@@ -276,15 +276,15 @@ static int sunxi_musb_init(struct musb *musb)
 
 	musb->isr = sunxi_musb_interrupt;
 
-	setbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+	setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
 	if (glue->cfg->clkgate_bit)
 		setbits_le32(&glue->ccm->ahb_gate0,
-			     1 << glue->cfg->clkgate_bit);
+			     BIT(glue->cfg->clkgate_bit));
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+	setbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
 	if (glue->cfg->rst_bit)
 		setbits_le32(&glue->ccm->ahb_reset0_cfg,
-			     1 << glue->cfg->rst_bit);
+			     BIT(glue->cfg->rst_bit));
 #endif
 
 	sunxi_usb_phy_init(0);

@@ -416,15 +416,15 @@ static int musb_usb_remove(struct udevice *dev)
 
 	sunxi_usb_phy_exit(0);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	clrbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+	clrbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
 	if (glue->cfg->rst_bit)
 		clrbits_le32(&glue->ccm->ahb_reset0_cfg,
-			     1 << glue->cfg->rst_bit);
+			     BIT(glue->cfg->rst_bit));
 #endif
-	clrbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+	clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
 	if (glue->cfg->clkgate_bit)
 		clrbits_le32(&glue->ccm->ahb_gate0,
-			     1 << glue->cfg->clkgate_bit);
+			     BIT(glue->cfg->clkgate_bit));
 
 	free(host->host);
 	host->host = NULL;

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #21 lore raw

PATCH v7 8/35 sunxi: clock: Fix OHCI clock gating for H3/H5

In reply to Jagan Teki

From: Chen-Yu Tsai <[email protected]>

Clock gating bits on H43/H5 were wrong, fix them.

Signed-off-by Chen-Yu Tsai <[email protected]>

Reviewed-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +4 -7

index c5dea45985..6fa6cf40ee 100644
@@ -351,13 +351,10 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
-#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
 #else
 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #22 lore raw

PATCH v7 9/35 musb: sunxi: Add support for H3/H5A64

In reply to Jagan Teki

Like other Allwinner SoC, the H3/H5/A64 is missing the config register from the musb hardware block. Use a known working value for it like other SoC.

Signed-off-by Jagan Teki <[email protected]>

---
Note:
- About previous version comment, at this point the core can't handle this through dt becuase musb-new/musb_core.c not as clean as Linux.

 drivers/usb/musb-new/musb_regs.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/usb/musb-new/musb_regs.h +2 -1

index a3cc38e3b9..a6a491ad67 100644
@@ -432,7 +432,8 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
 
 static inline u8 musb_read_configdata(void __iomem *mbase)
 {
-#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T
+#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T || \
+		defined CONFIG_MACH_SUNXI_H3_H5 || defined CONFIG_MACH_SUN50I
 	/* <Sigh> allwinner saves a reg, and we need to hardcode this */
 	return 0xde;
 #else

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #23 lore raw

PATCH v7 10/35 phy: Add Allwinner A64 USB PHY driver

In reply to Jagan Teki

USB PHY implementation for Allwinner SOC's can be handling in to single driver with different phy configs.

This driver handle all Allwinner USB PHY's start from 4I to 50I(except 9I). Currently added A64 compatibility more will add in next coming patches.

Current implementation is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future.

Driver named as phy-sun4i-usb.c since the same PHY logic work for all Allwinner SOC's start from 4I to A64 except 9I with different phy configurations.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/Kconfig                       |   2 +
 drivers/Makefile                      |   1 +
 drivers/phy/allwinner/Kconfig         |  13 ++
 drivers/phy/allwinner/Makefile        |   6 +
 drivers/phy/allwinner/phy-sun4i-usb.c | 400 ++++++++++++++++++++++++++++++++++
 5 files changed, 422 insertions(+)
 create mode 100644 drivers/phy/allwinner/Kconfig
 create mode 100644 drivers/phy/allwinner/Makefile
 create mode 100644 drivers/phy/allwinner/phy-sun4i-usb.c

drivers/Kconfig +2 -0

index c2e813f5ad..9af883528d 100644
@@ -60,6 +60,8 @@ source "drivers/pcmcia/Kconfig"
 
 source "drivers/phy/Kconfig"
 
+source "drivers/phy/allwinner/Kconfig"
+
 source "drivers/phy/marvell/Kconfig"
 
 source "drivers/pinctrl/Kconfig"

drivers/Makefile +1 -0

index 6846d181aa..71fee4f8a0 100644
@@ -80,6 +80,7 @@ obj-$(CONFIG_NVME) += nvme/
 obj-y += pcmcia/
 obj-y += dfu/
 obj-$(CONFIG_X86) += pch/
+obj-y += phy/allwinner/
 obj-y += phy/marvell/
 obj-y += rtc/
 obj-y += scsi/

drivers/phy/allwinner/Kconfig new file +13 -0

new file mode 100644
index 0000000000..dba3bae61c
@@ -0,0 +1,13 @@
+#
+# Phy drivers for Allwinner platforms
+#
+config PHY_SUN4I_USB
+	bool "Allwinner Sun4I USB PHY driver"
+	depends on ARCH_SUNXI
+	select PHY
+	help
+	  Enable this to support the transceiver that is part of Allwinner
+	  sunxi SoCs.
+
+	  This driver controls the entire USB PHY block, both the USB OTG
+	  parts, as well as the 2 regular USB 2 host PHYs.

drivers/phy/allwinner/Makefile new file +6 -0

new file mode 100644
index 0000000000..5ed2702e4f
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o

drivers/phy/allwinner/phy-sun4i-usb.c new file +400 -0

400 lines not on this page · raw message

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #24 lore raw

PATCH v7 11/35 phy: sun4i-usb: Add id_detect and vbus_detect ops

In reply to Jagan Teki

ID and VBUS detection code require when musb changing between Host and/or Peripheral modes.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 39 +++++++++++++++++++++++++++++++++++
 include/phy-sun4i-usb.h               | 26 +++++++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 include/phy-sun4i-usb.h

drivers/phy/allwinner/phy-sun4i-usb.c +39 -0

index 78304c1f22..7f2970b96b 100644
@@ -14,6 +14,7 @@
 #include <dm.h>
 #include <dm/device.h>
 #include <generic-phy.h>
+#include <phy-sun4i-usb.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>

@@ -295,6 +296,44 @@ static int sun4i_usb_phy_xlate(struct phy *phy,
 	return 0;
 }
 
+int sun4i_usb_phy_vbus_detect(struct phy *phy)
+{
+	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
+	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+	int err, retries = 3;
+
+	debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
+
+	if (usb_phy->gpio_vbus_det < 0)
+		return usb_phy->gpio_vbus_det;
+
+	err = gpio_get_value(usb_phy->gpio_vbus_det);
+	/*
+	 * Vbus may have been provided by the board and just been turned of
+	 * some milliseconds ago on reset, what we're measuring then is a
+	 * residual charge on Vbus, sleep a bit and try again.
+	 */
+	while (err > 0 && retries--) {
+		mdelay(100);
+		err = gpio_get_value(usb_phy->gpio_vbus_det);
+	}
+
+	return err;
+}
+
+int sun4i_usb_phy_id_detect(struct phy *phy)
+{
+	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
+	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+
+	debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
+
+	if (usb_phy->gpio_id_det < 0)
+		return usb_phy->gpio_id_det;
+
+	return gpio_get_value(usb_phy->gpio_id_det);
+}
+
 static struct phy_ops sun4i_usb_phy_ops = {
 	.of_xlate = sun4i_usb_phy_xlate,
 	.init = sun4i_usb_phy_init,

include/phy-sun4i-usb.h new file +26 -0

new file mode 100644
index 0000000000..040e9d3750
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __GENERIC_PHY_SUN4I_USB_H
+#define __GENERIC_PHY_SUN4I_USB_H
+
+/**
+ * sun4i_usb_phy_id_detect - detect ID pin of USB PHY
+ *
+ * @phy:	USB PHY port to detect ID pin
+ * @return 0 if OK, or a negative error code
+ */
+int sun4i_usb_phy_id_detect(struct phy *phy);
+
+/**
+ * sun4i_usb_phy_vbus_detect - detect VBUS pin of USB PHY
+ *
+ * @phy:	USB PHY port to detect VBUS pin
+ * @return 0 if OK, or a negative error code
+ */
+int sun4i_usb_phy_vbus_detect(struct phy *phy);
+
+#endif /*__GENERIC_PHY_SUN4I_USB_H */

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #25 lore raw

PATCH v7 12/35 phy: sun4i-usb: Add H3/H5 PHY config

In reply to Jagan Teki

H3/H5 has 4 USB PHY, rest are similar to A64.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/phy/allwinner/phy-sun4i-usb.c +11 -0

index 7f2970b96b..993f036b78 100644
@@ -56,6 +56,7 @@
 #define MAX_PHYS			4
 
 enum sun4i_usb_phy_type {
+	sun8i_h3_phy,
 	sun50i_a64_phy,
 };

@@ -414,6 +415,15 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 	return 0;
 }
 
+static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
+	.num_phys = 4,
+	.type = sun8i_h3_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.enable_pmu_unk1 = true,
+	.phy0_dual_route = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.num_phys = 2,
 	.type = sun50i_a64_phy,

@@ -424,6 +434,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 };
 
 static const struct udevice_id sun4i_usb_phy_ids[] = {
+	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 	{ }
 };

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #26 lore raw

PATCH v7 13/35 phy: sun4i-usb: Add V3S PHY config

In reply to Jagan Teki

V3S has 1 USB PHY, rest are similar to A64.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/phy/allwinner/phy-sun4i-usb.c +11 -0

index 993f036b78..de0a59a32c 100644
@@ -57,6 +57,7 @@
 
 enum sun4i_usb_phy_type {
 	sun8i_h3_phy,
+	sun8i_v3s_phy,
 	sun50i_a64_phy,
 };

@@ -424,6 +425,15 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.phy0_dual_route = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
+	.num_phys = 1,
+	.type = sun8i_v3s_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.enable_pmu_unk1 = true,
+	.phy0_dual_route = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.num_phys = 2,
 	.type = sun50i_a64_phy,

@@ -435,6 +445,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 
 static const struct udevice_id sun4i_usb_phy_ids[] = {
 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
+	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 	{ }
 };

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #27 lore raw

PATCH v7 14/35 phy: sun4i-usb: Add A83T USB PHY config

In reply to Jagan Teki

Unlike, other Allwinner SUN4I Phy supporting SOC, A83T has 2 USB PHY's and second one is HSIC. So phy control need to configure to handle these HSIC and SIDDQ requirement.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 85 ++++++++++++++++++++++++++++-------
 1 file changed, 68 insertions(+), 17 deletions(-)

drivers/phy/allwinner/phy-sun4i-usb.c +68 ~~-17~~

index de0a59a32c..01782ac97c 100644
@@ -53,9 +53,19 @@
 #define SUNXI_AHB_INCRX_ALIGN_EN	BIT(8)
 #define SUNXI_ULPI_BYPASS_EN		BIT(0)
 
+/* A83T specific control bits for PHY0 */
+#define PHY_CTL_VBUSVLDEXT		BIT(5)
+#define PHY_CTL_SIDDQ			BIT(3)
+
+/* A83T specific control bits for PHY2 HSIC */
+#define SUNXI_EHCI_HS_FORCE		BIT(20)
+#define SUNXI_HSIC_CONNECT_INT		BIT(16)
+#define SUNXI_HSIC			BIT(1)
+
 #define MAX_PHYS			4
 
 enum sun4i_usb_phy_type {
+	sun8i_a83t_phy,
 	sun8i_h3_phy,
 	sun8i_v3s_phy,
 	sun50i_a64_phy,

@@ -92,13 +102,20 @@ struct sun4i_usb_phy_info {
 		.gpio_vbus = CONFIG_USB2_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
+#ifdef CONFIG_MACH_SUN8I_A83T
+		.rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
+			     CCM_USB_CTRL_12M_CLK),
+#else
 		.rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
+#endif
 	},
 	{
 		.gpio_vbus = CONFIG_USB3_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
+#ifdef CONFIG_MACH_SUN6I
 		.rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
+#endif
 	},
 };

@@ -166,9 +183,10 @@ static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 	}
 }
 
-static void sun4i_usb_phy_passby(struct sun4i_usb_phy_plat *usb_phy,
-				 bool enable)
+static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 {
+	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
+	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 	u32 bits, reg_value;
 
 	if (!usb_phy->pmu)

@@ -176,6 +194,12 @@ static void sun4i_usb_phy_passby(struct sun4i_usb_phy_plat *usb_phy,
 
 	bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 		SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
+
+	/* A83T USB2 is HSIC */
+	if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
+		bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
+			SUNXI_HSIC;
+
 	reg_value = readl(usb_phy->pmu);
 
 	if (enable)

@@ -244,25 +268,36 @@ static int sun4i_usb_phy_init(struct phy *phy)
 
 	setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 
-	if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
-		val = readl(usb_phy->pmu + REG_PMU_UNK1);
-		writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
-	}
+	if (data->cfg->type == sun8i_a83t_phy) {
+		if (phy->id == 0) {
+			val = readl(data->base + data->cfg->phyctl_offset);
+			val |= PHY_CTL_VBUSVLDEXT;
+			val &= ~PHY_CTL_SIDDQ;
+			writel(val, data->base + data->cfg->phyctl_offset);
+		}
+	} else {
+		if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
+			val = readl(usb_phy->pmu + REG_PMU_UNK1);
+			writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
+		}
 
-	if (usb_phy->id == 0)
-		sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, PHY_RES45_CAL_DATA,
-				    PHY_RES45_CAL_LEN);
+		if (usb_phy->id == 0)
+			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
+					    PHY_RES45_CAL_DATA,
+					    PHY_RES45_CAL_LEN);
 
-	/* Adjust PHY's magnitude and rate */
-	sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, PHY_TX_MAGNITUDE |
-			    PHY_TX_RATE, PHY_TX_AMPLITUDE_LEN);
+		/* Adjust PHY's magnitude and rate */
+		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
+				    PHY_TX_MAGNITUDE | PHY_TX_RATE,
+				    PHY_TX_AMPLITUDE_LEN);
 
-	/* Disconnect threshold adjustment */
-	sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->cfg->disc_thresh,
-			    PHY_DISCON_TH_LEN);
+		/* Disconnect threshold adjustment */
+		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+				    data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
+	}
 
 	if (usb_phy->id != 0)
-		sun4i_usb_phy_passby(usb_phy, true);
+		sun4i_usb_phy_passby(phy, true);
 
 	sun4i_usb_phy0_reroute(data, true);

@@ -274,7 +309,16 @@ static int sun4i_usb_phy_exit(struct phy *phy)
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 
-	sun4i_usb_phy_passby(usb_phy, false);
+	if (phy->id == 0) {
+		if (data->cfg->type == sun8i_a83t_phy) {
+			void __iomem *phyctl = data->base +
+				data->cfg->phyctl_offset;
+
+			writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
+		}
+	}
+
+	sun4i_usb_phy_passby(phy, false);
 
 	clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);

@@ -416,6 +460,12 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 	return 0;
 }
 
+static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
+	.num_phys = 3,
+	.type = sun8i_a83t_phy,
+	.phyctl_offset = REG_PHYCTL_A33,
+};
+
 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.num_phys = 4,
 	.type = sun8i_h3_phy,

@@ -444,6 +494,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 };
 
 static const struct udevice_id sun4i_usb_phy_ids[] = {
+	{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #28 lore raw

PATCH v7 15/35 phy: sun4i-usb: Add A10/A13/A20 PHY config

In reply to Jagan Teki

Add PHY configs for Allwinner A10/A13/A20 which are SUN4I.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

drivers/phy/allwinner/phy-sun4i-usb.c +28 -0

index 01782ac97c..abb3d0f055 100644
@@ -65,6 +65,7 @@
 #define MAX_PHYS			4
 
 enum sun4i_usb_phy_type {
+	sun4i_a10_phy,
 	sun8i_a83t_phy,
 	sun8i_h3_phy,
 	sun8i_v3s_phy,

@@ -460,6 +461,30 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 	return 0;
 }
 
+static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
+	.num_phys = 3,
+	.type = sun4i_a10_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.enable_pmu_unk1 = false,
+};
+
+static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
+	.num_phys = 2,
+	.type = sun4i_a10_phy,
+	.disc_thresh = 2,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.enable_pmu_unk1 = false,
+};
+
+static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
+	.num_phys = 3,
+	.type = sun4i_a10_phy,
+	.disc_thresh = 2,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.enable_pmu_unk1 = false,
+};
+
 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 	.num_phys = 3,
 	.type = sun8i_a83t_phy,

@@ -494,6 +519,9 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 };
 
 static const struct udevice_id sun4i_usb_phy_ids[] = {
+	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
+	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
+	{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 	{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #29 lore raw

PATCH v7 16/35 phy: sun4i-usb: Add A31 PHY config

In reply to Jagan Teki

Allwinner A31 has 3 USB PHY's and rest similar to A10.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

drivers/phy/allwinner/phy-sun4i-usb.c +10 -0

index abb3d0f055..16b399e880 100644
@@ -66,6 +66,7 @@
 
 enum sun4i_usb_phy_type {
 	sun4i_a10_phy,
+	sun6i_a31_phy,
 	sun8i_a83t_phy,
 	sun8i_h3_phy,
 	sun8i_v3s_phy,

@@ -477,6 +478,14 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 	.enable_pmu_unk1 = false,
 };
 
+static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
+	.num_phys = 3,
+	.type = sun6i_a31_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.enable_pmu_unk1 = false,
+};
+
 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.num_phys = 3,
 	.type = sun4i_a10_phy,

@@ -521,6 +530,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 static const struct udevice_id sun4i_usb_phy_ids[] = {
 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
+	{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 	{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 	{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #30 lore raw

PATCH v7 17/35 phy: sun4i-usb: Add A33 USB PHY config

In reply to Jagan Teki

Allwinner A33 has 2 USB PHY's and 0x10 has phy ctrl offset.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

drivers/phy/allwinner/phy-sun4i-usb.c +10 -0

index 16b399e880..75056e250c 100644
@@ -67,6 +67,7 @@
 enum sun4i_usb_phy_type {
 	sun4i_a10_phy,
 	sun6i_a31_phy,
+	sun8i_a33_phy,
 	sun8i_a83t_phy,
 	sun8i_h3_phy,
 	sun8i_v3s_phy,

@@ -494,6 +495,14 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.enable_pmu_unk1 = false,
 };
 
+static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
+	.num_phys = 2,
+	.type = sun8i_a33_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.enable_pmu_unk1 = false,
+};
+
 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 	.num_phys = 3,
 	.type = sun8i_a83t_phy,

@@ -532,6 +541,7 @@ static const struct udevice_id sun4i_usb_phy_ids[] = {
 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 	{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 	{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
+	{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
 	{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #31 lore raw

PATCH v7 18/35 phy: sun4i-usb: Add A23 USB PHY config

In reply to Jagan Teki

Allwinner A23 has 2 USB PHY's and 0x04 has phy ctrl offset.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 9 +++++++++
 1 file changed, 9 insertions(+)

drivers/phy/allwinner/phy-sun4i-usb.c +9 -0

index 75056e250c..4194a15007 100644
@@ -495,6 +495,14 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.enable_pmu_unk1 = false,
 };
 
+static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
+	.num_phys = 2,
+	.type = sun4i_a10_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A10,
+	.enable_pmu_unk1 = false,
+};
+
 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 	.num_phys = 2,
 	.type = sun8i_a33_phy,

@@ -541,6 +549,7 @@ static const struct udevice_id sun4i_usb_phy_ids[] = {
 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 	{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
 	{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
+	{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
 	{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
 	{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #32 lore raw

PATCH v7 19/35 device-tree-bindings: phy: Sync sun4i-usb-phy bindings

In reply to Jagan Teki

Sync sun4i-usb-phy bindings from Linux, since the drivers/phy/allwinner/phy-sun4i-usb.c follw similar.

Signed-off-by Jagan Teki <[email protected]>

---
 doc/device-tree-bindings/phy/sun4i-usb-phy.txt | 65 ++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 doc/device-tree-bindings/phy/sun4i-usb-phy.txt

doc/device-tree-bindings/phy/sun4i-usb-phy.txt new file +65 -0

new file mode 100644
index 0000000000..c1ce5a0a65
@@ -0,0 +1,65 @@
+Allwinner sun4i USB PHY
+-----------------------
+
+Required properties:
+- compatible : should be one of
+  * allwinner,sun4i-a10-usb-phy
+  * allwinner,sun5i-a13-usb-phy
+  * allwinner,sun6i-a31-usb-phy
+  * allwinner,sun7i-a20-usb-phy
+  * allwinner,sun8i-a23-usb-phy
+  * allwinner,sun8i-a33-usb-phy
+  * allwinner,sun8i-a83t-usb-phy
+  * allwinner,sun8i-h3-usb-phy
+  * allwinner,sun8i-v3s-usb-phy
+  * allwinner,sun50i-a64-usb-phy
+- reg : a list of offset + length pairs
+- reg-names :
+  * "phy_ctrl"
+  * "pmu0" for H3, V3s and A64
+  * "pmu1"
+  * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
+  * "pmu3" for sun8i-h3
+- #phy-cells : from the generic phy bindings, must be 1
+- clocks : phandle + clock specifier for the phy clocks
+- clock-names :
+  * "usb_phy" for sun4i, sun5i or sun7i
+  * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
+  * "usb0_phy", "usb1_phy" for sun8i
+  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
+  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
+- resets : a list of phandle + reset specifier pairs
+- reset-names :
+  * "usb0_reset"
+  * "usb1_reset"
+  * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
+  * "usb3_reset" for sun8i-h3
+
+Optional properties:
+- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
+- usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus
+- usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect
+- usb0_vbus-supply : regulator phandle for controller usb0 vbus
+- usb1_vbus-supply : regulator phandle for controller usb1 vbus
+- usb2_vbus-supply : regulator phandle for controller usb2 vbus
+- usb3_vbus-supply : regulator phandle for controller usb3 vbus
+
+Example:
+	usbphy: phy at 01c13400 {
+		#phy-cells = <1>;
+		compatible = "allwinner,sun4i-a10-usb-phy";
+		/* phy base regs, phy1 pmu reg, phy2 pmu reg */
+		reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+		reg-names = "phy_ctrl", "pmu1", "pmu2";
+		clocks = <&usb_clk 8>;
+		clock-names = "usb_phy";
+		resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+		reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+		usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
+		usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+		usb0_vbus-supply = <&reg_usb0_vbus>;
+		usb1_vbus-supply = <&reg_usb1_vbus>;
+		usb2_vbus-supply = <&reg_usb2_vbus>;
+	};

Signature · 1 line

2.14.3

Marek Vasut

2018-05-07 11:49 UTC #33 lore raw

PATCH v7 19/35 device-tree-bindings: phy: Sync sun4i-usb-phy bindings

Quoted 2 lines · Jagan Teki

Sync sun4i-usb-phy bindings from Linux, since the drivers/phy/allwinner/phy-sun4i-usb.c follw similar.

which commit in Linux does this come from ? This should be in the commit message for future reference.

Quoted 78 lines

Signed-off-by Jagan Teki <[email protected]>

---
 doc/device-tree-bindings/phy/sun4i-usb-phy.txt | 65 ++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 doc/device-tree-bindings/phy/sun4i-usb-phy.txt

doc/device-tree-bindings/phy/sun4i-usb-phy.txt new file +65 -0

new file mode 100644
index 0000000000..c1ce5a0a65
@@ -0,0 +1,65 @@
+Allwinner sun4i USB PHY
+-----------------------
+
+Required properties:
+- compatible : should be one of
+  * allwinner,sun4i-a10-usb-phy
+  * allwinner,sun5i-a13-usb-phy
+  * allwinner,sun6i-a31-usb-phy
+  * allwinner,sun7i-a20-usb-phy
+  * allwinner,sun8i-a23-usb-phy
+  * allwinner,sun8i-a33-usb-phy
+  * allwinner,sun8i-a83t-usb-phy
+  * allwinner,sun8i-h3-usb-phy
+  * allwinner,sun8i-v3s-usb-phy
+  * allwinner,sun50i-a64-usb-phy
+- reg : a list of offset + length pairs
+- reg-names :
+  * "phy_ctrl"
+  * "pmu0" for H3, V3s and A64
+  * "pmu1"
+  * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
+  * "pmu3" for sun8i-h3
+- #phy-cells : from the generic phy bindings, must be 1
+- clocks : phandle + clock specifier for the phy clocks
+- clock-names :
+  * "usb_phy" for sun4i, sun5i or sun7i
+  * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
+  * "usb0_phy", "usb1_phy" for sun8i
+  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
+  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
+- resets : a list of phandle + reset specifier pairs
+- reset-names :
+  * "usb0_reset"
+  * "usb1_reset"
+  * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
+  * "usb3_reset" for sun8i-h3
+
+Optional properties:
+- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
+- usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus
+- usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect
+- usb0_vbus-supply : regulator phandle for controller usb0 vbus
+- usb1_vbus-supply : regulator phandle for controller usb1 vbus
+- usb2_vbus-supply : regulator phandle for controller usb2 vbus
+- usb3_vbus-supply : regulator phandle for controller usb3 vbus
+
+Example:
+	usbphy: phy at 01c13400 {
+		#phy-cells = <1>;
+		compatible = "allwinner,sun4i-a10-usb-phy";
+		/* phy base regs, phy1 pmu reg, phy2 pmu reg */
+		reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+		reg-names = "phy_ctrl", "pmu1", "pmu2";
+		clocks = <&usb_clk 8>;
+		clock-names = "usb_phy";
+		resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+		reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+		usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
+		usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+		usb0_vbus-supply = <&reg_usb0_vbus>;
+		usb1_vbus-supply = <&reg_usb1_vbus>;
+		usb2_vbus-supply = <&reg_usb2_vbus>;
+	};

Signature · 2 lines

Best regards,
Marek Vasut

Jagan Teki

author

2018-05-07 07:33 UTC #34 lore raw

PATCH v7 20/35 board: sunxi: Use generic-phy for board_usb_cable_connected

In reply to Jagan Teki

Allwinner PHY USB code is now part of generic-phy framework, so use it in board_usb_cable_connected.

Signed-off-by Jagan Teki <[email protected]>

---
 board/sunxi/board.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

board/sunxi/board.c +32 -1

index 322dd9e23a..63620ea7e2 100644
@@ -12,8 +12,11 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <mmc.h>
 #include <axp_pmic.h>
+#include <generic-phy.h>
+#include <phy-sun4i-usb.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/display.h>

@@ -596,7 +599,35 @@ void sunxi_board_init(void)
 #ifdef CONFIG_USB_GADGET
 int g_dnl_board_usb_cable_connected(void)
 {
-	return sunxi_usb_phy_vbus_detect(0);
+	struct udevice *dev;
+	struct phy phy;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev);
+	if (ret) {
+		pr_err("%s: Cannot find USB device\n", __func__);
+		return ret;
+	}
+
+	ret = generic_phy_get_by_name(dev, "usb", &phy);
+	if (ret) {
+		pr_err("failed to get %s USB PHY\n", dev->name);
+		return ret;
+	}
+
+	ret = generic_phy_init(&phy);
+	if (ret) {
+		pr_err("failed to init %s USB PHY\n", dev->name);
+		return ret;
+	}
+
+	ret = sun4i_usb_phy_vbus_detect(&phy);
+	if (ret == 1) {
+		pr_err("A charger is plugged into the OTG\n");
+		return -ENODEV;
+	}
+
+	return ret;
 }
 #endif

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #35 lore raw

PATCH v7 21/35 phy: sun4i-usb: Add a sunxi specific function for setting squelch-detect

In reply to Jagan Teki

The sunxi otg phy has a bug where it wrongly detects a high speed squelch when reset on the root port gets de-asserted with a lo-speed device.

The workaround for this is to disable squelch detect before de-asserting reset, and re-enabling it after the reset de-assert is done. Add a sunxi specific phy function to allow the sunxi-musb glue to do this.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c |  6 ++++++
 drivers/usb/musb-new/musb_core.h      |  4 ++++
 drivers/usb/musb-new/musb_uboot.c     | 19 ++++++++-----------
 drivers/usb/musb-new/sunxi.c          | 16 ++++++++++++++++
 include/phy-sun4i-usb.h               |  8 ++++++++
 5 files changed, 42 insertions(+), 11 deletions(-)

drivers/phy/allwinner/phy-sun4i-usb.c +6 -0

index 4194a15007..2b3cf48025 100644
@@ -36,6 +36,7 @@
 #define PHY_TX_AMPLITUDE_TUNE		0x20
 #define PHY_TX_SLEWRATE_TUNE		0x22
 #define PHY_DISCON_TH_SEL		0x2a
+#define PHY_SQUELCH_DETECT		0x3c
 
 #define PHYCTL_DATA			BIT(7)
 #define OTGCTL_ROUTE_MUSB		BIT(0)

@@ -383,6 +384,11 @@ int sun4i_usb_phy_id_detect(struct phy *phy)
 	return gpio_get_value(usb_phy->gpio_id_det);
 }
 
+void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
+{
+	sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
+}
+
 static struct phy_ops sun4i_usb_phy_ops = {
 	.of_xlate = sun4i_usb_phy_xlate,
 	.init = sun4i_usb_phy_init,

drivers/usb/musb-new/musb_core.h +4 -0

index 6394bb052b..713a3cf30c 100644
@@ -201,6 +201,8 @@ enum musb_g_ep0_state {
  * @vbus_status: returns vbus status if possible
  * @set_vbus:	forces vbus status
  * @adjust_channel_params: pre check for standard dma channel_program func
+ * @pre_root_reset_end: called before the root usb port reset flag gets cleared
+ * @post_root_reset_end: called after the root usb port reset flag gets cleared
  */
 struct musb_platform_ops {
 	int	(*init)(struct musb *musb);

@@ -222,6 +224,8 @@ struct musb_platform_ops {
 	int	(*adjust_channel_params)(struct dma_channel *channel,
 				u16 packet_sz, u8 *mode,
 				dma_addr_t *dma_addr, u32 *len);
+	void	(*pre_root_reset_end)(struct musb *musb);
+	void	(*post_root_reset_end)(struct musb *musb);
 };
 
 /*

drivers/usb/musb-new/musb_uboot.c +8 ~~-11~~

index 8662c0ff70..48242c0475 100644
@@ -193,19 +193,16 @@ static int _musb_reset_root_port(struct musb_host_data *host,
 	power &= 0xf0;
 	musb_writeb(mbase, MUSB_POWER, MUSB_POWER_RESET | power);
 	mdelay(50);
-#ifdef CONFIG_ARCH_SUNXI
-	/*
-	 * sunxi phy has a bug and it will wrongly detect high speed squelch
-	 * when clearing reset on low-speed devices, temporary disable
-	 * squelch detection to work around this.
-	 */
-	sunxi_usb_phy_enable_squelch_detect(0, 0);
-#endif
+
+	if (host->host->ops->pre_root_reset_end)
+		host->host->ops->pre_root_reset_end(host->host);
+
 	power = musb_readb(mbase, MUSB_POWER);
 	musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power);
-#ifdef CONFIG_ARCH_SUNXI
-	sunxi_usb_phy_enable_squelch_detect(0, 1);
-#endif
+
+	if (host->host->ops->post_root_reset_end)
+		host->host->ops->post_root_reset_end(host->host);
+
 	host->host->isr(0, host->host);
 	host->host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ?
 			USB_SPEED_HIGH :

drivers/usb/musb-new/sunxi.c +16 -0

index 16551c7cf8..349653cd33 100644
@@ -305,10 +305,26 @@ static int sunxi_musb_init(struct musb *musb)
 	return 0;
 }
 
+static void sunxi_musb_pre_root_reset_end(struct musb *musb)
+{
+	struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
+
+	sun4i_usb_phy_set_squelch_detect(glue->phy, false);
+}
+
+static void sunxi_musb_post_root_reset_end(struct musb *musb)
+{
+	struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
+
+	sun4i_usb_phy_set_squelch_detect(glue->phy, true);
+}
+
 static const struct musb_platform_ops sunxi_musb_ops = {
 	.init		= sunxi_musb_init,
 	.enable		= sunxi_musb_enable,
 	.disable	= sunxi_musb_disable,
+	.pre_root_reset_end = sunxi_musb_pre_root_reset_end,
+	.post_root_reset_end = sunxi_musb_post_root_reset_end,
 };
 
 /* Allwinner OTG supports up to 5 endpoints */

include/phy-sun4i-usb.h +8 -0

index 040e9d3750..b0a45b2058 100644
@@ -23,4 +23,12 @@ int sun4i_usb_phy_id_detect(struct phy *phy);
  */
 int sun4i_usb_phy_vbus_detect(struct phy *phy);
 
+/**
+ * sun4i_usb_phy_set_squelch_detect() - Enable/disable squelch detect
+ *
+ * @phy: reference to a sun4i usb phy
+ * @enabled: wether to enable or disable squelch detect
+ */
+void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled);
+
 #endif /*__GENERIC_PHY_SUN4I_USB_H */

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #36 lore raw

PATCH v7 22/35 usb: sunxi: Switch to use generic-phy

In reply to Jagan Teki

Allwinner USB PHY handling can be done through driver-model generic-phy so add the generic-phy ops to relevant places on host and musb sunxi driver and enable them in respective SOC's.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig       |  9 +++++++
 drivers/usb/host/ehci-sunxi.c     | 51 ++++++++++++++++++++++++++---------
 drivers/usb/host/ohci-sunxi.c     | 53 ++++++++++++++++++++++++++----------
 drivers/usb/musb-new/musb_uboot.c |  3 ---
 drivers/usb/musb-new/sunxi.c      | 56 ++++++++++++++++++++++++++++++++-------
 5 files changed, 133 insertions(+), 39 deletions(-)

arch/arm/mach-sunxi/Kconfig +9 -0

index b868f0e350..0a7bd3086a 100644
@@ -124,6 +124,7 @@ endif
 config MACH_SUNXI_H3_H5
 	bool
 	select DM_I2C
+	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT

@@ -138,6 +139,7 @@ config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7
 	select ARM_CORTEX_CPU_IS_UP
+	select PHY_SUN4I_USB
 	select DRAM_SUN4I
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL

@@ -147,6 +149,7 @@ config MACH_SUN5I
 	select CPU_V7
 	select ARM_CORTEX_CPU_IS_UP
 	select DRAM_SUN4I
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	imply CONS_INDEX_2 if !DM_SERIAL

@@ -158,6 +161,7 @@ config MACH_SUN6I
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN6I
+	select PHY_SUN4I_USB
 	select SUN6I_P2WI
 	select SUN6I_PRCM
 	select SUNXI_GEN_SUN6I

@@ -171,6 +175,7 @@ config MACH_SUN7I
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN4I
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

@@ -182,6 +187,7 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A23
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

@@ -194,6 +200,7 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A33
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

@@ -203,6 +210,7 @@ config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7
 	select DRAM_SUN8I_A83T
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select MMC_SUNXI_HAS_NEW_MODE
 	select SUPPORT_SPL

@@ -253,6 +261,7 @@ config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
 	select DM_I2C
+	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I
 	select SUNXI_HIGH_SRAM

drivers/usb/host/ehci-sunxi.c +38 ~~-13~~

103 lines not on this page · raw message

drivers/usb/host/ohci-sunxi.c +39 ~~-14~~

106 lines not on this page · raw message

drivers/usb/musb-new/musb_uboot.c +0 -3

index 48242c0475..2b04fbd046 100644
@@ -1,9 +1,6 @@
 #include <common.h>
 #include <console.h>
 #include <watchdog.h>
-#ifdef CONFIG_ARCH_SUNXI
-#include <asm/arch/usb_phy.h>
-#endif
 #include <linux/errno.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>

drivers/usb/musb-new/sunxi.c +47 -9

138 lines not on this page · raw message

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #37 lore raw

PATCH v7 23/35 sunxi: Drop legacy usb_phy.c

In reply to Jagan Teki

Allwinner PHY USB code is now part of generic-phy framework, so drop existing legacy handling like arch/arm/mach-sunxi.c and related code areas.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/usb_phy.h |  21 --
 arch/arm/mach-sunxi/Makefile              |   3 -
 arch/arm/mach-sunxi/usb_phy.c             | 407 ------------------------------
 board/sunxi/board.c                       |   7 -
 4 files changed, 438 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-sunxi/usb_phy.h
 delete mode 100644 arch/arm/mach-sunxi/usb_phy.c

arch/arm/include/asm/arch-sunxi/usb_phy.h deleted +0 ~~-21~~

deleted file mode 100644
index 5a9cacb6f4..0000000000
@@ -1,21 +0,0 @@
-/*
- * Sunxi usb-phy code
- *
- * Copyright (C) 2015 Hans de Goede <[email protected]>
- * Copyright (C) 2014 Roman Byshko <[email protected]>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-int sunxi_usb_phy_probe(void);
-int sunxi_usb_phy_remove(void);
-void sunxi_usb_phy_init(int index);
-void sunxi_usb_phy_exit(int index);
-void sunxi_usb_phy_power_on(int index);
-void sunxi_usb_phy_power_off(int index);
-int sunxi_usb_phy_vbus_detect(int index);
-int sunxi_usb_phy_id_detect(int index);
-void sunxi_usb_phy_enable_squelch_detect(int index, int enable);

arch/arm/mach-sunxi/Makefile +0 -3

index 183175340a..41f047f89e 100644
@@ -13,9 +13,6 @@ obj-y	+= clock.o
 obj-y	+= cpu_info.o
 obj-y	+= dram_helpers.o
 obj-y	+= pinmux.o
-ifndef CONFIG_MACH_SUN9I
-obj-y	+= usb_phy.o
-endif
 obj-$(CONFIG_SUN6I_P2WI)	+= p2wi.o
 obj-$(CONFIG_SUN6I_PRCM)	+= prcm.o
 obj-$(CONFIG_AXP_PMIC_BUS)	+= pmic_bus.o

arch/arm/mach-sunxi/usb_phy.c deleted +0 ~~-407~~

407 lines not on this page · raw message

board/sunxi/board.c +0 -7

index 63620ea7e2..a5789090c0 100644
@@ -24,7 +24,6 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/spl.h>
-#include <asm/arch/usb_phy.h>
 #ifndef CONFIG_ARM64
 #include <asm/armv7.h>
 #endif

@@ -775,12 +774,6 @@ int misc_init_r(void)
 
 	setup_environment(gd->fdt_blob);
 
-#ifndef CONFIG_MACH_SUN9I
-	ret = sunxi_usb_phy_probe();
-	if (ret)
-		return ret;
-#endif
-
 #ifdef CONFIG_USB_ETHER
 	usb_ether_init();
 #endif

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #38 lore raw

PATCH v7 24/35 sunxi: h3: Sync OTG and HCI nodes from Linux DT

In reply to Jagan Teki

From: Jun Nie <[email protected]>

Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller.

Signed-off-by Jun Nie <[email protected]>

Reviewed-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

arch/arm/dts/sun8i-h3.dtsi +32 -0

index d9d31fa3f5..1df6ca4f31 100644
@@ -219,6 +219,19 @@
 			#size-cells = <0>;
 		};
 
+		usb_otg: usb at 1c19000 {
+			compatible = "allwinner,sun8i-h3-musb";
+			reg = <0x01c19000 0x400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			status = "disabled";
+		};
+
 		usbphy: phy at 01c19400 {
 			compatible = "allwinner,sun8i-h3-usb-phy";
 			reg = <0x01c19400 0x2c>,

@@ -251,6 +264,25 @@
 			#phy-cells = <1>;
 		};
 
+		ehci0: usb at 1c1a000 {
+			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+			reg = <0x01c1a000 0x100>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
+		ohci0: usb at 1c1a400 {
+			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+			reg = <0x01c1a400 0x100>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
 		ehci1: usb at 01c1b000 {
 			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 			reg = <0x01c1b000 0x100>;

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #39 lore raw

PATCH v7 25/35 arm64: allwinner: a64: bananapi-m64: Sync usb_otg node from Linux

In reply to Jagan Teki

Sync bananapi-m64 usb_otg node from Linux.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun50i-a64-bananapi-m64.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

arch/arm/dts/sun50i-a64-bananapi-m64.dts +10 -0

index 02db114113..80405e5b26 100644
@@ -119,3 +119,13 @@
 	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
 	status = "okay";
 };
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+	status = "okay";
+};

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #40 lore raw

PATCH v7 26/35 configs: bananapi-m64: Enable USB OTG peripheral mode

In reply to Jagan Teki

Enable USB_MUSB_GADGET which operate OTG in peripheral mode

Signed-off-by Jagan Teki <[email protected]>

---
 configs/bananapi_m64_defconfig | 1 +
 1 file changed, 1 insertion(+)

configs/bananapi_m64_defconfig +1 -0

index 47f31c6d9d..40c1c18aca 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #41 lore raw

PATCH v7 27/35 ARM: dts: sun8i: a83t: Sync usbphy node from Linux

In reply to Jagan Teki

Sync sun8i-a83t usbphy node details from Linux.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun8i-a83t.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

arch/arm/dts/sun8i-a83t.dtsi +20 -0

index bab6c1812b..2953e0fdac 100644
@@ -230,13 +230,29 @@
 			reg = <0x01c19000 0x400>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
 			status = "disabled";
 		};
 
+		usbphy: phy at 1c19400 {
+			compatible = "allwinner,sun8i-a83t-usb-phy";
+			reg = <0x01c19400 0x10>,
+			      <0x01c1a800 0x14>,
+			      <0x01c1b800 0x14>;
+			reg-names = "phy_ctrl",
+				    "pmu1",
+				    "pmu2";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
 		ehci0: usb at 01c1a000 {
 			compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
 			reg = <0x01c1a000 0x100>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
 			status = "disabled";
 		};

@@ -244,6 +260,8 @@
 			compatible = "allwinner,sun8i-a83t-ohci", "generic-ohci";
 			reg = <0x01c1a400 0x100>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
 			status = "disabled";
 		};

@@ -251,6 +269,8 @@
 			compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
 			reg = <0x01c1b000 0x100>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
 			status = "disabled";
 		};

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #42 lore raw

PATCH v7 28/35 arm64: allwinner: a64: bananapi-m64: Sync usb host nodes from Linux

In reply to Jagan Teki

Sync bananapi-m64 usb host nodes from Linux.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

arch/arm/dts/sun50i-a64-bananapi-m64.dts +16 -0

index 80405e5b26..dcde4a4881 100644
@@ -68,6 +68,14 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;

@@ -108,6 +116,14 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #43 lore raw

PATCH v7 29/35 ARM: dts: sun8i-h3: bananapi-m2-plus: Sync usb otg nodes from Linux

In reply to Jagan Teki

Bananapi-m2-plus has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts +13 -0

index f3b1d5f6db..e766aa3e2f 100644
@@ -93,6 +93,10 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };

@@ -146,6 +150,10 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
 &ohci1 {
 	status = "okay";
 };

@@ -189,6 +197,11 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
 	/* USB VBUS is on as long as VCC-IO is on */
 	status = "okay";

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #44 lore raw

PATCH v7 30/35 configs: bananapi-m2-plus: Enable USB OTG peripheral mode

In reply to Jagan Teki

Enable USB_MUSB_GADGET which operate OTG in peripheral mode

Signed-off-by Jagan Teki <[email protected]>

---
 configs/Sinovoip_BPI_M2_Plus_defconfig | 1 +
 1 file changed, 1 insertion(+)

configs/Sinovoip_BPI_M2_Plus_defconfig +1 -0

index da5620a770..a325e9f806 100644
@@ -14,4 +14,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #45 lore raw

PATCH v7 31/35 arm64: allwinner: h5: orangepi-pc2: Order nodes in alphabetic

In reply to Jagan Teki

Order sun50i-h5-orangepi-pc2.dts nodes in alphabetic

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 56 ++++++++++++++++-----------------
 1 file changed, 28 insertions(+), 28 deletions(-)

arch/arm/dts/sun50i-h5-orangepi-pc2.dts +28 ~~-28~~

index d1c347d2b8..2124043dc8 100644
@@ -50,6 +50,11 @@
 	model = "OrangePi PC 2";
 	compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
 
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &emac;
+	};
+
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};

@@ -58,11 +63,6 @@
 		reg = <0x40000000 0x40000000>;
 	};
 
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &emac;
-	};
-
 	soc {
 		reg_vcc3v3: vcc3v3 {
 			compatible = "regulator-fixed";

@@ -73,6 +73,25 @@
 	};
 };
 
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-handle = <&ext_rgmii_phy>;
+	status = "okay";
+};
+
+&external_mdio {
+	ext_rgmii_phy: ethernet-phy at 1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
 &mmc0 {
 	compatible = "allwinner,sun50i-h5-mmc",
 		     "allwinner,sun50i-a64-mmc",

@@ -86,35 +105,16 @@
 	status = "okay";
 };
 
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
-	status = "okay";
-};
-
-&usbphy {
-	status = "okay";
-};
-
 &ohci1 {
 	status = "okay";
 };
 
-&ehci1 {
-	status = "okay";
-};
-
-&emac {
+&uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&emac_rgmii_pins>;
-	phy-mode = "rgmii";
-	phy-handle = <&ext_rgmii_phy>;
+	pinctrl-0 = <&uart0_pins_a>;
 	status = "okay";
 };
 
-&external_mdio {
-	ext_rgmii_phy: ethernet-phy at 1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+&usbphy {
+	status = "okay";
 };

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #46 lore raw

PATCH v7 32/35 arm64: allwinner: h5: orangepi-pc2: Sync usb otg nodes from Linux

In reply to Jagan Teki

orangepi-pc2 has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/dts/sun50i-h5-orangepi-pc2.dts +13 -0

index 2124043dc8..a65300d5aa 100644
@@ -73,6 +73,10 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };

@@ -105,6 +109,10 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
 &ohci1 {
 	status = "okay";
 };

@@ -115,6 +123,11 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
 	status = "okay";
 };

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #47 lore raw

PATCH v7 33/35 configs: orangepi-pc2: Enable USB OTG peripheral mode

In reply to Jagan Teki

Enable USB_MUSB_GADGET which operate OTG in peripheral mode

Signed-off-by Jagan Teki <[email protected]>

---
 configs/orangepi_pc2_defconfig | 1 +
 1 file changed, 1 insertion(+)

configs/orangepi_pc2_defconfig +1 -0

index dd5f2c78ab..ca1e586e89 100644
@@ -13,4 +13,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #48 lore raw

PATCH v7 34/35 arm64: allwinner: h5: orangepi-prime: Sync usb otg nodes from Linux

In reply to Jagan Teki

orangepi-prime has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun50i-h5-orangepi-prime.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/dts/sun50i-h5-orangepi-prime.dts +13 -0

index d4577dfae1..131d8058c4 100644
@@ -72,6 +72,10 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };

@@ -89,6 +93,10 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
 &ohci1 {
 	status = "okay";
 };

@@ -99,6 +107,11 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
 	status = "okay";
 };

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-07 07:33 UTC #49 lore raw

PATCH v7 35/35 configs: orangepi-prime: Enable USB OTG peripheral mode

In reply to Jagan Teki

Enable USB_MUSB_GADGET which operate OTG in peripheral mode

Signed-off-by Jagan Teki <[email protected]>

---
 configs/orangepi_prime_defconfig | 1 +
 1 file changed, 1 insertion(+)

configs/orangepi_prime_defconfig +1 -0

index df39caa903..6161863258 100644
@@ -11,4 +11,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

Signature · 1 line

2.14.3

Jagan Teki

author

2018-05-08 06:34 UTC #50 lore raw

v7 cover phy: sunxi: Add Allwinner sun4i USB PHY

In reply to Jagan Teki

Hi Jun,

Quoted 64 lines · Jagan Teki

This series rework of previous version where it removes legacy usb phy handling and added phy driver on generic-phy framework.
Current implementation phy driver is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future.
Changes for v7:
- rebase on master
Changes for v6:
- Create private config for passing through driver_data instead directly passing musb_config. This make room for adding new configs in coming patches.
- memset to pdata in musb-new/sunxi.c
Changes for v5:
- Rework of previous series
- Used driver_data on sunxi.c since dt supported
- tested on bpi-m2-plus, orangepi_pc2/prime, bananapi-m64
Changes for v4:
- Rework of previous series
- Add Allwinner sun4i USB PHY driver
- Drop legacy arch/arm/mach-sunxi/usb_phy.c and related code
Chen-Yu Tsai (1):
sunxi: clock: Fix OHCI clock gating for H3/H5
Jagan Teki (33):
usb: sunxi: Simplify ccm reg base code
musb: sunxi: Add proper macros instead of numericals
musb: sunxi: Use simple way to fill musb_hdrc pdata
musb: sunxi: Add fifo config
sunxi: clock: Fix clock gating for H3/H5/A64
musb: sunxi: Add OTG device clkgate and reset for H3/H5
musb: sunxi: Use BIT instead of numerical shift
musb: sunxi: Add support for H3/H5A64
phy: Add Allwinner A64 USB PHY driver
phy: sun4i-usb: Add id_detect and vbus_detect ops
phy: sun4i-usb: Add H3/H5 PHY config
phy: sun4i-usb: Add V3S PHY config
phy: sun4i-usb: Add A83T USB PHY config
phy: sun4i-usb: Add A10/A13/A20 PHY config
phy: sun4i-usb: Add A31 PHY config
phy: sun4i-usb: Add A33 USB PHY config
phy: sun4i-usb: Add A23 USB PHY config
device-tree-bindings: phy: Sync sun4i-usb-phy bindings
board: sunxi: Use generic-phy for board_usb_cable_connected
phy: sun4i-usb: Add a sunxi specific function for setting
squelch-detect
usb: sunxi: Switch to use generic-phy
sunxi: Drop legacy usb_phy.c
arm64: allwinner: a64: bananapi-m64: Sync usb_otg node from Linux
configs: bananapi-m64: Enable USB OTG peripheral mode
ARM: dts: sun8i: a83t: Sync usbphy node from Linux
arm64: allwinner: a64: bananapi-m64: Sync usb host nodes from Linux
ARM: dts: sun8i-h3: bananapi-m2-plus: Sync usb otg nodes from Linux
configs: bananapi-m2-plus: Enable USB OTG peripheral mode
arm64: allwinner: h5: orangepi-pc2: Order nodes in alphabetic
arm64: allwinner: h5: orangepi-pc2: Sync usb otg nodes from Linux
configs: orangepi-pc2: Enable USB OTG peripheral mode
arm64: allwinner: h5: orangepi-prime: Sync usb otg nodes from Linux
configs: orangepi-prime: Enable USB OTG peripheral mode

Quoted 2 lines

Jun Nie (1):
sunxi: h3: Sync OTG and HCI nodes from Linux DT

I've verified H3/H5 boards and can you do it from your side?

Jagan.

Jun Nie

2018-05-15 08:46 UTC #51 lore raw

v7 cover phy: sunxi: Add Allwinner sun4i USB PHY

In reply to Jagan Teki

2018-05-07 15:33 GMT+08:00 Jagan Teki <[email protected]>:

Quoted 9 lines

This series rework of previous version where it removes legacy usb phy handling and added phy driver on generic-phy framework.
Current implementation phy driver is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future.
Changes for v7:
- rebase on master

Acked-by Jun Nie <[email protected]>

Jagan Teki

2018-05-15 12:49 UTC #52 lore raw

v7 cover phy: sunxi: Add Allwinner sun4i USB PHY

Hi Marek,

Quoted 4 lines · Jun Nie

2018-05-07 15:33 GMT+08:00 Jagan Teki <[email protected]>:
Quoted 3 lines
This series rework of previous version where it removes legacy usb phy handling and added phy driver on generic-phy framework.

Quoted 8 lines

Quoted 6 lines
Current implementation phy driver is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future.
Changes for v7:
- rebase on master
Acked-by Jun Nie <[email protected]>

Any further comments, can this be apply?

Jagan.

Jagan Teki

author

2018-05-22 12:40 UTC #53 lore raw

Quoted 10 lines · Jagan Teki

Hi Marek,
Quoted 7 lines · Jun Nie
2018-05-07 15:33 GMT+08:00 Jagan Teki <[email protected]>:
Quoted 6 lines
This series rework of previous version where it removes legacy usb phy handling and added phy driver on generic-phy framework.
Current implementation phy driver is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future.

Quoted 7 lines

Quoted 5 lines
Quoted 3 lines
Changes for v7:
- rebase on master
Acked-by Jun Nie <[email protected]>
Any further comments, can this be apply?

Let us know if you have any further comments, it has a dependency with other new boards to move and helpful for early testing before the release. if you are OK? I will pick it on my tree?

Jagan.

Signature · 4 lines

Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

Marek Vasut

2018-05-22 12:44 UTC #54 lore raw

Quoted 15 lines · Jagan Teki

Quoted 14 lines · Jagan Teki
Hi Marek,
Quoted 11 lines · Jun Nie
2018-05-07 15:33 GMT+08:00 Jagan Teki <[email protected]>:
Quoted 9 lines
This series rework of previous version where it removes legacy usb phy handling and added phy driver on generic-phy framework.
Current implementation phy driver is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future.
Changes for v7:
- rebase on master

Quoted 7 lines

Quoted 3 lines
Quoted 1 line
Acked-by Jun Nie <[email protected]>
Any further comments, can this be apply?
Let us know if you have any further comments, it has a dependency with other new boards to move and helpful for early testing before the release. if you are OK? I will pick it on my tree?

Yeah, just pick it.

Signature · 2 lines

Best regards,
Marek Vasut