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clk: davinci: pll-dm355: fix SYSCLKn parent names

PATCH Superseded David Lechner 2 participants 4 messages May 7, 2018

Subsystems (2)
Common clk TI DaVinci series clock driver

v2 of 3 Superseded Latest is v3 →

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David Lechner

author maintainer
#0 lore raw

PATCH v2 1/2 clk: davinci: pll-dm355: fix SYSCLKn parent names

This fixes the parent clock names of the SYSCLKn clocks for the DM355 SoC in the TI DaVinici PLL clock driver.

It appears that this name just didn't get updated to the correct name like the other SoCs during the driver's development.

Reported-by Sekhar Nori <[email protected]>
Signed-off-by David Lechner <[email protected]>

---

v2 changes:
- add second patch to fix additional problems with DM355

 drivers/clk/davinci/pll-dm355.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/clk/davinci/pll-dm355.c +6 -6
index 5345f8286c50..1f746d2fc894 100644
@@ -22,10 +22,10 @@ static const struct davinci_pll_clk_info dm355_pll1_info = {
 		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
 
 int dm355_pll1_init(struct device *dev, void __iomem *base)
 {

@@ -62,8 +62,8 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
 		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
-SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV);
+SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
 
 int dm355_pll2_init(struct device *dev, void __iomem *base)
 {
Signature · 1 line
2.17.0
author maintainer
#1 lore raw

PATCH v2 2/2 clk: davinci: pll-dm355: drop pll2_sysclk2

This removes pll2_sysclk2 from the TI DM355 clock driver. This SoC doesn't have such a clock. Also, SYSCLK_ALWAYS_ENABLED is transferred to pll2_sysclk1 since it drives the DDR and doesn't have another mechanism to keep it on.

Reported-by Sekhar Nori <[email protected]>
Signed-off-by David Lechner <[email protected]>
---
 drivers/clk/davinci/pll-dm355.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)
drivers/clk/davinci/pll-dm355.c +1 -4
index 1f746d2fc894..93f4a53d6b44 100644
@@ -62,8 +62,7 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
 		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV);
-SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
 
 int dm355_pll2_init(struct device *dev, void __iomem *base)
 {

@@ -71,8 +70,6 @@ int dm355_pll2_init(struct device *dev, void __iomem *base)
 
 	davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
 
-	davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
-
 	davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
 
 	return 0;
Signature · 1 line
2.17.0
#2 lore raw
In reply to David Lechner
Quoted 36 lines · David Lechner

This fixes the parent clock names of the SYSCLKn clocks for the DM355 SoC in the TI DaVinici PLL clock driver.

It appears that this name just didn't get updated to the correct name like the other SoCs during the driver's development.

Reported-by Sekhar Nori <[email protected]>
Signed-off-by David Lechner <[email protected]>

---

v2 changes:
- add second patch to fix additional problems with DM355

 drivers/clk/davinci/pll-dm355.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/clk/davinci/pll-dm355.c +4 -4
index 5345f8286c50..1f746d2fc894 100644
@@ -22,10 +22,10 @@ static const struct davinci_pll_clk_info dm355_pll1_info = {
 		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
 
 int dm355_pll1_init(struct device *dev, void __iomem *base)
 {

drivers/clk/davinci/pll-dm355.c static const struct davinci_pll_clk_info dm355_pll2_info = { · line 66

Quoted 7 lines
drivers/clk/davinci/pll-dm355.c +2 -2
@@ -62,8 +62,8 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
 		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
-SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV);
+SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);

Good find with PLL2 SYSCLK2. Can you reverse the patch order so we are not fixing up a non-existent clock?

Thanks,
Sekhar

author maintainer
#3 lore raw
Quoted 40 lines · Sekhar Nori
Quoted 39 lines · David Lechner

This fixes the parent clock names of the SYSCLKn clocks for the DM355 SoC in the TI DaVinici PLL clock driver.

It appears that this name just didn't get updated to the correct name like the other SoCs during the driver's development.

Reported-by Sekhar Nori <[email protected]>
Signed-off-by David Lechner <[email protected]>

---

v2 changes:
- add second patch to fix additional problems with DM355

  drivers/clk/davinci/pll-dm355.c | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)
drivers/clk/davinci/pll-dm355.c +4 -4
index 5345f8286c50..1f746d2fc894 100644
@@ -22,10 +22,10 @@ static const struct davinci_pll_clk_info dm355_pll1_info = {
  		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
  };
 
-SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
 
  int dm355_pll1_init(struct device *dev, void __iomem *base)
  {

@@ -62,8 +62,8 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
  		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
  };
Quoted 8 lines

drivers/clk/davinci/pll-dm355.c static const struct davinci_pll_clk_info dm355_pll2_info = { · line 66

Quoted 4 lines
drivers/clk/davinci/pll-dm355.c +2 -2
-SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
-SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV);
+SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);

Good find with PLL2 SYSCLK2. Can you reverse the patch order so we are not fixing up a non-existent clock?

Sure. But it will take me a couple days to get back to it.