CPU scaling support for msm8996
Subsystems (9)
v5 cover CPU scaling support for msm8996
[v5]
* Rebased
* Adressed comments from Bjorn
* Adressed comments from Viresh
* Adressed comments from Sricharan
* Adressed comments from Nicolas
* Adressed comments from Rob
* Adressed comments from Mark
[v4]
* Adressed comments from Stephen
* Added CPU regulator support
* Added qcom-cpufreq-kryo driver
[v3]
* Rebased on top of the latest PLL driver changes
* Addressed comment from Rob Herring for bindings
[v2]
* Addressed comments from Rob Herring for bindings
* Addressed comments from Mark Rutland for memory barrier
* Addressed comments from Julien Thierry for clock reenabling condition
* Tuned the HW configuration for clock frequencies below 600MHz
Clocks:
This series adds support for the CPU clocks on msm8996 devices. The driver uses the existing PLL drivers and is required to control the CPU frequency scaling on the MSM8996.
Regulators:
Added SAW regulator support to the SPMI regulator driver. The SAW regulators will be controlled through special CPU registers instead of direct SPMI accesses.
Cpufreq:
The qcom-cpufreq-kryo driver is aimed to support different SOC versions. The driver reads eFuse information and chooses the required OPP subset by passing the OPP supported-hw parameter.
A previous post of RFC can be found here:
https://patchwork.kernel.org/patch/10316261/
Ilia Lin (11):
soc: qcom: Separate kryo l2 accessors from PMU driver
clk: qcom: Add CPU clock driver for msm8996
clk: qcom: Add DT bindings for CPU clock driver for msm8996
clk: qcom: Add ACD path to CPU clock driver for msm8996
dt: qcom: Add opp and thermal to the msm8996
regulator: qcom_spmi: Add support for SAW
dt-bindings: qcom_spmi: Add support for SAW documentation
dt: qcom: Add SAW regulator for 8x96 CPUs
cpufreq: Add Kryo CPU scaling driver
dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
dt: qcom: Add qcom-cpufreq-kryo driver configuration
Rajendra Nayak (3):
clk: qcom: Make clk_alpha_pll_configure available to modules
clk: qcom: cpu-8996: Add support to switch to alternate PLL
clk: qcom: cpu-8996: Add support to switch below 600Mhz
.../devicetree/bindings/clock/qcom,kryocc.txt | 17 + .../devicetree/bindings/opp/kryo-cpufreq.txt | 693 +++++++++++++++++++++ .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++ arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 650 ++++++++++++++++++- drivers/clk/clk-fixed-factor.c | 2 +- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 1 + drivers/clk/qcom/clk-alpha-pll.h | 6 + drivers/clk/qcom/clk-cpu-8996.c | 519 +++++++++++++++ drivers/cpufreq/Kconfig.arm | 11 + drivers/cpufreq/Makefile | 1 + drivers/cpufreq/cpufreq-dt-platdev.c | 3 + drivers/cpufreq/qcom-cpufreq-kryo.c | 153 +++++ drivers/perf/Kconfig | 1 + drivers/perf/qcom_l2_pmu.c | 90 +-- drivers/regulator/qcom_spmi-regulator.c | 133 +++- drivers/soc/qcom/Kconfig | 3 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/kryo-l2-accessors.c | 65 ++ include/soc/qcom/kryo-l2-accessors.h | 21 + 22 files changed, 2347 insertions(+), 80 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt create mode 100644 drivers/clk/qcom/clk-cpu-8996.c create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c create mode 100644 include/soc/qcom/kryo-l2-accessors.h
Signature · 1 line
1.9.1
PATCH v5 1/14 soc: qcom: Separate kryo l2 accessors from PMU driver
The driver provides kernel level API for other drivers to access the MSM8996 L2 cache registers. Separating the L2 access code from the PMU driver and making it public to allow other drivers use it. The accesses must be separated with a single spinlock, maintained in this driver.
--- drivers/perf/Kconfig | 1 + drivers/perf/qcom_l2_pmu.c | 90 ++++++++++-------------------------- drivers/soc/qcom/Kconfig | 3 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/kryo-l2-accessors.c | 65 ++++++++++++++++++++++++++ include/soc/qcom/kryo-l2-accessors.h | 21 +++++++++ 6 files changed, 115 insertions(+), 66 deletions(-) create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c create mode 100644 include/soc/qcom/kryo-l2-accessors.h
drivers/perf/Kconfig +1 -0
@@ -69,6 +69,7 @@ config HISI_PMU config QCOM_L2_PMU bool "Qualcomm Technologies L2-cache PMU" depends on ARCH_QCOM && ARM64 && ACPI + select QCOM_KRYO_L2_ACCESSORS help Provides support for the L2 cache performance monitor unit (PMU) in Qualcomm Technologies processors.
drivers/perf/qcom_l2_pmu.c +24 -66
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drivers/soc/qcom/Kconfig +3 -0
@@ -39,6 +39,9 @@ config QCOM_GSBI functions for connecting the underlying serial UART, SPI, and I2C devices to the output pins. +config QCOM_KRYO_L2_ACCESSORS + bool + config QCOM_MDT_LOADER tristate select QCOM_SCM
drivers/soc/qcom/Makefile +1 -0
@@ -14,3 +14,4 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o obj-$(CONFIG_QCOM_SMP2P) += smp2p.o obj-$(CONFIG_QCOM_SMSM) += smsm.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o +obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
drivers/soc/qcom/kryo-l2-accessors.c new file +65 -0
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include/soc/qcom/kryo-l2-accessors.h new file +21 -0
@@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H +#define __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H + +void kryo_l2_set_indirect_reg (u64 reg,u64 val); +u64 kryo_l2_get_indirect_reg (u64 reg); + +#endif
Signature · 1 line
1.9.1
PATCH v5 2/14 clk: qcom: Make clk_alpha_pll_configure available to modules
In reply to Ilia LinFrom: Rajendra Nayak <[email protected]>
Allow clk_alpha_pll_configure to be called from loadable kernel modules.
--- drivers/clk/qcom/clk-alpha-pll.c | 1 + 1 file changed, 1 insertion(+)
drivers/clk/qcom/clk-alpha-pll.c +1 -0
@@ -228,6 +228,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,if (pll->flags &SUPPORTS_FSM_MODE )qcom_pll_set_fsm_mode (regmap,PLL_MODE (pll),6 ,0 ); } +EXPORT_SYMBOL_GPL (clk_alpha_pll_configure);static int clk_alpha_pll_hwfsm_enable (struct clk_hw *hw) {
Signature · 1 line
1.9.1
PATCH v5 3/14 clk: qcom: Add CPU clock driver for msm8996
In reply to Ilia LinEach of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below
+-------+
XO | |
+------------------>0 |
| |
PLL/2 | SMUX +----+
+------->1 | |
| | | |
| +-------+ | +-------+
| +---->0 |
| | |
+---------------+ | +----------->1 | CPU clk
|Primary PLL +----+ PLL_EARLY | | +------>
| +------+-----------+ +------>2 PMUX |
+---------------+ | | | |
| +------+ | +-->3 |
+--^+ ACD +-----+ | +-------+
+---------------+ +------+ |
|Alt PLL | |
| +---------------------------+
+---------------+ PLL_EARLYThe primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes.
The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX.
So for frequencies above 600MHz we follow the following path
Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
and for frequencies between 300MHz and 600MHz we follow
Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
Support for this is added in a subsequent patch as well.
ACD stands for Adaptive Clock Distribution and is used to detect voltage droops. We do not add support for ACD as yet.
--- drivers/clk/clk-fixed-factor.c | 2 +- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.h | 6 + drivers/clk/qcom/clk-cpu-8996.c | 412 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 429 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/qcom/clk-cpu-8996.c
drivers/clk/clk-fixed-factor.c +1 -1
@@ -94,7 +94,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, init.num_parents =1 ; hw = &fix->hw; - ret =clk_hw_register (dev, hw); + ret =devm_clk_hw_register (dev, hw);if (ret) {kfree (fix); hw =ERR_PTR (ret);
drivers/clk/qcom/Kconfig +9 -0
@@ -33,6 +33,15 @@ config QCOM_CLK_APCS_MSM8916 Say Y if you want to support CPU frequency scaling on devices such as msm8916. +config QCOM_CLK_APCC_MSM8996 + tristate "MSM8996 CPU Clock Controller" + depends on COMMON_CLK_QCOM + select QCOM_KRYO_L2_ACCESSORS + help + Support for the CPU clock controller on msm8996 devices. + Say Y if you want to support CPU clock scaling using CPUfreq + drivers for dyanmic power management. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
drivers/clk/qcom/Makefile +1 -0
@@ -36,6 +36,7 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o +obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
drivers/clk/qcom/clk-alpha-pll.h +6 -0
@@ -50,6 +50,12 @@ struct pll_vco {u32 val; }; +#define VCO (a, b, c) { \ + .val = a,\ + .min_freq = b,\ + .max_freq = c,\ +} +/** * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers
drivers/clk/qcom/clk-cpu-8996.c new file +412 -0
412 lines not on this page · raw message
Signature · 1 line
1.9.1
kbuild test robot
build botRe: [PATCH v5 03/14] clk: qcom: Add CPU clock driver for msm8996
Thank you for the patch! Perhaps something to improve:
Hi Ilia,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on v4.17-rc3 next-20180503]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Ilia-Lin/CPU-scaling-support-for-msm8996/20180504-174840 base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next reproduce: # apt-get install sparse make ARCH=x86_64 allmodconfig make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/clk/qcom/clk-cpu-8996.c:142:9: sparse: constant 2150400000 is so big it is long >> drivers/clk/qcom/clk-cpu-8996.c:239:22: sparse: symbol 'clk_cpu_8996_mux_ops' was not declared. Should it be static?
drivers/clk/qcom/clk-cpu-8996.c:324:19: sparse: symbol 'clks' was not declared. Should it be static?
vim +142 drivers/clk/qcom/clk-cpu-8996.c
137
138 static const struct pll_vco alt_pll_vco_modes[] = {
139 VCO(3, 250000000, 500000000),
140 VCO(2, 500000000, 750000000),
141 VCO(1, 750000000, 1000000000),
> 142 VCO(0, 1000000000, 2150400000),
143 };
144
145 static const struct alpha_pll_config altpll_config = {
146 .l = 16,
147 .vco_val = 0x3 << 20,
148 .vco_mask = 0x3 << 20,
149 .config_ctl_val = 0x4001051b,
150 .post_div_mask = 0x3 << 8,
151 .post_div_val = 0x1,
152 .main_output_mask = BIT(0),
153 .early_output_mask = BIT(3),
154 };
155
156 static struct clk_alpha_pll perfcl_alt_pll = {
157 .offset = 0x80100,
158 .regs = alt_pll_regs,
159 .vco_table = alt_pll_vco_modes,
160 .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
161 .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
162 .clkr.hw.init = &(struct clk_init_data) {
163 .name = "perfcl_alt_pll",
164 .parent_names = (const char *[]){ "xo" },
165 .num_parents = 1,
166 .ops = &clk_alpha_pll_hwfsm_ops,
167 },
168 };
169
170 static struct clk_alpha_pll pwrcl_alt_pll = {
171 .offset = 0x100,
172 .regs = alt_pll_regs,
173 .vco_table = alt_pll_vco_modes,
174 .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
175 .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
176 .clkr.hw.init = &(struct clk_init_data) {
177 .name = "pwrcl_alt_pll",
178 .parent_names = (const char *[]){ "xo" },
179 .num_parents = 1,
180 .ops = &clk_alpha_pll_hwfsm_ops,
181 },
182 };
183
184 /* Mux'es */
185
186 struct clk_cpu_8996_mux {
187 u32 reg;
188 u8 shift;
189 u8 width;
190 struct clk_hw *pll;
191 struct clk_regmap clkr;
192 };
193
194 static inline
195 struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
196 {
197 return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
198 }
199
200 static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
201 {
202 u32 val;
203 struct clk_regmap *clkr = to_clk_regmap(hw);
204 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
205 u32 mask = (u32)GENMASK(cpuclk->width - 1, 0);
206
207 regmap_read(clkr->regmap, cpuclk->reg, &val);
208 val >>= (u32)(cpuclk->shift);
209
210 return (u8)(val & mask);
211 }
212
213 static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
214 {
215 u32 val;
216 struct clk_regmap *clkr = to_clk_regmap(hw);
217 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
218 unsigned int mask = GENMASK(cpuclk->width + cpuclk->shift - 1,
219 cpuclk->shift);
220
221 val = (u32)index;
222 val <<= (u32)(cpuclk->shift);
223
224 return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
225 }
226
227 static int
228 clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
229 {
230 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
231 struct clk_hw *parent = cpuclk->pll;
232
233 req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
234 req->best_parent_hw = parent;
235
236 return 0;
237 }
238
> 239 const struct clk_ops clk_cpu_8996_mux_ops = { 240 .set_parent = clk_cpu_8996_mux_set_parent,
241 .get_parent = clk_cpu_8996_mux_get_parent,
242 .determine_rate = clk_cpu_8996_mux_determine_rate,
243 };
244
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
PATCH v5 4/14 clk: qcom: Add DT bindings for CPU clock driver for msm8996
In reply to Ilia LinEach of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below
+-------+
XO | |
+------------------>0 |
| |
PLL/2 | SMUX +----+
+------->1 | |
| | | |
| +-------+ | +-------+
| +---->0 |
| | |
+---------------+ | +----------->1 | CPU clk
|Primary PLL +----+ PLL_EARLY | | +------>
| +------+-----------+ +------>2 PMUX |
+---------------+ | | | |
| +------+ | +-->3 |
+--^+ ACD +-----+ | +-------+
+---------------+ +------+ |
|Alt PLL | |
| +---------------------------+
+---------------+ PLL_EARLYThe primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes.
The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX.
--- Documentation/devicetree/bindings/clock/qcom,kryocc.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt
Documentation/devicetree/bindings/clock/qcom,kryocc.txt new file +17 -0
@@ -0,0 +1,17 @@ +Qualcomm CPUSS clock controller for Kryo CPUs +---------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + + "qcom,msm8996-apcc" + +- reg : shall contain base register location and length +- #clock-cells : shall contain 1 + +Example: + kryocc: clock-controller at 6400000 { + compatible = "qcom,msm8996-apcc"; + reg = <0x6400000 0x90000>; + #clock-cells = <1>; + };
Signature · 1 line
1.9.1
PATCH v5 5/14 clk: qcom: cpu-8996: Add support to switch to alternate PLL
In reply to Ilia LinFrom: Rajendra Nayak <[email protected]>
Each of the CPU clusters on msm8996 are powered via a primary PLL and a secondary PLL. The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself, when we temporarily switch to an alternate PLL. Use clock rate change notifiers to support this.
--- drivers/clk/qcom/clk-cpu-8996.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
drivers/clk/qcom/clk-cpu-8996.c +33 -0
@@ -61,6 +61,7 @@* detect voltage droops. We do not add support for ACD as yet. */ +#include <linux/clk.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/regmap.h>
@@ -187,10 +188,14 @@ struct clk_cpu_8996_mux {u32 reg;u8 shift;u8 width; +struct notifier_block nb;struct clk_hw *pll;struct clk_regmap clkr; }; +#define to_clk_cpu_8996_mux_nb (_nb) \ + container_of(_nb, struct clk_cpu_8996_mux, nb) +static inline struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw (struct clk_hw *hw) {
@@ -236,6 +241,26 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)return 0 ; } +int cpu_clk_notifier_cb (struct notifier_block *nb,unsigned long event, +void *data) +{ +int ret; +struct clk_cpu_8996_mux *cpuclk =to_clk_cpu_8996_mux_nb (nb); + +switch (event) { +case PRE_RATE_CHANGE : + ret =clk_cpu_8996_mux_set_parent (&cpuclk->clkr.hw,ALT_INDEX ); +break ; +case POST_RATE_CHANGE : + ret =clk_cpu_8996_mux_set_parent (&cpuclk->clkr.hw,PLL_INDEX ); +break ; +default : + ret =0 ; +break ; + } + +return notifier_from_errno (ret); +};const struct clk_ops clk_cpu_8996_mux_ops = { .set_parent = clk_cpu_8996_mux_set_parent, .get_parent = clk_cpu_8996_mux_get_parent,
@@ -279,6 +304,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, + .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data ) { .name ="pwrcl_pmux" , .parent_names = (const char *[]){
@@ -298,6 +324,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, + .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data ) { .name ="perfcl_pmux" , .parent_names = (const char *[]){
@@ -356,6 +383,12 @@ struct clk_regmap *clks[] = {clk_alpha_pll_configure (&perfcl_alt_pll, regmap, &altpll_config);clk_alpha_pll_configure (&pwrcl_alt_pll, regmap, &altpll_config); + ret =clk_notifier_register (pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); +if (ret) +return ret; + + ret =clk_notifier_register (perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb); +return ret; }
Signature · 1 line
1.9.1
PATCH v5 6/14 clk: qcom: cpu-8996: Add support to switch below 600Mhz
In reply to Ilia LinFrom: Rajendra Nayak <[email protected]>
The CPU clock controller's primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX.
So for frequencies above 600MHz we follow the following path
Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
and for frequencies between 300MHz and 600MHz we follow
Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
Conflicts:
drivers/clk/qcom/clk-cpu-8996.c --- drivers/clk/qcom/clk-cpu-8996.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-)
drivers/clk/qcom/clk-cpu-8996.c +22 -3
@@ -77,6 +77,8 @@ enum _pmux_input {NUM_OF_PMUX_INPUTS }; +#define DIV_2_THRESHOLD 600000000 +static const u8 prim_pll_regs[PLL_OFF_MAX_REGS ] = { [PLL_OFF_L_VAL ] =0x04 , [PLL_OFF_ALPHA_VAL ] =0x08 ,
@@ -104,10 +106,11 @@ enum _pmux_input {static const struct alpha_pll_config hfpll_config = { .l =60 , - .config_ctl_val =0x200d4828 , + .config_ctl_val =0x200d4aa8 , .config_ctl_hi_val =0x006 , .pre_div_mask =BIT (12 ), .post_div_mask =0x3 <<8 , + .post_div_val =0x1 <<8 , .main_output_mask =BIT (0 ), .early_output_mask =BIT (3 ), };
@@ -149,7 +152,7 @@ enum _pmux_input { .vco_mask = 0x3 << 20, .config_ctl_val = 0x4001051b, .post_div_mask = 0x3 << 8, - .post_div_val = 0x1, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), };
@@ -190,6 +193,7 @@ struct clk_cpu_8996_mux {u8 width;struct notifier_block nb;struct clk_hw *pll; +struct clk_hw *pll_div_2;struct clk_regmap clkr; };
@@ -235,6 +239,13 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)struct clk_cpu_8996_mux *cpuclk =to_clk_cpu_8996_mux_hw (hw);struct clk_hw *parent = cpuclk->pll; +if (cpuclk->pll_div_2 && req->rate <DIV_2_THRESHOLD ) { +if (req->rate < (DIV_2_THRESHOLD /2 )) +return -EINVAL ; + + parent = cpuclk->pll_div_2; + } + req->best_parent_rate =clk_hw_round_rate (parent, req->rate); req->best_parent_hw = parent;
@@ -246,13 +257,19 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, {int ret;struct clk_cpu_8996_mux *cpuclk =to_clk_cpu_8996_mux_nb (nb); +struct clk_notifier_data *cnd = data;switch (event) {case PRE_RATE_CHANGE : ret =clk_cpu_8996_mux_set_parent (&cpuclk->clkr.hw,ALT_INDEX );break ;case POST_RATE_CHANGE : - ret =clk_cpu_8996_mux_set_parent (&cpuclk->clkr.hw,PLL_INDEX ); +if (cnd->new_rate <DIV_2_THRESHOLD ) + ret =clk_cpu_8996_mux_set_parent (&cpuclk->clkr.hw, +DIV_2_INDEX ); +else + ret =clk_cpu_8996_mux_set_parent (&cpuclk->clkr.hw, +PLL_INDEX );break ;default : ret =0 ;
@@ -304,6 +321,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, + .pll_div_2 = &pwrcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data ) { .name ="pwrcl_pmux" ,
@@ -324,6 +342,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, + .pll_div_2 = &perfcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data ) { .name ="perfcl_pmux" ,
Signature · 1 line
1.9.1
PATCH v5 7/14 clk: qcom: Add ACD path to CPU clock driver for msm8996
In reply to Ilia LinThe PMUX for each duplex allows for selection of ACD clock source. The DVM (Dynamic Variation Monitor) will flag an error
when a voltage droop event is detected. This flagged error enables ACD to provide a div-by-2 clock, sourced from the primary PLL. The duplex will be provided the divided clock
until a pre-programmed delay has expired.
This change configures ACD during the probe and switches the PMUXes to the ACD clock source.
--- drivers/clk/qcom/clk-cpu-8996.c | 75 +++++++++++++++++++++++++++++++++++------ 1 file changed, 65 insertions(+), 10 deletions(-)
drivers/clk/qcom/clk-cpu-8996.c +65 -10
@@ -62,9 +62,11 @@*/ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <soc/qcom/kryo-l2-accessors.h> #include "clk-alpha-pll.h" #include "clk-regmap.h"
@@ -78,6 +80,11 @@ enum _pmux_input { };#define DIV_2_THRESHOLD 600000000 +#define PWRCL_REG_OFFSET 0x0 +#define PERFCL_REG_OFFSET 0x80000 +#define MUX_OFFSET 0x40 +#define ALT_PLL_OFFSET 0x100 +#define SSSCTL_OFFSET 0x160static const u8 prim_pll_regs[PLL_OFF_MAX_REGS ] = { [PLL_OFF_L_VAL ] =0x04 ,
@@ -116,7 +123,7 @@ enum _pmux_input { };static struct clk_alpha_pll perfcl_pll = { - .offset =0x80000 , + .offset =PERFCL_REG_OFFSET , .regs = prim_pll_regs, .flags =SUPPORTS_DYNAMIC_UPDATE |SUPPORTS_FSM_MODE , .clkr.hw.init = &(struct clk_init_data ){
@@ -128,7 +135,7 @@ enum _pmux_input { };static struct clk_alpha_pll pwrcl_pll = { - .offset =0x0 , + .offset =PWRCL_REG_OFFSET , .regs = prim_pll_regs, .flags =SUPPORTS_DYNAMIC_UPDATE |SUPPORTS_FSM_MODE , .clkr.hw.init = &(struct clk_init_data ){
@@ -158,7 +165,7 @@ enum _pmux_input { };static struct clk_alpha_pll perfcl_alt_pll = { - .offset =0x80100 , + .offset =PERFCL_REG_OFFSET +ALT_PLL_OFFSET , .regs = alt_pll_regs, .vco_table = alt_pll_vco_modes, .num_vco =ARRAY_SIZE (alt_pll_vco_modes),
@@ -172,7 +179,7 @@ enum _pmux_input { };static struct clk_alpha_pll pwrcl_alt_pll = { - .offset =0x100 , + .offset =PWRCL_REG_OFFSET +ALT_PLL_OFFSET , .regs = alt_pll_regs, .vco_table = alt_pll_vco_modes, .num_vco =ARRAY_SIZE (alt_pll_vco_modes),
@@ -185,6 +192,9 @@ enum _pmux_input { }, }; +void __iomem *base; +static void qcom_cpu_clk_msm8996_acd_init (void __iomem *base); +/* Mux'es */ struct clk_cpu_8996_mux {
@@ -262,6 +272,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,switch (event) {case PRE_RATE_CHANGE : ret =clk_cpu_8996_mux_set_parent (&cpuclk->clkr.hw,ALT_INDEX ); +qcom_cpu_clk_msm8996_acd_init (base);break ;case POST_RATE_CHANGE :if (cnd->new_rate <DIV_2_THRESHOLD )
@@ -269,7 +280,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, DIV_2_INDEX); else ret =clk_cpu_8996_mux_set_parent (&cpuclk->clkr.hw, -PLL_INDEX ); +ACD_INDEX );break ;default : ret =0 ;
@@ -285,7 +296,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, };static struct clk_cpu_8996_mux pwrcl_smux = { - .reg =0x40 , + .reg =PWRCL_REG_OFFSET +MUX_OFFSET , .shift =2 , .width =2 , .clkr.hw.init = &(struct clk_init_data ) {
@@ -301,7 +312,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, };static struct clk_cpu_8996_mux perfcl_smux = { - .reg =0x80040 , + .reg =PERFCL_REG_OFFSET +MUX_OFFSET , .shift =2 , .width =2 , .clkr.hw.init = &(struct clk_init_data ) {
@@ -317,7 +328,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, };static struct clk_cpu_8996_mux pwrcl_pmux = { - .reg =0x40 , + .reg =PWRCL_REG_OFFSET +MUX_OFFSET , .shift =0 , .width =2 , .pll = &pwrcl_pll.clkr.hw,
@@ -338,7 +349,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, };static struct clk_cpu_8996_mux perfcl_pmux = { - .reg =0x80040 , + .reg =PERFCL_REG_OFFSET +MUX_OFFSET , .shift =0 , .width =2 , .pll = &perfcl_pll.clkr.hw,
@@ -402,6 +413,10 @@ struct clk_regmap *clks[] = {clk_alpha_pll_configure (&perfcl_alt_pll, regmap, &altpll_config);clk_alpha_pll_configure (&pwrcl_alt_pll, regmap, &altpll_config); +/* Enable alt PLLs */ +clk_prepare_enable (pwrcl_alt_pll.clkr.hw.clk); +clk_prepare_enable (perfcl_alt_pll.clkr.hw.clk); + ret =clk_notifier_register (pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);if (ret)return ret;
@@ -411,10 +426,48 @@ struct clk_regmap *clks[] = {return ret; } +#define CPU_AFINITY_MASK 0xFFF +#define PWRCL_CPU_REG_MASK 0x3 +#define PERFCL_CPU_REG_MASK 0x103 + +#define L2ACDCR_REG 0x580ULL +#define L2ACDTD_REG 0x581ULL +#define L2ACDDVMRC_REG 0x584ULL +#define L2ACDSSCR_REG 0x589ULL + +static DEFINE_SPINLOCK (acd_lock); + +static void qcom_cpu_clk_msm8996_acd_init (void __iomem *base) +{ +u64 hwid; +unsigned long flags; + +spin_lock_irqsave (&acd_lock, flags); + + hwid =read_cpuid_mpidr () &CPU_AFINITY_MASK ; + +kryo_l2_set_indirect_reg (L2ACDTD_REG ,0x00006A11 ); +kryo_l2_set_indirect_reg (L2ACDDVMRC_REG ,0x000E0F0F ); +kryo_l2_set_indirect_reg (L2ACDSSCR_REG ,0x00000601 ); + +if (PWRCL_CPU_REG_MASK == (hwid |PWRCL_CPU_REG_MASK )) { +writel (0xF , base +PWRCL_REG_OFFSET +SSSCTL_OFFSET ); +wmb (); +kryo_l2_set_indirect_reg (L2ACDCR_REG ,0x002C5FFD ); + } + +if (PERFCL_CPU_REG_MASK == (hwid |PERFCL_CPU_REG_MASK )) { +kryo_l2_set_indirect_reg (L2ACDCR_REG ,0x002C5FFD ); +writel (0xF , base +PERFCL_REG_OFFSET +SSSCTL_OFFSET ); +wmb (); + } + +spin_unlock_irqrestore (&acd_lock, flags); +} +static int qcom_cpu_clk_msm8996_driver_probe (struct platform_device *pdev) {int ret; -void __iomem *base;struct resource *res;struct regmap *regmap;struct clk_hw_onecell_data *data;
@@ -438,6 +491,8 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)if (ret)return ret; +qcom_cpu_clk_msm8996_acd_init (base); + data->hws[0 ] = &pwrcl_pmux.clkr.hw; data->hws[1 ] = &perfcl_pmux.clkr.hw; data->num =2 ;
Signature · 1 line
1.9.1
PATCH v5 8/14 dt: qcom: Add opp and thermal to the msm8996
In reply to Ilia Lin--- arch/arm64/boot/dts/qcom/msm8996.dtsi | 269 ++++++++++++++++++++++++++++++++-- 1 file changed, 260 insertions(+), 9 deletions(-)
arch/arm64/boot/dts/qcom/msm8996.dtsi +260 -9
@@ -14,6 +14,7 @@ #include <dt-bindings/clock/qcom,gcc-msm8996.h> #include <dt-bindings/clock/qcom,mmcc-msm8996.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/thermal/thermal.h> / { model = "Qualcomm Technologies, Inc. MSM8996";
@@ -97,6 +98,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&kryocc 0>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache";
@@ -109,6 +113,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x1>; enable-method = "psci"; + clocks = <&kryocc 0>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; };
@@ -117,6 +124,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + clocks = <&kryocc 1>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache";
@@ -129,6 +139,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x101>; enable-method = "psci"; + clocks = <&kryocc 1>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_1>; };
@@ -155,6 +168,182 @@ }; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + clock-latency-ns = <200000>; + }; + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + clock-latency-ns = <200000>; + }; + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + clock-latency-ns = <200000>; + }; + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + clock-latency-ns = <200000>; + }; + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + clock-latency-ns = <200000>; + }; + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + clock-latency-ns = <200000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + clock-latency-ns = <200000>; + }; + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + clock-latency-ns = <200000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + clock-latency-ns = <200000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + clock-latency-ns = <200000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + clock-latency-ns = <200000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + clock-latency-ns = <200000>; + }; + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + clock-latency-ns = <200000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + clock-latency-ns = <200000>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + clock-latency-ns = <200000>; + }; + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + clock-latency-ns = <200000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + clock-latency-ns = <200000>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + clock-latency-ns = <200000>; + }; + }; + thermal-zones { cpu-thermal0 { polling-delay-passive = <250>;
@@ -163,18 +352,34 @@ thermal-sensors = <&tsens0 3>; trips { - cpu_alert0: trip0 { + cpu_alert0: cpu_alert0 { temperature = <75000>; hysteresis = <2000>; + type = "active"; + }; + cpu_warn0: cpu_warn0 { + temperature = <90000>; + hysteresis = <2000>; type = "passive"; }; - cpu_crit0: trip1 { + cpu_crit0: cpu_crit0 { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>; + }; + map1 { + trip = <&cpu_warn0>; + cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>; + }; + }; }; cpu-thermal1 {
@@ -184,18 +389,34 @@ thermal-sensors = <&tsens0 5>; trips { - cpu_alert1: trip0 { + cpu_alert1: cpu_alert1 { temperature = <75000>; hysteresis = <2000>; + type = "active"; + }; + cpu_warn1: cpu_warn1 { + temperature = <90000>; + hysteresis = <2000>; type = "passive"; }; - cpu_crit1: trip1 { + cpu_crit1: cpu_crit1 { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>; + }; + map1 { + trip = <&cpu_warn1>; + cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>; + }; + }; }; cpu-thermal2 {
@@ -205,18 +426,33 @@ thermal-sensors = <&tsens0 8>; trips { - cpu_alert2: trip0 { + cpu_alert2: cpu_alert2 { temperature = <75000>; hysteresis = <2000>; + type = "active"; + }; + cpu_warn2: cpu_warn2 { + temperature = <90000>; + hysteresis = <2000>; type = "passive"; }; - cpu_crit2: trip1 { + cpu_crit2: cpu_crit2 { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; + cooling-maps { + map0 { + trip = <&cpu_alert2>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>; + }; + map1 { + trip = <&cpu_warn2>; + cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>; + }; + }; }; cpu-thermal3 {
@@ -226,9 +462,14 @@ thermal-sensors = <&tsens0 10>; trips { - cpu_alert3: trip0 { + cpu_alert3: cpu_alert3 { temperature = <75000>; hysteresis = <2000>; + type = "active"; + }; + cpu_warn3: cpu_warn3 { + temperature = <90000>; + hysteresis = <2000>; type = "passive"; };
@@ -238,6 +479,16 @@ type = "critical"; }; }; + cooling-maps { + map0 { + trip = <&cpu_alert3>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>; + }; + map1 { + trip = <&cpu_warn3>; + cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>; + }; + }; }; };
@@ -414,7 +665,7 @@ }; kryocc: clock-controller at 6400000 { - compatible = "qcom,apcc-msm8996"; + compatible = "qcom,msm8996-apcc"; reg = <0x6400000 0x90000>; #clock-cells = <1>; };
@@ -1001,7 +1252,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; - pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; + pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep>; vdda-supply = <&pm8994_l28>;
Signature · 1 line
1.9.1
PATCH v5 9/14 regulator: qcom_spmi: Add support for SAW
In reply to Ilia LinAdd support for SAW controlled regulators.
The regulators defined as SAW controlled in the device tree will be controlled through special CPU registers instead of direct SPMI accesses.
This is required especially for CPU supply regulators to synchronize with clock scaling and for Automatic Voltage Switching.
--- drivers/regulator/qcom_spmi-regulator.c | 133 +++++++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 3 deletions(-)
drivers/regulator/qcom_spmi-regulator.c +130 -3
@@ -25,6 +25,8 @@#include <linux/regulator/driver.h> #include <linux/regmap.h> #include <linux/list.h> +#include <linux/mfd/syscon.h> +#include <linux/io.h> /* Pin control enable input pins. */ #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
@@ -181,6 +183,23 @@ enum spmi_boost_byp_registers { SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b, }; +enum spmi_saw3_registers { +SAW3_SECURE =0x00 , +SAW3_ID =0x04 , +SAW3_SPM_STS =0x0C , +SAW3_AVS_STS =0x10 , +SAW3_PMIC_STS =0x14 , +SAW3_RST =0x18 , +SAW3_VCTL =0x1C , +SAW3_AVS_CTL =0x20 , +SAW3_AVS_LIMIT =0x24 , +SAW3_AVS_DLY =0x28 , +SAW3_AVS_HYSTERESIS =0x2C , +SAW3_SPM_STS2 =0x38 , +SAW3_SPM_PMIC_DATA_3 =0x4C , +SAW3_VERSION =0xFD0 , +}; +/* Used for indexing into ctrl_reg. These are offets from 0x40 */ enum spmi_common_control_register_index {SPMI_COMMON_IDX_VOLTAGE_RANGE =0 ,
@@ -1035,6 +1054,89 @@ static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data)return IRQ_HANDLED ; } +#define SAW3_VCTL_DATA_MASK 0xFF +#define SAW3_VCTL_CLEAR_MASK 0x700FF +#define SAW3_AVS_CTL_EN_MASK 0x1 +#define SAW3_AVS_CTL_TGGL_MASK 0x8000000 +#define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00 + +static struct regmap *saw_regmap =NULL ; + +static void spmi_saw_set_vdd (void *data) +{ +u32 vctl, data3, avs_ctl, pmic_sts; +bool avs_enabled = false; +unsigned long timeout; +u8 voltage_sel = *(u8 *)data; + +regmap_read (saw_regmap,SAW3_AVS_CTL , &avs_ctl); +regmap_read (saw_regmap,SAW3_VCTL , &vctl); +regmap_read (saw_regmap,SAW3_SPM_PMIC_DATA_3 , &data3); + +/* select the band */ + vctl &= ~SAW3_VCTL_CLEAR_MASK ; + vctl |= (u32 )voltage_sel; + + data3 &= ~SAW3_VCTL_CLEAR_MASK ; + data3 |= (u32 )voltage_sel; + +/* If AVS is enabled, switch it off during the voltage change */ + avs_enabled =SAW3_AVS_CTL_EN_MASK & avs_ctl; +if (avs_enabled) { + avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK ; +regmap_write (saw_regmap,SAW3_AVS_CTL , avs_ctl); + } + +regmap_write (saw_regmap,SAW3_RST ,1 ); +regmap_write (saw_regmap,SAW3_VCTL , vctl); +regmap_write (saw_regmap,SAW3_SPM_PMIC_DATA_3 , data3); + + timeout = jiffies +usecs_to_jiffies (100 ); +do { +regmap_read (saw_regmap,SAW3_PMIC_STS , &pmic_sts); + pmic_sts &=SAW3_VCTL_DATA_MASK ; +if (pmic_sts == (u32 )voltage_sel) +break ; + +cpu_relax (); + + }while (time_before (jiffies, timeout)); + +/* After successful voltage change, switch the AVS back on */ +if (avs_enabled) { + pmic_sts &=0x3f ; + avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK ; + avs_ctl |= ((pmic_sts -4 ) <<10 ); + avs_ctl |= (pmic_sts <<17 ); + avs_ctl |=SAW3_AVS_CTL_TGGL_MASK ; +regmap_write (saw_regmap,SAW3_AVS_CTL , avs_ctl); + } +} + +static int +spmi_regulator_saw_set_voltage (struct regulator_dev *rdev,unsigned selector) +{ +struct spmi_regulator *vreg =rdev_get_drvdata (rdev); +int ret; +u8 range_sel, voltage_sel; + + ret =spmi_sw_selector_to_hw (vreg, selector, &range_sel, &voltage_sel); +if (ret) +return ret; + +if (0 != range_sel) { +dev_dbg (&rdev->dev,"range_sel = %02X voltage_sel = %02X" , \ + range_sel, voltage_sel); +return -EINVAL ; + } + +/* Always do the SAW register writes on the first CPU */ +return smp_call_function_single (0 , spmi_saw_set_vdd, \ + &voltage_sel, true); +} + +static struct regulator_ops spmi_saw_ops = {}; +static struct regulator_ops spmi_smps_ops = { .enable = regulator_enable_regmap, .disable = regulator_disable_regmap,
@@ -1250,6 +1352,7 @@ static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type) } dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV -SPMI_COMMON_REG_DIG_MAJOR_REV ]; +if (!force_type) { type = version[SPMI_COMMON_REG_TYPE -SPMI_COMMON_REG_DIG_MAJOR_REV ];
@@ -1648,7 +1751,9 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev)struct regmap *regmap;const char *name;struct device *dev = &pdev->dev; -int ret; +struct device_node *node = pdev->dev.of_node; +struct device_node *syscon; +int ret, lenp;struct list_head *vreg_list; vreg_list =devm_kzalloc (dev,sizeof (*vreg_list),GFP_KERNEL );
@@ -1665,7 +1770,22 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev)if (!match)return -ENODEV ; +if (of_find_property (node,"qcom,saw-reg" , &lenp)) { + syscon =of_parse_phandle (node,"qcom,saw-reg" ,0 ); + saw_regmap =syscon_node_to_regmap (syscon); +of_node_put (syscon); +if (IS_ERR (regmap)) +dev_err (dev,"ERROR reading SAW regmap\n" ); + } +for (reg = match->data; reg->name; reg++) { + +if (saw_regmap && \ +of_find_property (of_find_node_by_name (node, reg->name), \ +"qcom,saw-slave" , &lenp)) { +continue ; + } + vreg =devm_kzalloc (dev,sizeof (*vreg),GFP_KERNEL );if (!vreg)return -ENOMEM ;
@@ -1673,7 +1793,6 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev) vreg->dev = dev; vreg->base = reg->base; vreg->regmap = regmap; -if (reg->ocp) { vreg->ocp_irq =platform_get_irq_byname (pdev, reg->ocp);if (vreg->ocp_irq <0 ) {
@@ -1681,7 +1800,6 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev) goto err; } } - vreg->desc.id =-1 ; vreg->desc.owner =THIS_MODULE ; vreg->desc.type =REGULATOR_VOLTAGE ;
@@ -1698,6 +1816,15 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev)if (ret)continue ; +if (saw_regmap && \ +of_find_property (of_find_node_by_name (node, reg->name), \ +"qcom,saw-leader" , &lenp)) { + spmi_saw_ops = *(vreg->desc.ops); + spmi_saw_ops.set_voltage_sel = \ + spmi_regulator_saw_set_voltage; + vreg->desc.ops = &spmi_saw_ops; + } + config.dev = dev; config.driver_data = vreg; config.regmap = regmap;
Signature · 1 line
1.9.1
PATCH v5 10/14 dt-bindings: qcom_spmi: Add support for SAW documentation
In reply to Ilia LinAdd support for SAW controlled regulators.
The regulators defined as SAW controlled in the device tree will be controlled through special CPU registers instead of direct SPMI accesses.
This is required especially for CPU supply regulators to synchronize with clock scaling and for Automatic Voltage Switching. Document it.
--- .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+)
Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt +45 -0
@@ -110,6 +110,11 @@ Qualcomm SPMI Regulators Definition: Reference to regulator supplying the input pin, as described in the data sheet. +- qcom,saw-reg: + Usage: optional + Value type: <phandle> + Description: Reference to syscon node defining the SAW registers. + The regulator node houses sub-nodes for each regulator within the device. Each sub-node is identified using the node's name, with valid values listed for each
@@ -201,6 +206,17 @@ see regulator.txt - with additional custom properties described below: 2 = 0.55 uA 3 = 0.75 uA +- qcom,saw-slave: + Usage: optional + Value type: <boo> + Description: SAW controlled gang slave. Will not be configured. + +- qcom,saw-leader: + Usage: optional + Value type: <boo> + Description: SAW controlled gang leader. Will be configured as + SAW regulator. + Example: regulators {
@@ -221,3 +237,32 @@ Example: .... }; + +Example 2: + + saw3: syscon at 9A10000 { + compatible = "syscon"; + reg = <0x9A10000 0x1000>; + }; + + ... + + spm-regulators { + compatible = "qcom,pm8994-regulators"; + qcom,saw-reg = <&saw3>; + s8 { + qcom,saw-slave; + }; + s9 { + qcom,saw-slave; + }; + s10 { + qcom,saw-slave; + }; + pm8994_s11_saw: s11 { + qcom,saw-leader; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1140000>; + }; + };
Signature · 1 line
1.9.1
Re: [PATCH v5 10/14] dt-bindings: qcom_spmi: Add support for SAW documentation
Quoted 8 lines · Ilia Lin
Add support for SAW controlled regulators.
The regulators defined as SAW controlled in the device tree will be controlled through special CPU registers instead of direct SPMI accesses.
This is required especially for CPU supply regulators to synchronize with clock scaling and for Automatic Voltage Switching. Document it.
Quoted 4 lines
Signed-off-by Ilia Lin <[email protected]>--- .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+)
PATCH v5 11/14 dt: qcom: Add SAW regulator for 8x96 CPUs
In reply to Ilia Lin1. Add syscon node for the SAW CPU registers
2. Add SAW regulators gang definition for s8-s11
3. Add voltages to the OPP tables
4. Add the s11 SAW regulator as CPU regulator
--- arch/arm64/boot/dts/qcom/msm8996.dtsi | 75 +++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+)
arch/arm64/boot/dts/qcom/msm8996.dtsi +75 -0
@@ -15,6 +15,7 @@ #include <dt-bindings/clock/qcom,mmcc-msm8996.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/spmi/spmi.h> / { model = "Qualcomm Technologies, Inc. MSM8996";
@@ -99,6 +100,7 @@ reg = <0x0 0x0>; enable-method = "psci"; clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; next-level-cache = <&L2_0>;
@@ -114,6 +116,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; next-level-cache = <&L2_0>;
@@ -125,6 +128,7 @@ reg = <0x0 0x100>; enable-method = "psci"; clocks = <&kryocc 1>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; next-level-cache = <&L2_1>;
@@ -140,6 +144,7 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&kryocc 1>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; next-level-cache = <&L2_1>;
@@ -174,66 +179,82 @@ opp-307200000 { opp-hz = /bits/ 64 <307200000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-422400000 { opp-hz = /bits/ 64 <422400000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-960000000 { opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; };
@@ -244,102 +265,127 @@ opp-307200000 { opp-hz = /bits/ 64 <307200000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-883200000 { opp-hz = /bits/ 64 <883200000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; };
@@ -656,6 +702,10 @@ #mbox-cells = <1>; }; + saw3: syscon at 9A10000 { + compatible = "syscon"; + reg = <0x9A10000 0x1000>; + }; gcc: clock-controller at 300000 { compatible = "qcom,gcc-msm8996"; #clock-cells = <1>;
@@ -882,6 +932,31 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; + pmic at 1 { + compatible = "qcom,pm8994", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + spm-regulators { + compatible = "qcom,pm8994-regulators"; + qcom,saw-reg = <&saw3>; + s8 { + qcom,saw-slave; + }; + s9 { + qcom,saw-slave; + }; + s10 { + qcom,saw-slave; + }; + pm8994_s11_saw: s11 { + qcom,saw-leader; + regulator-always-on; + regulator-min-microvolt = <905000>; + regulator-max-microvolt = <1140000>; + }; + }; + }; }; mmcc: clock-controller at 8c0000 {
Signature · 1 line
1.9.1
PATCH v5 12/14 cpufreq: Add Kryo CPU scaling driver
In reply to Ilia LinIn Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination.
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework.
--- drivers/cpufreq/Kconfig.arm | 11 +++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/cpufreq-dt-platdev.c | 3 + drivers/cpufreq/qcom-cpufreq-kryo.c | 153 +++++++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
drivers/cpufreq/Kconfig.arm +11 -0
@@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS +config ARM_QCOM_CPUFREQ_KRYO + tristate "Qualcomm Technologies, Inc. Kryo based CPUFreq" + depends on QCOM_QFPROM + depends on QCOM_SMEM + select PM_OPP + help + This adds the CPUFreq driver for + Qualcomm Technologies, Inc. Kryo SoC based boards. + + If in doubt, say N. + config ARM_S3C_CPUFREQ bool help
drivers/cpufreq/Makefile +1 -0
@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
drivers/cpufreq/cpufreq-dt-platdev.c +3 -0
@@ -118,6 +118,9 @@ { .compatible = "nvidia,tegra124", }, + { .compatible = "qcom,apq8096", }, + { .compatible = "qcom,msm8996", }, + { .compatible = "st,stih407", }, { .compatible = "st,stih410", },
drivers/cpufreq/qcom-cpufreq-kryo.c new file +153 -0
153 lines not on this page · raw message
Signature · 1 line
1.9.1
Viresh Kumar
maintainerRe: [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driver
Quoted 24 lines · Ilia Lin
In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination.
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework.Signed-off-by Ilia Lin <[email protected]>--- drivers/cpufreq/Kconfig.arm | 11 +++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/cpufreq-dt-platdev.c | 3 + drivers/cpufreq/qcom-cpufreq-kryo.c | 153 +++++++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.cdrivers/cpufreq/Kconfig.arm +0
-0
drivers/cpufreq/Kconfig.arm config ARM_OMAP2PLUS_CPUFREQ · line 128
Quoted 5 lines
drivers/cpufreq/Kconfig.arm +2
-0@@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS +config ARM_QCOM_CPUFREQ_KRYO + tristate "Qualcomm Technologies, Inc. Kryo based CPUFreq"
I don't see any reply to Sricharan's query on this being tristate.
Quoted 44 lines
drivers/cpufreq/Kconfig.arm +9
-0+ depends on QCOM_QFPROM + depends on QCOM_SMEM + select PM_OPP + help + This adds the CPUFreq driver for + Qualcomm Technologies, Inc. Kryo SoC based boards. + + If in doubt, say N. + config ARM_S3C_CPUFREQ bool helpdrivers/cpufreq/Makefile +1
-0@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.odrivers/cpufreq/cpufreq-dt-platdev.c +3
-0@@ -118,6 +118,9 @@ { .compatible = "nvidia,tegra124", }, + { .compatible = "qcom,apq8096", }, + { .compatible = "qcom,msm8996", }, + { .compatible = "st,stih407", }, { .compatible = "st,stih410", },drivers/cpufreq/qcom-cpufreq-kryo.c new file +0
-0
drivers/cpufreq/qcom-cpufreq-kryo.c line 2
Quoted 2 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +2
-0@@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
Incorrect multi line comment.
Quoted 5 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +5
-0+* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +*
drivers/cpufreq/qcom-cpufreq-kryo.c line 17
Quoted 10 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +10
-0+* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/cpu.h> +#include <linux/err.h> +#include <linux/init.h> +//#include <linux/io.h>
??
Quoted 110 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +110
-0+#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_opp.h> +#include <linux/slab.h> +#include <linux/soc/qcom/smem.h> + +#define MSM_ID_SMEM 137 +#define SILVER_LEAD 0 +#define GOLD_LEAD 2 + +enum _msm_id { +MSM8996V3 =0xF6ul , +APQ8096V3 =0x123ul , +MSM8996SG =0x131ul , +APQ8096SG =0x138ul , +}; + +enum _msm8996_version { +MSM8996_V3 , +MSM8996_SG , +NUM_OF_MSM8996_VERSIONS , +}; + +static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id (void ) +{ +size_t len; +u32 *msm_id; +enum _msm8996_version version; + + msm_id =qcom_smem_get (QCOM_SMEM_HOST_ANY ,MSM_ID_SMEM , &len); +/* The first 4 bytes are format, next to them is the actual msm-id */ + msm_id++; + +switch ((enum _msm_id )*msm_id) { +case MSM8996V3 : +case APQ8096V3 : + version =MSM8996_V3 ; +break ; +case MSM8996SG : +case APQ8096SG : + version =MSM8996_SG ; +break ; +default : + version =NUM_OF_MSM8996_VERSIONS ; + } + +return version; +} + +static int __init qcom_cpufreq_kryo_driver_init (void ) +{ +size_t len; +int ret; +u32 versions; +enum _msm8996_version msm8996_version; +u8 *speedbin; +struct platform_device *pdev; +struct device *cpu_dev; +struct device_node *np; +struct nvmem_cell *speedbin_nvmem; +struct opp_table *opp_temp =NULL ; + + cpu_dev =get_cpu_device (SILVER_LEAD ); +if (IS_ERR_OR_NULL (cpu_dev)) +return PTR_ERR (cpu_dev); + + msm8996_version =qcom_cpufreq_kryo_get_msm_id (); +if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { +dev_err (cpu_dev,"Not Snapdragon 820/821!" ); +return -ENODEV ; + } + + np =dev_pm_opp_of_get_opp_desc_node (cpu_dev); +if (IS_ERR_OR_NULL (np)) +return PTR_ERR (np); + +if (!of_device_is_compatible (np,"operating-points-v2-kryo-cpu" )) { + ret = -ENOENT ; + goto free_np; + } + + speedbin_nvmem =of_nvmem_cell_get (np,NULL ); +if (IS_ERR (speedbin_nvmem)) { + ret =PTR_ERR (speedbin_nvmem); +dev_err (cpu_dev,"Could not get nvmem cell: %d\n" , ret); + goto free_np; + } + + speedbin =nvmem_cell_read (speedbin_nvmem, &len); + +switch (msm8996_version) { +case MSM8996_V3 : + versions =1 << (unsigned int )(*speedbin); +break ; +case MSM8996_SG : + versions =1 << ((unsigned int )(*speedbin) +4 ); +break ; +default : +BUG (); +break ; + } + + ret =PTR_ERR_OR_ZERO (opp_temp = \ +dev_pm_opp_set_supported_hw (cpu_dev,&versions,1 )); +if (0 > ret) + goto free_np; +
drivers/cpufreq/qcom-cpufreq-kryo.c line 137
Quoted 10 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +10
-0+ cpu_dev =get_cpu_device (GOLD_LEAD ); + ret =PTR_ERR_OR_ZERO (dev_pm_opp_set_supported_hw (cpu_dev,&versions,1 )); +if (0 > ret) + goto put_supported_hw_silver; + +of_node_put (np); + + pdev =platform_device_register_simple ("cpufreq-dt" ,-1 ,NULL ,0 ); +if (IS_ERR (pdev)) { +return PTR_ERR (pdev);
Don't need to free resources on error here ?
Quoted 18 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +16
-0+ } + +return 0 ; + +put_supported_hw_silver: +dev_pm_opp_put_supported_hw (opp_temp); + +free_np: +of_node_put (np); + +return ret; +} +late_initcall (qcom_cpufreq_kryo_driver_init); + +MODULE_DESCRIPTION ("Qualcomm Technologies, Inc. Kryo CPUfreq driver" ); +MODULE_LICENSE ("GPL v2" );Signature · 1 line
1.9.1
Signature · 1 line
viresh
RE: [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driver
Quoted 48 lines
-----Original Message-----
From: Viresh Kumar <[email protected]>
Sent: Friday, May 4, 2018 09:08
To: Ilia Lin <[email protected]>
Cc: mturquette at baylibre.com; sboyd at kernel.org; robh at kernel.org; mark.rutland at arm.com; rjw at rjwysocki.net; lgirdwood at gmail.com; broonie at kernel.org; andy.gross at linaro.org; david.brown at linaro.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux- pm at vger.kernel.org; linux-arm-msm at vger.kernel.org; linux-
soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org; rnayak at codeaurora.org; amit.kucheria at linaro.org; nicolas.dechesne at linaro.org; celster at codeaurora.org;
tfinkel at codeaurora.org
Subject: Re: [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driverQuoted 29 lines · Ilia Lin
In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information. This is used to determine the voltage and frequency value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.Signed-off-by Ilia Lin <[email protected]>--- drivers/cpufreq/Kconfig.arm | 11 +++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/cpufreq-dt-platdev.c | 3 + drivers/cpufreq/qcom-cpufreq-kryo.c | 153 +++++++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.cdrivers/cpufreq/Kconfig.arm +0
-0@@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS
Quoted 4 lines
drivers/cpufreq/Kconfig.arm config ARM_OMAP2PLUS_CPUFREQ · line 128
Quoted 2 lines
drivers/cpufreq/Kconfig.arm +2
-0+config ARM_QCOM_CPUFREQ_KRYO + tristate "Qualcomm Technologies, Inc. Kryo based CPUFreq"I don't see any reply to Sricharan's query on this being tristate.
Why shouldn't we leave possibility to compile the cpufreq-dt built-in, and the qcom-cpufreq-kryo module?
Quoted 42 lines
drivers/cpufreq/Makefile obj-$(CONFIG_MACH_MVEBU_V7) +=
Quoted 18 lines
drivers/cpufreq/Kconfig.arm +9
-0+ depends on QCOM_QFPROM + depends on QCOM_SMEM + select PM_OPP + help + This adds the CPUFreq driver for + Qualcomm Technologies, Inc. Kryo SoC based boards. + + If in doubt, say N. + config ARM_S3C_CPUFREQ bool helpdrivers/cpufreq/Makefile index renamed from drivers/cpufreq/Makefile +0
-08d24ade..fb4a2ec 100644
drivers/cpufreq/Makefile +0
-0@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) +=mvebu-cpufreq.o
drivers/cpufreq/Makefile obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
Quoted 4 lines
drivers/cpufreq/Makefile +1
-0obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
Quoted 18 lines
drivers/cpufreq/Makefile +0
-0obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.odrivers/cpufreq/cpufreq-dt-platdev.c +3
-0@@ -118,6 +118,9 @@ { .compatible = "nvidia,tegra124", }, + { .compatible = "qcom,apq8096", }, + { .compatible = "qcom,msm8996", }, + { .compatible = "st,stih407", }, { .compatible = "st,stih410", },
Quoted 11 lines
drivers/cpufreq/qcom-cpufreq-kryo.c line 2
Quoted 9 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +2
-0@@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. Incorrect multi line comment.
This was done as per Bjorn's instruction.
Quoted 11 lines
Quoted 11 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +10
-0+* +* This program is free software; you can redistribute it and/or +modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details.
Quoted 8 lines
drivers/cpufreq/qcom-cpufreq-kryo.c line 17
Quoted 6 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +6
-0+*/ + +#include <linux/cpu.h> +#include <linux/err.h> +#include <linux/init.h> +//#include <linux/io.h> ??
Not good. Will fix this.bbbbbbbb
Quoted 36 lines
Quoted 25 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +24
-0+#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_opp.h> +#include <linux/slab.h> +#include <linux/soc/qcom/smem.h> + +#define MSM_ID_SMEM 137 +#define SILVER_LEAD 0 +#define GOLD_LEAD 2 + +enum _msm_id { +MSM8996V3 =0xF6ul , +APQ8096V3 =0x123ul , +MSM8996SG =0x131ul , +APQ8096SG =0x138ul , +}; + +enum _msm8996_version { +MSM8996_V3 , +MSM8996_SG , +NUM_OF_MSM8996_VERSIONS ,drivers/cpufreq/qcom-cpufreq-kryo.c
Quoted 10 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +10
-0+}; + +static enum _msm8996_version __init +qcom_cpufreq_kryo_get_msm_id (void ) +{ +size_t len; +u32 *msm_id; +enum _msm8996_version version; + + msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY,
MSM_ID_SMEM, &len);
Quoted 1 line
drivers/cpufreq/qcom-cpufreq-kryo.c line 53
Quoted 1 line
drivers/cpufreq/qcom-cpufreq-kryo.c new file +1
-0+/* The first 4 bytes are format, next to them is the actual msm-id
*/
Quoted 81 lines
Quoted 63 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +63
-0+ msm_id++; + +switch ((enum _msm_id )*msm_id) { +case MSM8996V3 : +case APQ8096V3 : + version =MSM8996_V3 ; +break ; +case MSM8996SG : +case APQ8096SG : + version =MSM8996_SG ; +break ; +default : + version =NUM_OF_MSM8996_VERSIONS ; + } + +return version; +} + +static int __init qcom_cpufreq_kryo_driver_init (void ) +{ +size_t len; +int ret; +u32 versions; +enum _msm8996_version msm8996_version; +u8 *speedbin; +struct platform_device *pdev; +struct device *cpu_dev; +struct device_node *np; +struct nvmem_cell *speedbin_nvmem; +struct opp_table *opp_temp =NULL ; + + cpu_dev =get_cpu_device (SILVER_LEAD ); +if (IS_ERR_OR_NULL (cpu_dev)) +return PTR_ERR (cpu_dev); + + msm8996_version =qcom_cpufreq_kryo_get_msm_id (); +if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { +dev_err (cpu_dev,"Not Snapdragon 820/821!" ); +return -ENODEV ; + } + + np =dev_pm_opp_of_get_opp_desc_node (cpu_dev); +if (IS_ERR_OR_NULL (np)) +return PTR_ERR (np); + +if (!of_device_is_compatible (np,"operating-points-v2-kryo-cpu" )) { + ret = -ENOENT ; + goto free_np; + } + + speedbin_nvmem =of_nvmem_cell_get (np,NULL ); +if (IS_ERR (speedbin_nvmem)) { + ret =PTR_ERR (speedbin_nvmem); +dev_err (cpu_dev,"Could not get nvmem cell: %d\n" , ret); + goto free_np; + } + + speedbin =nvmem_cell_read (speedbin_nvmem, &len); + +switch (msm8996_version) { +case MSM8996_V3 : + versions =1 << (unsigned int )(*speedbin); +break ;drivers/cpufreq/qcom-cpufreq-kryo.c line 127
Quoted 10 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +10
-0+case MSM8996_SG : + versions =1 << ((unsigned int )(*speedbin) +4 ); +break ; +default : +BUG (); +break ; + } + + ret = PTR_ERR_OR_ZERO(opp_temp = \ +
dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));drivers/cpufreq/qcom-cpufreq-kryo.c
Quoted 5 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +5
-0+if (0 > ret) + goto free_np; + + cpu_dev =get_cpu_device (GOLD_LEAD ); + ret =
PTR_ERR_OR_ZERO(dev_pm_opp_set_supported_hw(cpu_dev,&versions,1 ));
Quoted 10 lines
drivers/cpufreq/qcom-cpufreq-kryo.c line 137
Quoted 8 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +8
-0+if (0 > ret) + goto put_supported_hw_silver; + +of_node_put (np); + + pdev =platform_device_register_simple ("cpufreq-dt" ,-1 ,NULL ,0 ); +if (IS_ERR (pdev)) { +return PTR_ERR (pdev);Don't need to free resources on error here ?
You are right. Will fix.
Quoted 22 lines
Quoted 18 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +16
-1+ } + +return 0 ; + +put_supported_hw_silver: +dev_pm_opp_put_supported_hw (opp_temp); + +free_np: +of_node_put (np); + +return ret; +} +late_initcall (qcom_cpufreq_kryo_driver_init); + +MODULE_DESCRIPTION ("Qualcomm Technologies, Inc. Kryo CPUfreq +driver"); MODULE_LICENSE("GPL v2"); --Quoted 1 line
1.9.1
--
viresh
Viresh Kumar
maintainerRe: [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driver
Quoted 48 lines · ilialin at codeaurora.org
Quoted 48 lines
-----Original Message-----
From: Viresh Kumar <[email protected]>
Sent: Friday, May 4, 2018 09:08
To: Ilia Lin <[email protected]>
Cc: mturquette at baylibre.com; sboyd at kernel.org; robh at kernel.org; mark.rutland at arm.com; rjw at rjwysocki.net; lgirdwood at gmail.com; broonie at kernel.org; andy.gross at linaro.org; david.brown at linaro.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux- pm at vger.kernel.org; linux-arm-msm at vger.kernel.org; linux-
soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org; rnayak at codeaurora.org; amit.kucheria at linaro.org; nicolas.dechesne at linaro.org; celster at codeaurora.org;
tfinkel at codeaurora.org
Subject: Re: [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driverQuoted 29 lines · Ilia Lin
In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information. This is used to determine the voltage and frequency value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.Signed-off-by Ilia Lin <[email protected]>--- drivers/cpufreq/Kconfig.arm | 11 +++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/cpufreq-dt-platdev.c | 3 + drivers/cpufreq/qcom-cpufreq-kryo.c | 153 +++++++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.cdrivers/cpufreq/Kconfig.arm +0
-0@@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS
Quoted 7 lines
Quoted 4 lines
drivers/cpufreq/Kconfig.arm config ARM_OMAP2PLUS_CPUFREQ · line 128
Quoted 2 lines
drivers/cpufreq/Kconfig.arm +2
-0+config ARM_QCOM_CPUFREQ_KRYO + tristate "Qualcomm Technologies, Inc. Kryo based CPUFreq"I don't see any reply to Sricharan's query on this being tristate.
Why shouldn't we leave possibility to compile the cpufreq-dt built-in, and the qcom-cpufreq-kryo module?
I was not saying this is incorrect, all I am saying is that you never replied to a comment from one of the reviewers.
And I don't see a reason why this should be a tristate really. cpufreq-dt is already capable of being a module, all your driver does is that it creates the cpufreq-dt platform device after setting the OPP hw properties..
Over that, have you ever tried inserting, then removing and inserting the driver module again? I feel it will fail.
The reason is that you never provided an exit routine which can get rid of the platform device created in the first place.
Quoted 53 lines
Quoted 41 lines
drivers/cpufreq/Makefile obj-$(CONFIG_MACH_MVEBU_V7) +=
Quoted 17 lines
drivers/cpufreq/Kconfig.arm +9
-0+ depends on QCOM_QFPROM + depends on QCOM_SMEM + select PM_OPP + help + This adds the CPUFreq driver for + Qualcomm Technologies, Inc. Kryo SoC based boards. + + If in doubt, say N. + config ARM_S3C_CPUFREQ bool helpdrivers/cpufreq/Makefile index renamed from drivers/cpufreq/Makefile +0
-08d24ade..fb4a2ec 100644
drivers/cpufreq/Makefile +0
-0@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) +=mvebu-cpufreq.o
drivers/cpufreq/Makefile obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
Quoted 4 lines
drivers/cpufreq/Makefile +1
-0obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
Quoted 18 lines
drivers/cpufreq/Makefile +0
-0obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.odrivers/cpufreq/cpufreq-dt-platdev.c +3
-0@@ -118,6 +118,9 @@ { .compatible = "nvidia,tegra124", }, + { .compatible = "qcom,apq8096", }, + { .compatible = "qcom,msm8996", }, + { .compatible = "st,stih407", }, { .compatible = "st,stih410", },Quoted 11 lines
drivers/cpufreq/qcom-cpufreq-kryo.c line 2
Quoted 9 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +2
-0@@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. Incorrect multi line comment.
Quoted 1 line
This was done as per Bjorn's instruction.
You haven't followed him correctly.
What he asked for is:
// SPDX...
/*
* XXXX
*/
What you have done is:
// SPDX...
/* XXXX
*/
Signature · 1 line
viresh
RE: [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driver
Quoted 74 lines
-----Original Message-----
From: Viresh Kumar <[email protected]>
Sent: Friday, May 4, 2018 09:57
To: ilialin at codeaurora.org
Cc: mturquette at baylibre.com; sboyd at kernel.org; robh at kernel.org; mark.rutland at arm.com; rjw at rjwysocki.net; lgirdwood at gmail.com; broonie at kernel.org; andy.gross at linaro.org; david.brown at linaro.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux- pm at vger.kernel.org; linux-arm-msm at vger.kernel.org; linux-
soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org; rnayak at codeaurora.org; amit.kucheria at linaro.org; nicolas.dechesne at linaro.org; celster at codeaurora.org;
tfinkel at codeaurora.org
Subject: Re: [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driverQuoted 19 lines · ilialin at codeaurora.org
Quoted 19 lines
-----Original Message-----
From: Viresh Kumar <[email protected]>
Sent: Friday, May 4, 2018 09:08
To: Ilia Lin <[email protected]>
Cc: mturquette at baylibre.com; sboyd at kernel.org; robh at kernel.org; mark.rutland at arm.com; rjw at rjwysocki.net; lgirdwood at gmail.com; broonie at kernel.org; andy.gross at linaro.org; david.brown at linaro.org; catalin.marinas at arm.com; will.deacon at arm.com;
linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux- pm at vger.kernel.org; linux-arm-msm at vger.kernel.org; linux- soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
rnayak at codeaurora.org; amit.kucheria at linaro.org; nicolas.dechesne at linaro.org; celster at codeaurora.org; tfinkel at codeaurora.org
Subject: Re: [PATCH v5 12/14] cpufreq: Add Kryo CPU scaling driverQuoted 6 lines
Quoted 6 lines · Ilia Lin
Quoted 5 lines
In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse
combination.
Quoted 29 lines
Quoted 28 lines
Quoted 21 lines
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information. This is used to determine the voltage and frequency value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.Signed-off-by Ilia Lin <[email protected]>--- drivers/cpufreq/Kconfig.arm | 11 +++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/cpufreq-dt-platdev.c | 3 + drivers/cpufreq/qcom-cpufreq-kryo.c | 153 +++++++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644
drivers/cpufreq/qcom-cpufreq-kryo.c(quoted diff) +0
-0b/drivers/cpufreq/Kconfig.arm index de55c7d..f9da18c 100644
drivers/cpufreq/Kconfig.arm config ARM_OMAP2PLUS_CPUFREQ · line 128
Quoted 5 lines
drivers/cpufreq/Kconfig.arm +2
-0@@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS +config ARM_QCOM_CPUFREQ_KRYO + tristate "Qualcomm Technologies, Inc. Kryo based CPUFreq"I don't see any reply to Sricharan's query on this being tristate.
Quoted 4 lines
Quoted 2 lines
Why shouldn't we leave possibility to compile the cpufreq-dt built-in, and the qcom-cpufreq-kryo module?
I was not saying this is incorrect, all I am saying is that you never
replied to a
Quoted 4 lines
comment from one of the reviewers.
And I don't see a reason why this should be a tristate really. cpufreq-dt is already capable of being a module, all your driver does is
that it
Quoted 1 line
creates the cpufreq-dt platform device after setting the OPP hw
properties..
Quoted 5 lines
Over that, have you ever tried inserting, then removing and inserting the driver module again? I feel it will fail.
The reason is that you never provided an exit routine which can get rid of
the
Quoted 1 line
platform device created in the first place.
Convinced. I'll change it to bool.
Quoted 65 lines
Quoted 54 lines
Quoted 42 lines
drivers/cpufreq/Makefile obj-$(CONFIG_MACH_MVEBU_V7) +=
Quoted 18 lines
drivers/cpufreq/Kconfig.arm +9
-0+ depends on QCOM_QFPROM + depends on QCOM_SMEM + select PM_OPP + help + This adds the CPUFreq driver for + Qualcomm Technologies, Inc. Kryo SoC based boards. + + If in doubt, say N. + config ARM_S3C_CPUFREQ bool helpdrivers/cpufreq/Makefile +0
-0@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) +=mvebu-cpufreq.o
drivers/cpufreq/Makefile obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
Quoted 4 lines
drivers/cpufreq/Makefile +1
-0obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
Quoted 18 lines
drivers/cpufreq/Makefile +0
-0obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.odrivers/cpufreq/cpufreq-dt-platdev.c +3
-0@@ -118,6 +118,9 @@ { .compatible = "nvidia,tegra124", }, + { .compatible = "qcom,apq8096", }, + { .compatible = "qcom,msm8996", }, + { .compatible = "st,stih407", }, { .compatible = "st,stih410", },Quoted 11 lines
drivers/cpufreq/qcom-cpufreq-kryo.c line 2
Quoted 9 lines
drivers/cpufreq/qcom-cpufreq-kryo.c new file +2
-0@@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. Incorrect multi line comment.
Quoted 1 line
This was done as per Bjorn's instruction.
You haven't followed him correctly.
What he asked for is:
// SPDX...
/*
* XXXX
*/
Quoted 5 lines
What you have done is:
// SPDX...
/* XXXX
*/
OK. Got you. Will fix.
Quoted 3 lines
--
viresh
PATCH v5 13/14 dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
In reply to Ilia LinIn Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination.
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework.
This change adds documentation.
--- .../devicetree/bindings/opp/kryo-cpufreq.txt | 693 +++++++++++++++++++++ 1 file changed, 693 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +693 -0
@@ -0,0 +1,693 @@ +Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings +=================================== + +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 +that have KRYO processors, the CPU ferequencies subset and voltage value +of each OPP varies based on the silicon variant in use. +Qualcomm Technologies, Inc. Process Voltage Scaling Tables +defines the voltage and frequency value based on the msm-id in SMEM +and speedbin blown in the efuse combination. +The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC +to provide the OPP framework with required information (existing HW bitmap). +This is used to determine the voltage and frequency value for each OPP of +operating-points-v2 table when it is parsed by the OPP framework. + +Required properties: +-------------------- +In 'cpus' nodes: +- operating-points-v2: Phandle to the operating-points-v2 table to use. + +In 'operating-points-v2' table: +- compatible: Should be + - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the + efuse registers that has information about the + speedbin that is used to select the right frequency/voltage + value pair. + Please refer the for nvmem-cells + bindings Documentation/devicetree/bindings/nvmem/nvmem.txt + and also examples below. + +In every OPP node: +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW. + Bitmap: + 0: MSM8996 V3, speedbin 0 + 1: MSM8996 V3, speedbin 1 + 2: MSM8996 V3, speedbin 2 + 3: unused + 4: MSM8996 SG, speedbin 0 + 5: MSM8996 SG, speedbin 1 + 6: MSM8996 SG, speedbin 2 + 7-31: unused + +Example 1: +--------- + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; + operating-points-v2 = <&cluster0_opp>; + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <15>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; + operating-points-v2 = <&cluster0_opp>; + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <15>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu at 100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + clocks = <&kryocc 1>; + cpu-supply = <&pm8994_s11_saw>; + operating-points-v2 = <&cluster1_opp>; + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <15>; + #cooling-cells = <2>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU3: cpu at 101 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x101>; + enable-method = "psci"; + clocks = <&kryocc 1>; + cpu-supply = <&pm8994_s11_saw>; + operating-points-v2 = <&cluster1_opp>; + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <15>; + #cooling-cells = <2>; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU2>; + }; + + core1 { + cpu = <&CPU3>; + }; + }; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 < 307200000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 < 384000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-422400000 { + opp-hz = /bits/ 64 < 422400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-460800000 { + opp-hz = /bits/ 64 < 460800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 < 480000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-537600000 { + opp-hz = /bits/ 64 < 537600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 < 556800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-614400000 { + opp-hz = /bits/ 64 < 614400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 < 652800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 < 691200000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 < 729600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-768000000 { + opp-hz = /bits/ 64 < 768000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-844800000 { + opp-hz = /bits/ 64 < 844800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 < 902400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-960000000 { + opp-hz = /bits/ 64 < 960000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-979200000 { + opp-hz = /bits/ 64 < 979200000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 < 1036800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 < 1056000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 < 1113600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 < 1132800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 < 1190400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 < 1209600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1228800000 { + opp-hz = /bits/ 64 < 1228800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 < 1286400000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 < 1324800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x5>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 < 1363200000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x72>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 < 1401600000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x5>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 < 1440000000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 < 1478400000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + opp-1497600000 { + opp-hz = /bits/ 64 < 1497600000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x4>; + clock-latency-ns = <200000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 < 1516800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 < 1593600000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x71>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 < 1996800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x20>; + clock-latency-ns = <200000>; + }; + opp-2188800000 { + opp-hz = /bits/ 64 < 2188800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x10>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 < 307200000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 < 384000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-403200000 { + opp-hz = /bits/ 64 < 403200000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-460800000 { + opp-hz = /bits/ 64 < 460800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 < 480000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-537600000 { + opp-hz = /bits/ 64 < 537600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 < 556800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-614400000 { + opp-hz = /bits/ 64 < 614400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 < 652800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 < 691200000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 < 729600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-748800000 { + opp-hz = /bits/ 64 < 748800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 < 806400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-825600000 { + opp-hz = /bits/ 64 < 825600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-883200000 { + opp-hz = /bits/ 64 < 883200000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 < 902400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 < 940800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-979200000 { + opp-hz = /bits/ 64 < 979200000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 < 1036800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 < 1056000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 < 1113600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 < 1132800000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 < 1190400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 < 1209600000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 < 1248000000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 < 1286400000 >; + opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 < 1324800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 < 1363200000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 < 1401600000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 < 1440000000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 < 1478400000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 < 1516800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 < 1555200000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 < 1593600000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 < 1632000000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 < 1670400000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1708800000 { + opp-hz = /bits/ 64 < 1708800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 < 1747200000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 < 1785600000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1804800000 { + opp-hz = /bits/ 64 < 1804800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x6>; + clock-latency-ns = <200000>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 < 1824000000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x71>; + clock-latency-ns = <200000>; + }; + opp-1900800000 { + opp-hz = /bits/ 64 < 1900800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x74>; + clock-latency-ns = <200000>; + }; + opp-1920000000 { + opp-hz = /bits/ 64 < 1920000000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 < 1977600000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x30>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 < 1996800000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + opp-2054400000 { + opp-hz = /bits/ 64 < 2054400000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x30>; + clock-latency-ns = <200000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 < 2073600000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 < 2150400000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x31>; + clock-latency-ns = <200000>; + }; + opp-2246400000 { + opp-hz = /bits/ 64 < 2246400000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x10>; + clock-latency-ns = <200000>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 < 2342400000 >; + opp-microvolt = <1140000 905000 1140000>; + opp-supported-hw = <0x10>; + clock-latency-ns = <200000>; + }; + + }; + +.... + +reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; +.... + smem_mem: smem-mem at 86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + }; +.... +}; + +smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; +}; + +soc { +.... + qfprom: qfprom at 74000 { + compatible = "qcom,qfprom"; + reg = <0x00074000 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + .... + speedbin_efuse: speedbin at 133 { + reg = <0x133 0x1>; + bits = <5 3>; + }; + }; +};
Signature · 1 line
1.9.1
Viresh Kumar
maintainerRe: [PATCH v5 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
Quoted 75 lines · Ilia Lin
In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination.
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework.This change adds documentation.
Signed-off-by Ilia Lin <[email protected]>--- .../devicetree/bindings/opp/kryo-cpufreq.txt | 693 +++++++++++++++++++++ 1 file changed, 693 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txtDocumentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +50
-0@@ -0,0 +1,693 @@ +Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings +=================================== + +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 +that have KRYO processors, the CPU ferequencies subset and voltage value +of each OPP varies based on the silicon variant in use. +Qualcomm Technologies, Inc. Process Voltage Scaling Tables +defines the voltage and frequency value based on the msm-id in SMEM +and speedbin blown in the efuse combination. +The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC +to provide the OPP framework with required information (existing HW bitmap). +This is used to determine the voltage and frequency value for each OPP of +operating-points-v2 table when it is parsed by the OPP framework. + +Required properties: +-------------------- +In 'cpus' nodes: +- operating-points-v2: Phandle to the operating-points-v2 table to use. + +In 'operating-points-v2' table: +- compatible: Should be + - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the + efuse registers that has information about the + speedbin that is used to select the right frequency/voltage + value pair. + Please refer the for nvmem-cells + bindings Documentation/devicetree/bindings/nvmem/nvmem.txt + and also examples below. + +In every OPP node: +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW. + Bitmap: + 0: MSM8996 V3, speedbin 0 + 1: MSM8996 V3, speedbin 1 + 2: MSM8996 V3, speedbin 2 + 3: unused + 4: MSM8996 SG, speedbin 0 + 5: MSM8996 SG, speedbin 1 + 6: MSM8996 SG, speedbin 2 + 7-31: unused + +Example 1: +--------- + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu at 0 {
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt line 60
Quoted 10 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +10
-0+ device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; + operating-points-v2 = <&cluster0_opp>; + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <15>;
cooling min/max aren't required anymore, as I told you in the previous version :)
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt line 147
Quoted 7 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +7
-0+ cluster0_opp: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 < 307200000 >;
You fixed spacing around frequency values in the dts but not here.
Quoted 4 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +4
-0+ opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + };
Signature · 1 line
viresh
RE: [PATCH v5 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
bbbb
Quoted 107 lines
-----Original Message-----
From: Viresh Kumar <[email protected]>
Sent: Friday, May 4, 2018 09:11
To: Ilia Lin <[email protected]>
Cc: mturquette at baylibre.com; sboyd at kernel.org; robh at kernel.org; mark.rutland at arm.com; rjw at rjwysocki.net; lgirdwood at gmail.com; broonie at kernel.org; andy.gross at linaro.org; david.brown at linaro.org; catalin.marinas at arm.com; will.deacon at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux- pm at vger.kernel.org; linux-arm-msm at vger.kernel.org; linux-
soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org; rnayak at codeaurora.org; amit.kucheria at linaro.org; nicolas.dechesne at linaro.org; celster at codeaurora.org;
tfinkel at codeaurora.org
Subject: Re: [PATCH v5 13/14] dt-bindings: cpufreq: Document operating- points-v2-kryo-cpuQuoted 12 lines · Ilia Lin
In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 that have KRYO processors, the CPU ferequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination.
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information. This is used to determine the voltage and frequency value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.Quoted 5 lines
This change adds documentation.
Signed-off-by Ilia Lin <[email protected]>--- .../devicetree/bindings/opp/kryo-cpufreq.txt | 693+++++++++++++++++++++
Quoted 12 lines
1 file changed, 693 insertions(+) create mode 100644
Documentation/devicetree/bindings/opp/kryo-cpufreq.txtDocumentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +1
-0@@ -0,0 +1,693 @@ +Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindingsDocumentation/devicetree/bindings/opp/kryo-cpufreq.txt line 11
Quoted 10 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +10
-0+=================================== + +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 +that have KRYO processors, the CPU ferequencies subset and voltage +value of each OPP varies based on the silicon variant in use. +Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines +the voltage and frequency value based on the msm-id in SMEM and +speedbin blown in the efuse combination. +The qcom-cpufreq-kryo driver reads the msm-id and efuse value from +the SoC to provide the OPP framework with required information(existing HW bitmap).
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
Quoted 13 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +13
-0+This is used to determine the voltage and frequency value for each +OPP of +operating-points-v2 table when it is parsed by the OPP framework. + +Required properties: +-------------------- +In 'cpus' nodes: +- operating-points-v2: Phandle to the operating-points-v2 table to use. + +In 'operating-points-v2' table: +- compatible: Should be + - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. +- nvmem-cells: A phandle pointing to a nvmem-cells node representingthe
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
Quoted 5 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +5
-0+ efuse registers that has information about the + speedbin that is used to select the right frequency/voltage + value pair. + Please refer the for nvmem-cells + bindings
Documentation/devicetree/bindings/nvmem/nvmem.txtDocumentation/devicetree/bindings/opp/kryo-cpufreq.txt
Quoted 4 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +4
-0+ and also examples below. + +In every OPP node: +- opp-supported-hw: A single 32 bit bitmap value, representingcompatible HW.
Quoted 23 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +23
-0+ Bitmap: + 0: MSM8996 V3, speedbin 0 + 1: MSM8996 V3, speedbin 1 + 2: MSM8996 V3, speedbin 2 + 3: unused + 4: MSM8996 SG, speedbin 0 + 5: MSM8996 SG, speedbin 1 + 6: MSM8996 SG, speedbin 2 + 7-31: unused + +Example 1: +--------- + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&kryocc 0>;
Quoted 8 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt line 60
Quoted 5 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +5
-0+ cpu-supply = <&pm8994_s11_saw>; + operating-points-v2 = <&cluster0_opp>; + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <15>;cooling min/max aren't required anymore, as I told you in the previous version :)
Sure, I removed them in the DT, but forgot in the documentation. Will fix.
Quoted 10 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt line 147
Quoted 8 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +7
-0+ cluster0_opp: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 < 307200000 >;You fixed spacing around frequency values in the dts but not here.
Same as above.
Quoted 8 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt line 151
Quoted 5 lines
Documentation/devicetree/bindings/opp/kryo-cpufreq.txt new file +4
-0+ opp-microvolt = <905000 905000 1140000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + };--
viresh
PATCH v5 14/14 dt: qcom: Add qcom-cpufreq-kryo driver configuration
In reply to Ilia Lin--- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 310 +++++++++++++++++++++++++++- 2 files changed, 309 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/qcom/apq8096-db820c.dts +1 -1
@@ -17,5 +17,5 @@ / { model = "Qualcomm Technologies, Inc. DB820c"; - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc"; + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; };
arch/arm64/boot/dts/qcom/msm8996.dtsi +308 -2
532 lines not on this page · raw message
Signature · 1 line
1.9.1
Viresh Kumar
maintainerQuoted 8 lines · Ilia Lin
[v5]
* Rebased
* Adressed comments from Bjorn
* Adressed comments from Viresh
* Adressed comments from Sricharan
* Adressed comments from Nicolas
* Adressed comments from Rob
* Adressed comments from Mark
s/Adressed/Addressed/
And that's not how the history should be present here. I don't have any clue on what I commented on in the previous versions. Now that there is no clear history available, I need to go look at my previous replies to understand that. That's not right.
You should mention the exact changes here and you can include the name of the reviewer in parenthesis. Like this:
* Replaced kmalloc with kzalloc (Viresh).
Signature · 1 line
viresh