Refactor DPU device/driver hierarchy and add runtime_pm support

MDSS top level device includes the common power resources and it's corresponding driver (i.e. mdp5_mdss) handles call to enable/disable runtime_pm for enabling these resources. Remove redundant pm_runtime_enable call from msm_drv.

Signed-off-by Rajesh Yadav <[email protected]>

---
 drivers/gpu/drm/msm/msm_drv.c | 1 -
 1 file changed, 1 deletion(-)

drivers/gpu/drm/msm/msm_drv.c +0 -1

index ebc40a9..9bb436f 100644
@@ -581,7 +581,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
 		goto fail;
 	}
 	priv->kms = kms;
-	pm_runtime_enable(dev);
 
 	/**
 	 * Since kms->funcs->hw_init(kms) might call

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

SoCs having mdp5 or dpu have identical tree like device hierarchy where MDSS top level wrapper manages common power resources for all child devices.

Subclass msm_mdss so that msm_mdss includes common defines and mdp5/dpu mdss derivations to include any extensions.

Add mdss helper interface (msm_mdss_funcs) to msm_mdss base for mdp5/dpu mdss specific implementation calls.

This change subclasses msm_mdss for mdp5, dpu specific changes will be done separately.

Signed-off-by Rajesh Yadav <[email protected]>

SoCs containing dpu have a MDSS top level wrapper which includes sub-blocks as dpu, dsi, phy, dp etc. MDSS top level wrapper manages common resources like common clocks, power and irq for its sub-blocks.

Currently, in dpu driver, all the power resource management is part of power_handle which manages these resources via a custom implementation. And the resource relationships are not modelled properly in dt. Moreover the irq domain handling code is part of dpu device (which is a child device) due to lack of a dedicated driver for MDSS top level wrapper device.

This change adds dpu_mdss top level driver to handle common clock like - core clock, ahb clock (for register access), main power supply (i.e. gdsc) and irq management.
The top level mdss device/driver acts as an interrupt controller and manage hwirq mapping for its child devices.

It implements runtime_pm support for resource management. Child nodes can control these resources via runtime_pm get/put calls on their corresponding devices due to parent child relationship defined in dt.

Signed-off-by Rajesh Yadav <[email protected]>

---
 drivers/gpu/drm/msm/Makefile                      |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c      |  97 -------
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h      |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    |   9 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |  29 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  11 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c           |  48 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c           |   6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h           |   2 -

 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c          | 301 ++++++++++++++++++++++
 drivers/gpu/drm/msm/dpu_io_util.c                 |  55 ++++
 drivers/gpu/drm/msm/msm_drv.c                     |  26 +-
 drivers/gpu/drm/msm/msm_drv.h                     |   2 +-
 drivers/gpu/drm/msm/msm_kms.h                     |   2 +
 include/linux/dpu_io_util.h                       |   2 +
 16 files changed, 390 insertions(+), 222 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +14 -0

new file mode 100644
index 0000000..26bf2c1
@@ -0,0 +1,301 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (c) 2018, The Linux Foundation
+ */
+
+#include "dpu_kms.h"
+
+#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
+
+#define HW_INTR_STATUS			0x0010
+
+struct dpu_mdss {
+	struct msm_mdss base;
+	void __iomem *mmio;

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +8 -0

+
+static irqreturn_t dpu_mdss_irq(int irq, void *arg)
+{
+	struct dpu_mdss *dpu_mdss = arg;
+	u32 interrupts;
+
+	if (!arg)
+		return IRQ_NONE;

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +7 -0

+		}
+
+		interrupts &= ~(1 << hwirq);
+	}
+
+	return IRQ_HANDLED;
+

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +7 -0

+		DPU_ERROR("invalid parameters irqd %d\n", irqd != NULL);
+		return;
+	}
+	dpu_mdss = irq_data_get_irq_chip_data(irqd);
+
+	/* memory barrier */
+	smp_mb__before_atomic();

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +15 -0

+		DPU_ERROR("invalid parameters irqd %d\n", irqd != NULL);
+		return;
+	}
+	dpu_mdss = irq_data_get_irq_chip_data(irqd);
+
+	/* memory barrier */
+	smp_mb__before_atomic();
+	set_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
+	/* memory barrier */
+	smp_mb__after_atomic();
+}
+
+static struct irq_chip dpu_mdss_irq_chip = {
+	.name = "dpu_mdss",
+	.irq_mask = dpu_mdss_irq_mask,

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +43 -0

+		DPU_ERROR("invalid parameters domain %d\n", domain != NULL);
+		return -EINVAL;
+	}
+	dpu_mdss = domain->host_data;
+
+	irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
+	ret = irq_set_chip_data(irq, dpu_mdss);
+
+	return ret;
+}
+
+static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
+	.map = dpu_mdss_irqdomain_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss)
+{
+	struct device *dev;
+	struct irq_domain *domain;
+
+	dev = dpu_mdss->base.dev->dev;
+
+	domain = irq_domain_add_linear(dev->of_node, 32,
+			&dpu_mdss_irqdomain_ops, dpu_mdss);
+	if (!domain) {
+		DPU_ERROR("failed to add irq_domain\n");
+		return -EINVAL;
+	}
+
+	dpu_mdss->irq_controller.enabled_mask = 0;
+	dpu_mdss->irq_controller.domain = domain;
+
+	return 0;
+}
+
+int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
+{
+	if (dpu_mdss->irq_controller.domain) {
+		irq_domain_remove(dpu_mdss->irq_controller.domain);
+		dpu_mdss->irq_controller.domain = NULL;
+	}
+	return 0;

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +22 -0

+		return;
+
+	_dpu_mdss_irq_domain_fini(dpu_mdss);
+
+	msm_dss_put_clk(mp->clk_config, mp->num_clk);
+	devm_kfree(&pdev->dev, mp->clk_config);
+
+	if (dpu_mdss->mmio)
+		msm_iounmap(pdev, dpu_mdss->mmio);
+	dpu_mdss->mmio = NULL;
+
+	pm_runtime_disable(dev->dev);
+
+	devm_kfree(dev->dev, dpu_mdss);
+	priv->mdss = NULL;
+}
+
+static const struct msm_mdss_funcs mdss_funcs = {
+	.enable	= dpu_mdss_enable,
+	.disable = dpu_mdss_disable,
+	.destroy = dpu_mdss_destroy,
+};

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +62 -0

+		return 0;
+
+	dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
+	if (!dpu_mdss)
+		return -ENOMEM;
+
+	dpu_mdss->mmio = msm_ioremap(pdev, "mdss_phys", "mdss_phys");
+	if (IS_ERR(dpu_mdss->mmio)) {
+		ret = PTR_ERR(dpu_mdss->mmio);
+		DPU_ERROR("mdss register memory map failed: %d\n", ret);
+		dpu_mdss->mmio = NULL;
+		goto error;
+	}
+	DRM_INFO("mapped mdss address space @%p\n", dpu_mdss->mmio);
+	dpu_mdss->mmio_len = msm_iomap_size(pdev, "mdss_phys");
+
+	mp = &dpu_mdss->mp;
+	ret = msm_dss_parse_clock(pdev, mp);
+	if (ret) {
+		DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
+		goto clk_parse_err;
+	}
+
+	ret = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
+	if (ret) {
+		DPU_ERROR("failed to get clocks, ret=%d\n", ret);
+		goto clk_get_error;
+	}
+
+	ret = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
+	if (ret) {
+		DPU_ERROR("failed to set clock rate, ret=%d\n", ret);
+		goto clk_rate_error;
+	}
+
+	dpu_mdss->base.dev = dev;
+	dpu_mdss->base.funcs = &mdss_funcs;
+
+	ret = _dpu_mdss_irq_domain_add(dpu_mdss);
+	if (ret)
+		goto irq_domain_error;
+
+	ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),
+			dpu_mdss_irq, 0, "dpu_mdss_isr", dpu_mdss);
+	if (ret) {
+		DPU_ERROR("failed to init irq: %d\n", ret);
+		goto irq_error;
+	}
+
+	pm_runtime_enable(dev->dev);
+
+	pm_runtime_get_sync(dev->dev);
+	_dpu_mdss_hw_rev_init(dpu_mdss);
+	pm_runtime_put_sync(dev->dev);
+
+	priv->mdss = &dpu_mdss->base;
+
+	return ret;
+
+irq_error:
+	_dpu_mdss_irq_domain_fini(dpu_mdss);
+irq_domain_error:

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +2 -0

+	return ret;
+}

drivers/gpu/drm/msm/dpu_io_util.c +8 -0

index a18bc99..efa06a8 100644
@@ -448,6 +448,61 @@ int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable)
 } /* msm_dss_enable_clk */
 EXPORT_SYMBOL(msm_dss_enable_clk);
 
+int msm_dss_parse_clock(struct platform_device *pdev,
+		struct dss_module_power *mp)
+{
+	u32 i = 0, rc = 0;
+	const char *clock_name;
+	u32 clock_rate = 0;
+	u32 clock_max_rate = 0;
+	int num_clk = 0;

drivers/gpu/drm/msm/dpu_io_util.c +2 -0

+}
+EXPORT_SYMBOL(msm_dss_parse_clock);
 
 int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
 			uint8_t reg_offset, uint8_t *read_buf)

drivers/gpu/drm/msm/msm_drv.c +12 -3

index 5d8f1b6..a0e73ea 100644
@@ -503,7 +503,18 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
 	ddev->dev_private = priv;
 	priv->dev = ddev;
 
-	ret = mdp5_mdss_init(ddev);
+	switch (get_mdp_ver(pdev)) {
+	case KMS_MDP5:
+		ret = mdp5_mdss_init(ddev);
+		break;
+	case KMS_DPU:
+		ret = dpu_mdss_init(ddev);
+		break;
+	default:
+		ret = 0;
+		break;
+	}
+
 	if (ret)
 		goto mdss_init_fail;
 

@@ -1539,12 +1550,13 @@ static int add_display_components(struct device *dev,
 	int ret;
 
 	/*
-	 * MDP5 based devices don't have a flat hierarchy. There is a top level
-	 * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the

drivers/gpu/drm/msm/msm_drv.c +0 -0

 #endif
 	{}
 };

drivers/gpu/drm/msm/msm_drv.h +1 -1

index 90a2521..e8e5e73 100644
@@ -381,7 +381,7 @@ struct msm_drm_private {
 	/* subordinate devices, if present: */
 	struct platform_device *gpu_pdev;
 
-	/* top level MDSS wrapper device (for MDP5 only) */
+	/* top level MDSS wrapper device (for MDP5/DPU only) */
 	struct msm_mdss *mdss;
 
 	/* possibly this should be in the kms component, but it is

drivers/gpu/drm/msm/msm_kms.h +0 -0

index 9a7bc7d..8f50613 100644

drivers/gpu/drm/msm/msm_kms.h +2 -0

+int dpu_mdss_init(struct drm_device *dev);
+
 /**
  * Mode Set Utility Functions
  */

include/linux/dpu_io_util.h +2 -0

index 7c73899..45e606f 100644
@@ -104,6 +104,8 @@ int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg,
 void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
 int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
+int msm_dss_parse_clock(struct platform_device *pdev,
+		struct dss_module_power *mp);
 
 int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
 		       uint8_t reg_offset, uint8_t *read_buf);

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

SoCs containing dpu have a MDSS top level wrapper which includes sub-blocks as dpu, dsi, phy, dp etc. MDSS top level wrapper manages common resources like common clocks, power and irq for its sub-blocks.

Currently, in dpu driver, all the power resource management is part of power_handle which manages these resources via a custom implementation. And the resource relationships are not modelled properly in dt. Moreover the irq domain handling code is part of dpu device (which is a child device) due to lack of a dedicated driver for MDSS top level wrapper device.

This change adds dpu_mdss top level driver to handle common clock like - core clock, ahb clock (for register access), main power supply (i.e. gdsc) and irq management.
The top level mdss device/driver acts as an interrupt controller and manage hwirq mapping for its child devices.

It implements runtime_pm support for resource management. Child nodes can control these resources via runtime_pm get/put calls on their corresponding devices due to parent child relationship defined in dt.

Signed-off-by Rajesh Yadav <[email protected]>

---
 drivers/gpu/drm/msm/Makefile                      |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c      |  97 -------
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h      |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    |   9 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |  29 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  11 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c           |  48 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c           |   6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h           |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c          | 301 ++++++++++++++++++++++
 drivers/gpu/drm/msm/dpu_io_util.c                 |  55 ++++
 drivers/gpu/drm/msm/msm_drv.c                     |  26 +-
 drivers/gpu/drm/msm/msm_drv.h                     |   2 +-
 drivers/gpu/drm/msm/msm_kms.h                     |   2 +
 include/linux/dpu_io_util.h                       |   2 +
 16 files changed, 390 insertions(+), 222 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +3 -3

 	hw->base_off = addr;
-	hw->blk_off = m->mdss[0].base;
+	hw->blk_off = m->mdp[0].base;
 	hw->hwversion = m->hwversion;
-	return &m->mdss[0];
+	return 0;
 }
 
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 		struct dpu_mdss_cfg *m)
 {
 	struct dpu_hw_intr *intr;
-	struct dpu_mdss_base_cfg *cfg;
+	int ret;
 
 	if (!addr || !m)
 		return ERR_PTR(-EINVAL);

@@ -1195,10 +1182,10 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 	if (!intr)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +0 -0

 	__setup_intr_ops(&intr->ops);
 

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +21 -0

new file mode 100644
index 0000000..26bf2c1
@@ -0,0 +1,301 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (c) 2018, The Linux Foundation
+ */
+
+#include "dpu_kms.h"
+
+#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
+
+#define HW_INTR_STATUS			0x0010
+
+struct dpu_mdss {
+	struct msm_mdss base;
+	void __iomem *mmio;
+	unsigned long mmio_len;
+	u32 hwversion;
+	struct dss_module_power mp;
+	struct dpu_irq_controller irq_controller;
+};
+
+static inline void _dpu_mdss_hw_rev_init(struct dpu_mdss *dpu_mdss)

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +26 -0

+	while (interrupts) {
+		irq_hw_number_t hwirq = fls(interrupts) - 1;
+		unsigned int mapping;
+		int rc;
+
+		mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
+				hwirq);
+		if (mapping == 0) {
+			DPU_EVT32(hwirq, DPU_EVTLOG_ERROR);
+			goto error;
+		}
+
+		rc = generic_handle_irq(mapping);
+		if (rc < 0) {
+			DPU_EVT32(hwirq, mapping, rc, DPU_EVTLOG_ERROR);
+			goto error;
+		}
+
+		interrupts &= ~(1 << hwirq);
+	}
+
+	return IRQ_HANDLED;
+
+error:
+	/* bad situation, inform irq system, it may disable overall MDSS irq */
+	return IRQ_NONE;

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +7 -0

+	dpu_mdss = irq_data_get_irq_chip_data(irqd);
+
+	/* memory barrier */
+	smp_mb__before_atomic();
+	clear_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
+	/* memory barrier */
+	smp_mb__after_atomic();

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +15 -0

+	dpu_mdss = irq_data_get_irq_chip_data(irqd);
+
+	/* memory barrier */
+	smp_mb__before_atomic();
+	set_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
+	/* memory barrier */
+	smp_mb__after_atomic();
+}
+
+static struct irq_chip dpu_mdss_irq_chip = {
+	.name = "dpu_mdss",
+	.irq_mask = dpu_mdss_irq_mask,
+	.irq_unmask = dpu_mdss_irq_unmask,
+};
+

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +36 -0

+	dpu_mdss = domain->host_data;
+
+	irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
+	ret = irq_set_chip_data(irq, dpu_mdss);
+
+	return ret;
+}
+
+static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
+	.map = dpu_mdss_irqdomain_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss)
+{
+	struct device *dev;
+	struct irq_domain *domain;
+
+	dev = dpu_mdss->base.dev->dev;
+
+	domain = irq_domain_add_linear(dev->of_node, 32,
+			&dpu_mdss_irqdomain_ops, dpu_mdss);
+	if (!domain) {
+		DPU_ERROR("failed to add irq_domain\n");
+		return -EINVAL;
+	}
+
+	dpu_mdss->irq_controller.enabled_mask = 0;
+	dpu_mdss->irq_controller.domain = domain;
+
+	return 0;
+}
+
+int _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
+{
+	if (dpu_mdss->irq_controller.domain) {

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +27 -0

+
+	if (dpu_mdss->mmio)
+		msm_iounmap(pdev, dpu_mdss->mmio);
+	dpu_mdss->mmio = NULL;
+
+	pm_runtime_disable(dev->dev);
+
+	devm_kfree(dev->dev, dpu_mdss);
+	priv->mdss = NULL;
+}
+
+static const struct msm_mdss_funcs mdss_funcs = {
+	.enable	= dpu_mdss_enable,
+	.disable = dpu_mdss_disable,
+	.destroy = dpu_mdss_destroy,
+};
+
+int dpu_mdss_init(struct drm_device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev->dev);
+	struct msm_drm_private *priv = dev->dev_private;
+	struct dpu_mdss *dpu_mdss;
+	struct dss_module_power *mp;
+	int ret = 0;
+
+	if (!of_device_is_compatible(dev->dev->of_node, "qcom,dpu-mdss"))
+		return 0;

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c new file +60 -0

+	dpu_mdss->mmio_len = msm_iomap_size(pdev, "mdss_phys");
+
+	mp = &dpu_mdss->mp;
+	ret = msm_dss_parse_clock(pdev, mp);
+	if (ret) {
+		DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
+		goto clk_parse_err;
+	}
+
+	ret = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
+	if (ret) {
+		DPU_ERROR("failed to get clocks, ret=%d\n", ret);
+		goto clk_get_error;
+	}
+
+	ret = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
+	if (ret) {
+		DPU_ERROR("failed to set clock rate, ret=%d\n", ret);
+		goto clk_rate_error;
+	}
+
+	dpu_mdss->base.dev = dev;
+	dpu_mdss->base.funcs = &mdss_funcs;
+
+	ret = _dpu_mdss_irq_domain_add(dpu_mdss);
+	if (ret)
+		goto irq_domain_error;
+
+	ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),
+			dpu_mdss_irq, 0, "dpu_mdss_isr", dpu_mdss);
+	if (ret) {
+		DPU_ERROR("failed to init irq: %d\n", ret);
+		goto irq_error;
+	}
+
+	pm_runtime_enable(dev->dev);
+
+	pm_runtime_get_sync(dev->dev);
+	_dpu_mdss_hw_rev_init(dpu_mdss);
+	pm_runtime_put_sync(dev->dev);
+
+	priv->mdss = &dpu_mdss->base;
+
+	return ret;
+
+irq_error:
+	_dpu_mdss_irq_domain_fini(dpu_mdss);
+irq_domain_error:
+clk_rate_error:
+	msm_dss_put_clk(mp->clk_config, mp->num_clk);
+clk_get_error:
+	devm_kfree(&pdev->dev, mp->clk_config);
+clk_parse_err:
+	if (dpu_mdss->mmio)
+		msm_iounmap(pdev, dpu_mdss->mmio);
+	dpu_mdss->mmio = NULL;
+error:
+	devm_kfree(dev->dev, dpu_mdss);
+	return ret;
+}

drivers/gpu/drm/msm/dpu_io_util.c +1 -0

index a18bc99..efa06a8 100644
@@ -448,6 +448,61 @@ int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable)
 } /* msm_dss_enable_clk */
 EXPORT_SYMBOL(msm_dss_enable_clk);
 
+int msm_dss_parse_clock(struct platform_device *pdev,

drivers/gpu/drm/msm/dpu_io_util.c +26 -0

+	}
+
+	mp->num_clk = num_clk;
+	mp->clk_config = devm_kzalloc(&pdev->dev,
+			sizeof(struct dss_clk) * num_clk, GFP_KERNEL);
+	if (!mp->clk_config) {
+		rc = -ENOMEM;
+		mp->num_clk = 0;
+		goto clk_err;
+	}
+
+	for (i = 0; i < num_clk; i++) {
+		of_property_read_string_index(pdev->dev.of_node, "clock-names",
+							i, &clock_name);
+		strlcpy(mp->clk_config[i].clk_name, clock_name,
+				sizeof(mp->clk_config[i].clk_name));
+
+		of_property_read_u32_index(pdev->dev.of_node, "clock-rate",
+							i, &clock_rate);
+		mp->clk_config[i].rate = clock_rate;
+
+		if (!clock_rate)
+			mp->clk_config[i].type = DSS_CLK_AHB;
+		else
+			mp->clk_config[i].type = DSS_CLK_PCLK;
+

drivers/gpu/drm/msm/dpu_io_util.c +0 -0

 int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
 			uint8_t reg_offset, uint8_t *read_buf)

drivers/gpu/drm/msm/msm_drv.c +19 -7

index 5d8f1b6..a0e73ea 100644
@@ -503,7 +503,18 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
 	ddev->dev_private = priv;
 	priv->dev = ddev;
 
-	ret = mdp5_mdss_init(ddev);
+	switch (get_mdp_ver(pdev)) {
+	case KMS_MDP5:
+		ret = mdp5_mdss_init(ddev);
+		break;
+	case KMS_DPU:
+		ret = dpu_mdss_init(ddev);
+		break;
+	default:
+		ret = 0;
+		break;
+	}
+
 	if (ret)
 		goto mdss_init_fail;
 

@@ -1539,12 +1550,13 @@ static int add_display_components(struct device *dev,
 	int ret;
 
 	/*
-	 * MDP5 based devices don't have a flat hierarchy. There is a top level
-	 * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the
-	 * children devices, find the MDP5 node, and then add the interfaces
-	 * to our components list.
+	 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
+	 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
+	 * Populate the children devices, find the MDP5/DPU node, and then add
+	 * the interfaces to our components list.
 	 */
-	if (of_device_is_compatible(dev->of_node, "qcom,mdss")) {
+	if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
+		of_device_is_compatible(dev->of_node, "qcom,dpu-mdss")) {
 		ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
 		if (ret) {
 			dev_err(dev, "failed to populate children devices\n");

@@ -1686,7 +1698,7 @@ static int msm_pdev_remove(struct platform_device *pdev)
 	{ .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
 	{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
 #ifdef CONFIG_DRM_MSM_DPU
-	{ .compatible = "qcom,dpu-kms", .data = (void *)KMS_DPU },
+	{ .compatible = "qcom,dpu-mdss", .data = (void *)KMS_DPU },
 #endif
 	{}
 };

drivers/gpu/drm/msm/msm_drv.h +1 -1

index 90a2521..e8e5e73 100644
@@ -381,7 +381,7 @@ struct msm_drm_private {
 	/* subordinate devices, if present: */
 	struct platform_device *gpu_pdev;
 
-	/* top level MDSS wrapper device (for MDP5 only) */
+	/* top level MDSS wrapper device (for MDP5/DPU only) */
 	struct msm_mdss *mdss;
 
 	/* possibly this should be in the kms component, but it is

drivers/gpu/drm/msm/msm_kms.h +2 -0

index 9a7bc7d..8f50613 100644
@@ -145,6 +145,8 @@ struct msm_mdss {
 
 int mdp5_mdss_init(struct drm_device *dev);
 
+int dpu_mdss_init(struct drm_device *dev);
+
 /**
  * Mode Set Utility Functions
  */

include/linux/dpu_io_util.h +2 -0

index 7c73899..45e606f 100644
@@ -104,6 +104,8 @@ int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg,
 void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
 int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
+int msm_dss_parse_clock(struct platform_device *pdev,
+		struct dss_module_power *mp);
 
 int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
 		       uint8_t reg_offset, uint8_t *read_buf);

The dpu sub-block offsets were defined wrt mdss base address instead of dpu base address.
Since, dpu is now defined as a separate device, update hw catalog offsets for all dpu sub blocks wrt dpu base address.

Signed-off-by Rajesh Yadav <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 68 +++++++++++------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 +++---
 2 files changed, 43 insertions(+), 43 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +34 -34

index c5b370f..2fd3254 100644
@@ -80,7 +80,7 @@
 static struct dpu_mdp_cfg sdm845_mdp[] = {
 	{
 	.name = "top_0", .id = MDP_TOP,
-	.base = 0x1000, .len = 0x45C,
+	.base = 0x0, .len = 0x45C,
 	.features = 0,
 	.highest_bank_bit = 0x2,
 	.has_dest_scaler = true,

@@ -111,27 +111,27 @@
 static struct dpu_ctl_cfg sdm845_ctl[] = {
 	{
 	.name = "ctl_0", .id = CTL_0,
-	.base = 0x2000, .len = 0xE4,
+	.base = 0x1000, .len = 0xE4,
 	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
-	.base = 0x2200, .len = 0xE4,
+	.base = 0x1200, .len = 0xE4,
 	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
-	.base = 0x2400, .len = 0xE4,
+	.base = 0x1400, .len = 0xE4,
 	.features = 0
 	},
 	{
 	.name = "ctl_3", .id = CTL_3,
-	.base = 0x2600, .len = 0xE4,
+	.base = 0x1600, .len = 0xE4,
 	.features = 0
 	},
 	{
 	.name = "ctl_4", .id = CTL_4,
-	.base = 0x2800, .len = 0xE4,
+	.base = 0x1800, .len = 0xE4,
 	.features = 0
 	},
 };

@@ -211,21 +211,21 @@
 	}
 
 static struct dpu_sspp_cfg sdm845_sspp[] = {
-	SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x5000,
+	SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
 		sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
-	SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x7000,
+	SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
 		sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
-	SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x9000,
+	SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
 		sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
-	SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xb000,
+	SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
 		sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
-	SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x25000,
+	SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
 		sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
-	SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x27000,
+	SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
 		sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
-	SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x29000,
+	SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
 		sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
-	SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2b000,
+	SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
 		sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
 };
 

@@ -252,17 +252,17 @@
 	.lm_pair_mask = (1 << _lmpair) \
 	}
 static struct dpu_lm_cfg sdm845_lm[] = {
-	LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
+	LM_BLK("lm_0", LM_0, 0x44000, DSPP_0,
 		DS_0, PINGPONG_0, LM_1),
-	LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
+	LM_BLK("lm_1", LM_1, 0x45000, DSPP_1,
 		DS_1, PINGPONG_1, LM_0),
-	LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
+	LM_BLK("lm_2", LM_2, 0x46000, DSPP_2,
 		DS_MAX, PINGPONG_2, LM_5),
 	LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
 		DS_MAX, PINGPONG_MAX, 0),
 	LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
 		DS_MAX, PINGPONG_MAX, 0),
-	LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
+	LM_BLK("lm_5", LM_5, 0x49000, DSPP_3,
 		DS_MAX, PINGPONG_3, LM_2),
 };
 

@@ -270,7 +270,7 @@
  * DSPP sub blocks config
  *************************************************************/
 static struct dpu_dspp_top_cfg sdm845_dspp_top = {
-	.name = "dspp_top", .base = 0x1300, .len = 0xc
+	.name = "dspp_top", .base = 0x300, .len = 0xc
 };
 
 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {

@@ -304,10 +304,10 @@
 	}
 
 static struct dpu_dspp_cfg sdm845_dspp[] = {
-	DSPP_BLK("dspp_0", DSPP_0, 0x55000),
-	DSPP_BLK("dspp_1", DSPP_1, 0x57000),
-	DSPP_BLK("dspp_2", DSPP_2, 0x59000),
-	DSPP_BLK("dspp_3", DSPP_3, 0x5b000),
+	DSPP_BLK("dspp_0", DSPP_0, 0x54000),
+	DSPP_BLK("dspp_1", DSPP_1, 0x56000),
+	DSPP_BLK("dspp_2", DSPP_2, 0x58000),
+	DSPP_BLK("dspp_3", DSPP_3, 0x5a000),
 };
 
 /*************************************************************

@@ -315,7 +315,7 @@
  *************************************************************/
 static const struct dpu_ds_top_cfg sdm845_ds_top = {
 	.name = "ds_top_0", .id = DS_TOP,
-	.base = 0x61000, .len = 0xc,
+	.base = 0x60000, .len = 0xc,
 	.maxinputwidth = DEFAULT_DPU_LINE_WIDTH,
 	.maxoutputwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 	.maxupscale = MAX_UPSCALE_RATIO,

@@ -365,10 +365,10 @@
 	}
 
 static struct dpu_pingpong_cfg sdm845_pp[] = {
-	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x71000),
-	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x71800),
-	PP_BLK("pingpong_2", PINGPONG_2, 0x72000),
-	PP_BLK("pingpong_3", PINGPONG_3, 0x72800),
+	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000),
+	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
+	PP_BLK("pingpong_2", PINGPONG_2, 0x71000),
+	PP_BLK("pingpong_3", PINGPONG_3, 0x71800),
 };
 
 /*************************************************************

@@ -384,10 +384,10 @@
 	}
 
 static struct dpu_intf_cfg sdm845_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x6B000, INTF_DP, 0),
-	INTF_BLK("intf_1", INTF_1, 0x6B800, INTF_DSI, 0),
-	INTF_BLK("intf_2", INTF_2, 0x6C000, INTF_DSI, 1),
-	INTF_BLK("intf_3", INTF_3, 0x6C800, INTF_DP, 1),
+	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0),
+	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0),
+	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1),
+	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1),
 };
 
 /*************************************************************

@@ -401,7 +401,7 @@
 static struct dpu_wb_cfg sdm845_wb[] = {
 	{
 	.name = "wb_2", .id = WB_2,
-	.base = 0x66000, .len = 0x2c8,
+	.base = 0x65000, .len = 0x2c8,
 	.features = WB2_SDM845_MASK,
 	.sblk = &sdm845_wb2_sblk,
 	.format_list = wb2_formats,

@@ -414,7 +414,7 @@
 static struct dpu_cdm_cfg sdm845_cdm[] = {
 	{
 	.name = "cdm_0", .id = CDM_0,
-	.base = 0x7A200, .len = 0x224,
+	.base = 0x79200, .len = 0x224,
 	.features = 0,
 	.intf_connect = BIT(INTF_3),
 	.wb_connect = BIT(WB_2)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +9 -9

index 7093ba4..2de13e3 100644
@@ -20,16 +20,16 @@
 
 /**
  * Register offsets in MDSS register file for the interrupt registers
- * w.r.t. to the MDSS base
+ * w.r.t. to the MDP base
  */
-#define MDP_SSPP_TOP0_OFF		0x1000
-#define MDP_INTF_0_OFF			0x6B000
-#define MDP_INTF_1_OFF			0x6B800
-#define MDP_INTF_2_OFF			0x6C000
-#define MDP_INTF_3_OFF			0x6C800
-#define MDP_INTF_4_OFF			0x6D000
-#define MDP_AD4_0_OFF			0x7D000
-#define MDP_AD4_1_OFF			0x7E000
+#define MDP_SSPP_TOP0_OFF		0x0
+#define MDP_INTF_0_OFF			0x6A000
+#define MDP_INTF_1_OFF			0x6A800
+#define MDP_INTF_2_OFF			0x6B000
+#define MDP_INTF_3_OFF			0x6B800
+#define MDP_INTF_4_OFF			0x6C000
+#define MDP_AD4_0_OFF			0x7C000
+#define MDP_AD4_1_OFF			0x7D000
 #define MDP_AD4_INTR_EN_OFF		0x41c
 #define MDP_AD4_INTR_CLEAR_OFF		0x424
 #define MDP_AD4_INTR_STATUS_OFF		0x420

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

The dpu driver implements runtime_pm support for managing dpu specific resources like - clocks, bus bandwidth etc.

Use pm_runtime_get/put_sync calls on dpu device.

The common clocks and power management for all child nodes (mdp5/dpu, dsi, dp etc) is done by parent MDSS device/driver via runtime_pm due to parent child relationship.

Signed-off-by Rajesh Yadav <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c |  8 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c     | 12 ++++----
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  | 16 +++++-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c      | 45 +++++++---------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c    |  6 ++--
 5 files changed, 31 insertions(+), 56 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +4 -4

index 977adc4..5c5cc56 100644
@@ -452,10 +452,10 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
 	}
 	priv = dpu_kms->dev->dev_private;
 
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, true);
+	pm_runtime_get_sync(&dpu_kms->pdev->dev);
 	dpu_clear_all_irqs(dpu_kms);
 	dpu_disable_all_irqs(dpu_kms);
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false);
+	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 
 	spin_lock_init(&dpu_kms->irq_obj.cb_lock);
 

@@ -496,7 +496,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
 	}
 	priv = dpu_kms->dev->dev_private;
 
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, true);
+	pm_runtime_get_sync(&dpu_kms->pdev->dev);
 	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
 		if (atomic_read(&dpu_kms->irq_obj.enable_counts[i]) ||
 				!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))

@@ -504,7 +504,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
 
 	dpu_clear_all_irqs(dpu_kms);
 	dpu_disable_all_irqs(dpu_kms);
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false);
+	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 
 	kfree(dpu_kms->irq_obj.irq_cb_tbl);
 	kfree(dpu_kms->irq_obj.enable_counts);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +6 -6

index 48920b05..e2d2e32 100644
@@ -86,8 +86,12 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc *dpu_crtc, bool enable)
 
 	dpu_kms = to_dpu_kms(priv->kms);
 
-	return dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client,
-									enable);
+	if (enable)
+		pm_runtime_get_sync(&dpu_kms->pdev->dev);
+	else
+		pm_runtime_put_sync(&dpu_kms->pdev->dev);
+
+	return 0;
 }
 
 /**

@@ -2250,7 +2254,6 @@ static int _dpu_crtc_vblank_enable_no_lock(
 
 		/* drop lock since power crtc cb may try to re-acquire lock */
 		mutex_unlock(&dpu_crtc->crtc_lock);
-		pm_runtime_get_sync(dev->dev);
 		ret = _dpu_crtc_power_enable(dpu_crtc, true);
 		mutex_lock(&dpu_crtc->crtc_lock);
 		if (ret)

@@ -2580,7 +2583,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 	/* disable clk & bw control until clk & bw properties are set */
 	cstate->bw_control = false;
 	cstate->bw_split_vote = false;
-	pm_runtime_put_sync(crtc->dev->dev);
 
 	mutex_unlock(&dpu_crtc->crtc_lock);
 }

@@ -2611,8 +2613,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
 		return;
 	}
 
-	pm_runtime_get_sync(crtc->dev->dev);
-
 	drm_for_each_encoder(encoder, crtc->dev) {
 		if (encoder->crtc != crtc)
 			continue;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +8 -8

index 4386360..298a6ef 100644
@@ -268,8 +268,12 @@ static inline int _dpu_encoder_power_enable(struct dpu_encoder_virt *dpu_enc,
 
 	dpu_kms = to_dpu_kms(priv->kms);
 
-	return dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client,
-									enable);
+	if (enable)
+		pm_runtime_get_sync(&dpu_kms->pdev->dev);
+	else
+		pm_runtime_put_sync(&dpu_kms->pdev->dev);
+
+	return 0;
 }
 
 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,

@@ -796,10 +800,8 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 	}
 
 	if (enable) {
-		pm_runtime_get_sync(dpu_kms->dev->dev);
 		/* enable DPU core clks */
-		dpu_power_resource_enable(&priv->phandle,
-				dpu_kms->core_client, true);
+		pm_runtime_get_sync(&dpu_kms->pdev->dev);
 
 		/* enable all the irq */
 		_dpu_encoder_irq_control(drm_enc, true);

@@ -809,9 +811,7 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 		_dpu_encoder_irq_control(drm_enc, false);
 
 		/* disable DPU core clks */
-		dpu_power_resource_enable(&priv->phandle,
-				dpu_kms->core_client, false);
-		pm_runtime_put_sync(dpu_kms->dev->dev);
+		pm_runtime_put_sync(&dpu_kms->pdev->dev);
 	}
 
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +11 -34

index 2cd51fc..6dd0d8e 100644
@@ -100,8 +100,7 @@ static int _dpu_danger_signal_status(struct seq_file *s,
 	priv = kms->dev->dev_private;
 	memset(&status, 0, sizeof(struct dpu_danger_safe_status));
 
-	pm_runtime_get_sync(kms->dev->dev);
-	dpu_power_resource_enable(&priv->phandle, kms->core_client, true);
+	pm_runtime_get_sync(&kms->pdev->dev);
 	if (danger_status) {
 		seq_puts(s, "\nDanger signal status:\n");
 		if (kms->hw_mdp->ops.get_danger_status)

@@ -113,8 +112,7 @@ static int _dpu_danger_signal_status(struct seq_file *s,
 			kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
 					&status);
 	}
-	dpu_power_resource_enable(&priv->phandle, kms->core_client, false);
-	pm_runtime_put_sync(kms->dev->dev);
+	pm_runtime_put_sync(&kms->pdev->dev);
 
 	seq_printf(s, "MDP     :  0x%x\n", status.mdp);
 

@@ -215,11 +213,7 @@ static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
 			seq_puts(s, "         ");
 	}
 
-	if (dpu_power_resource_enable(&priv->phandle,
-				dpu_kms->core_client, true)) {
-		seq_puts(s, "failed to enable dpu clocks\n");
-		return 0;
-	}
+	pm_runtime_get_sync(&dpu_kms->pdev->dev);
 
 	/* main register output */
 	for (i = 0; i < regset->blk_len; i += 4) {

@@ -229,7 +223,7 @@ static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
 		seq_printf(s, " %08x", readl_relaxed(base + i));
 	}
 	seq_puts(s, "\n");
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false);
+	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 
 	return 0;
 }

@@ -334,20 +328,12 @@ static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms)
 
 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 {
-	int ret;
-
-	pm_runtime_get_sync(crtc->dev->dev);
-	ret = dpu_crtc_vblank(crtc, true);
-	pm_runtime_put_sync(crtc->dev->dev);
-
-	return ret;
+	return dpu_crtc_vblank(crtc, true);
 }
 
 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 {
-	pm_runtime_get_sync(crtc->dev->dev);
 	dpu_crtc_vblank(crtc, false);
-	pm_runtime_put_sync(crtc->dev->dev);
 }
 
 static void dpu_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,

@@ -409,8 +395,7 @@ static void dpu_kms_prepare_commit(struct msm_kms *kms,
 	if (!dev || !dev->dev_private)
 		return;
 	priv = dev->dev_private;
-	pm_runtime_get_sync(dev->dev);
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, true);
+	pm_runtime_get_sync(&dpu_kms->pdev->dev);
 
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
 		if (encoder->crtc != NULL)

@@ -474,8 +459,7 @@ static void dpu_kms_complete_commit(struct msm_kms *kms,
 	for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
 		dpu_crtc_complete_commit(crtc, old_crtc_state);
 
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false);
-	pm_runtime_put_sync(dpu_kms->dev->dev);
+	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 
 	DPU_EVT32_VERBOSE(DPU_EVTLOG_FUNC_EXIT);
 }

@@ -1627,13 +1611,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 		dpu_kms->core_client = NULL;
 		goto error;
 	}
-	pm_runtime_get_sync(dev->dev);
-	rc = dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client,
-		true);
-	if (rc) {
-		DPU_ERROR("resource enable failed: %d\n", rc);
-		goto error;
-	}
+
+	pm_runtime_get_sync(&dpu_kms->pdev->dev);
 
 	_dpu_kms_core_hw_rev_init(dpu_kms);
 

@@ -1768,8 +1747,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 			DPU_POWER_EVENT_POST_ENABLE,
 			dpu_kms_handle_power_event, dpu_kms, "kms");
 
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false);
-	pm_runtime_put_sync(dev->dev);
+	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 
 	return 0;
 

@@ -1778,8 +1756,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 hw_intr_init_err:
 perf_err:
 power_error:
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false);
-	pm_runtime_put_sync(dev->dev);
+	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 error:
 	_dpu_kms_hw_destroy(dpu_kms);
 end:

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +2 -4

index ba5230d..cf6c3fd 100644
@@ -476,11 +476,9 @@ int dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
 	if (!pdpu->is_rt_pipe)
 		goto end;
 
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, true);
-
+	pm_runtime_get_sync(&dpu_kms->pdev->dev);
 	_dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
-
-	dpu_power_resource_enable(&priv->phandle, dpu_kms->core_client, false);
+	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 
 end:
 	return 0;

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

MDSS and dpu drivers manage their respective clocks via runtime_pm. Remove custom clock management code from dpu_power_handle.

Also dpu core clock management code is restricted to dpu_core_perf module.

Signed-off-by Rajesh Yadav <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c      |  44 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h      |   8 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |  32 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h            |   9 +
 drivers/gpu/drm/msm/dpu_power_handle.c             | 195 +--------------------
 drivers/gpu/drm/msm/dpu_power_handle.h             |  40 -----
 7 files changed, 69 insertions(+), 264 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +0 -0

index 981f77f..d1364fa 100644