IOMMU and VT-d driver support for Shared Virtual Address (SVA)

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest:
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html

As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level page tables (request with PASID) which performs GVA->GPA translation. Second level page tables are owned by the host for GPA->HPA translation for both request with and without PASID.

A new IOMMU driver interface is therefore needed to perform tasks as follows:
* Enable nested translation and appropriate translation type
* Assign guest PASID table pointer (in GPA) and size to host IOMMU

This patch introduces new API functions to perform bind/unbind guest PASID tables. Based on common data, model specific IOMMU drivers can be extended to perform the specific steps for binding pasid table of assigned devices.

Signed-off-by Jean-Philippe Brucker <[email protected]>

Signed-off-by Liu, Yi L <[email protected]>

Signed-off-by Ashok Raj <[email protected]>

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/iommu/iommu.c      | 19 +++++++++++++++++++
 include/linux/iommu.h      | 24 ++++++++++++++++++++++++
 include/uapi/linux/iommu.h | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 include/uapi/linux/iommu.h

drivers/iommu/iommu.c +19 -0

index d2aa2320..3a69620 100644
@@ -1325,6 +1325,25 @@ int iommu_attach_device(struct iommu_domain *domain, struct device *dev)
 }
 EXPORT_SYMBOL_GPL(iommu_attach_device);
 
+int iommu_bind_pasid_table(struct iommu_domain *domain, struct device *dev,
+			struct pasid_table_config *pasidt_binfo)
+{
+	if (unlikely(!domain->ops->bind_pasid_table))
+		return -ENODEV;
+
+	return domain->ops->bind_pasid_table(domain, dev, pasidt_binfo);
+}
+EXPORT_SYMBOL_GPL(iommu_bind_pasid_table);
+
+void iommu_unbind_pasid_table(struct iommu_domain *domain, struct device *dev)
+{
+	if (unlikely(!domain->ops->unbind_pasid_table))
+		return;
+
+	domain->ops->unbind_pasid_table(domain, dev);
+}
+EXPORT_SYMBOL_GPL(iommu_unbind_pasid_table);
+
 static void __iommu_detach_device(struct iommu_domain *domain,
 				  struct device *dev)
 {

include/linux/iommu.h +24 -0

index 19938ee..5199ca4 100644
@@ -25,6 +25,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/of.h>
+#include <uapi/linux/iommu.h>
 
 #define IOMMU_READ	(1 << 0)
 #define IOMMU_WRITE	(1 << 1)

@@ -187,6 +188,8 @@ struct iommu_resv_region {
  * @domain_get_windows: Return the number of windows for a domain
  * @of_xlate: add OF master IDs to iommu grouping
  * @pgsize_bitmap: bitmap of all possible supported page sizes
+ * @bind_pasid_table: bind pasid table pointer for guest SVM
+ * @unbind_pasid_table: unbind pasid table pointer and restore defaults
  */
 struct iommu_ops {
 	bool (*capable)(enum iommu_cap);

@@ -233,8 +236,14 @@ struct iommu_ops {
 	u32 (*domain_get_windows)(struct iommu_domain *domain);
 
 	int (*of_xlate)(struct device *dev, struct of_phandle_args *args);
+
 	bool (*is_attach_deferred)(struct iommu_domain *domain, struct device *dev);
 
+	int (*bind_pasid_table)(struct iommu_domain *domain, struct device *dev,
+				struct pasid_table_config *pasidt_binfo);
+	void (*unbind_pasid_table)(struct iommu_domain *domain,
+				struct device *dev);
+
 	unsigned long pgsize_bitmap;
 };
 

@@ -296,6 +305,10 @@ extern int iommu_attach_device(struct iommu_domain *domain,
 			       struct device *dev);
 extern void iommu_detach_device(struct iommu_domain *domain,
 				struct device *dev);
+extern int iommu_bind_pasid_table(struct iommu_domain *domain,
+		struct device *dev, struct pasid_table_config *pasidt_binfo);
+extern void iommu_unbind_pasid_table(struct iommu_domain *domain,
+				struct device *dev);
 extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev);
 extern int iommu_map(struct iommu_domain *domain, unsigned long iova,
 		     phys_addr_t paddr, size_t size, int prot);

@@ -696,6 +709,17 @@ const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode)
 	return NULL;
 }
 
+static inline
+int iommu_bind_pasid_table(struct iommu_domain *domain, struct device *dev,
+			struct pasid_table_config *pasidt_binfo)
+{
+	return -ENODEV;
+}
+static inline
+void iommu_unbind_pasid_table(struct iommu_domain *domain, struct device *dev)
+{
+}
+
 #endif /* CONFIG_IOMMU_API */
 
 #endif /* __LINUX_IOMMU_H */

include/uapi/linux/iommu.h new file +20 -0

new file mode 100644
index 0000000..cb2d625
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * IOMMU user API definitions
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _UAPI_IOMMU_H
+#define _UAPI_IOMMU_H
+
+#include <linux/types.h>
+
+/**
+ * PASID table data used to bind guest PASID table to the host IOMMU. This will
+ * enable guest managed first level page tables.
+ * @version: for future extensions and identification of the data format
+ * @bytes: size of this structure

include/uapi/linux/iommu.h new file +3 -0

+};
+
+#endif /* _UAPI_IOMMU_H */

From: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org [mailto:iommu- bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org] On Behalf Of Auger Eric
Sent: Friday, August 24, 2018 12:35 AM

Hi Jacob,

Quoted 24 lines · Jacob Pan

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest:
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html

As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level page tables (request with PASID) which performs GVA->GPA translation. Second level page tables are owned by the host for GPA->HPA translation for both request with and without PASID.

A new IOMMU driver interface is therefore needed to perform tasks as follows:
* Enable nested translation and appropriate translation type
* Assign guest PASID table pointer (in GPA) and size to host IOMMU

This patch introduces new API functions to perform bind/unbind guest PASID tables. Based on common data, model specific IOMMU drivers can be extended to perform the specific steps for binding pasid table of assigned devices.

Signed-off-by Jean-Philippe Brucker <[email protected]>

Signed-off-by Liu, Yi L <yi.l.liu-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Ashok Raj <[email protected]>

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---

include/uapi/linux/iommu.h

Quoted 12 lines

include/uapi/linux/iommu.h new file +12 -0

+#ifndef _UAPI_IOMMU_H
+#define _UAPI_IOMMU_H
+
+#include <linux/types.h>
+
+/**
+ * PASID table data used to bind guest PASID table to the host IOMMU. This will
+ * enable guest managed first level page tables.
+ * @version: for future extensions and identification of the data format
+ * @bytes: size of this structure
+ * @base_ptr:	PASID table pointer
+ * @pasid_bits:	number of bits supported in the guest PASID table, must be

less

include/uapi/linux/iommu.h line 30

Quoted 8 lines

+ * or equal than the host supported PASID size.
+ */

include/uapi/linux/iommu.h new file +6 -0

+struct pasid_table_config {
+	__u32 version;
+#define PASID_TABLE_CFG_VERSION_1 1
+	__u32 bytes;
+	__u64 base_ptr;
+	__u8 pasid_bits;

As reported in "[RFC 00/13] SMMUv3 Nested Stage Setup" thread, this API could be used for ARM SMMUv3 nested stage enablement without many changes. Assuming SMMUv3 nested stage is confirmed to be interesting for vendors and maintainers, we could try to unify the APIs.

As far as I understand the VTD PASID table is equivalent to the ARM SMMUv3 context descriptor table (CD). This corresponds to the stage 1 context table with one or more entries, each corresponding to one PASID.

maybe using the s1ctx_table_config terminology instead of pasid_table_config would be more generic, the pasid table being Intel naming.

on top of pasid_bits, I think an "asid_bits" field may be needed too. The guest IOMMU might support a different number of asid bits from the host one.

Although without having skimmed through the whole series yet, I wonder how you handle the case where stage1 is bypassed or disabled? The guest may define the S1 context entries but bypass or abort stage 1 translations globally. Looks something missing to me at first sight.

Hi Eric,

Quoted 31 lines

From: [email protected] [mailto:iommu- [email protected]] On Behalf Of Auger Eric
Sent: Friday, August 24, 2018 12:35 AM

Hi Jacob,

Quoted 24 lines · Jacob Pan

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest:
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html

As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level page tables (request with PASID) which performs GVA->GPA translation. Second level page tables are owned by the host for GPA->HPA translation for both request with and without PASID.

A new IOMMU driver interface is therefore needed to perform tasks as follows:
* Enable nested translation and appropriate translation type
* Assign guest PASID table pointer (in GPA) and size to host IOMMU

This patch introduces new API functions to perform bind/unbind guest PASID tables. Based on common data, model specific IOMMU drivers can be extended to perform the specific steps for binding pasid table of assigned devices.

Signed-off-by Jean-Philippe Brucker <[email protected]>

Signed-off-by Liu, Yi L <[email protected]>

Signed-off-by Ashok Raj <[email protected]>

Signed-off-by Jacob Pan <[email protected]>

---

[...]

Quoted 13 lines

include/uapi/linux/iommu.h

Quoted 12 lines

include/uapi/linux/iommu.h new file +12 -0

+#ifndef _UAPI_IOMMU_H
+#define _UAPI_IOMMU_H
+
+#include <linux/types.h>
+
+/**
+ * PASID table data used to bind guest PASID table to the host IOMMU. This will
+ * enable guest managed first level page tables.
+ * @version: for future extensions and identification of the data format
+ * @bytes: size of this structure
+ * @base_ptr:	PASID table pointer
+ * @pasid_bits:	number of bits supported in the guest PASID table, must be

less

Quoted 13 lines

include/uapi/linux/iommu.h line 30

Quoted 8 lines

+ * or equal than the host supported PASID size.
+ */

include/uapi/linux/iommu.h new file +6 -0

+struct pasid_table_config {
+	__u32 version;
+#define PASID_TABLE_CFG_VERSION_1 1
+	__u32 bytes;
+	__u64 base_ptr;
+	__u8 pasid_bits;

As reported in "[RFC 00/13] SMMUv3 Nested Stage Setup" thread, this API could be used for ARM SMMUv3 nested stage enablement without many changes. Assuming SMMUv3 nested stage is confirmed to be interesting for vendors and maintainers, we could try to unify the APIs.

Just a quick question on nested stage on SMMUv3. If virtualizer wants to enable nested stage on SMMUv3, does it link the whole guest CD table to host or do it in other manner?

Quoted 4 lines

As far as I understand the VTD PASID table is equivalent to the ARM SMMUv3 context descriptor table (CD). This corresponds to the stage 1 context table with one or more entries, each corresponding to one PASID.

PASID table is index by PASID, and have multiple entries. A PASID table would have 2^PASID_BITS entries.

Quoted 8 lines

maybe using the s1ctx_table_config terminology instead of pasid_table_config would be more generic, the pasid table being Intel naming.

on top of pasid_bits, I think an "asid_bits" field may be needed too. The guest IOMMU might support a different number of asid bits from the host one.

Maybe needed for SMMUv3. I've noticed you've placed it in struct iommu_smmu_s1_config.

Quoted 1 line

Quoted 4 lines

Although without having skimmed through the whole series yet, I wonder how you handle the case where stage1 is bypassed or disabled? The guest may define the S1 context entries but bypass or abort stage 1 translations globally. Looks something missing to me at first sight.

Sorry, I didn't quite follow here. What usage is case such for? like stage 1 is bypassed or disabled. IOVA or SVA?

Thanks,
Yi Liu

Hi Yi Liu,

Quoted 69 lines · Yi L

Hi Eric,

Quoted 33 lines

From: [email protected] [mailto:iommu- [email protected]] On Behalf Of Auger Eric
Sent: Friday, August 24, 2018 12:35 AM

Hi Jacob,

Quoted 26 lines · Jacob Pan

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest:
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html

As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level page tables (request with PASID) which performs GVA->GPA translation. Second level page tables are owned by the host for GPA->HPA translation for both request with and without PASID.

A new IOMMU driver interface is therefore needed to perform tasks as follows:
* Enable nested translation and appropriate translation type
* Assign guest PASID table pointer (in GPA) and size to host IOMMU

This patch introduces new API functions to perform bind/unbind guest PASID tables. Based on common data, model specific IOMMU drivers can be extended to perform the specific steps for binding pasid table of assigned devices.

Signed-off-by: Jean-Philippe Brucker <[email protected]> Signed-off-by: Liu, Yi L <[email protected]> Signed-off-by: Ashok Raj <[email protected]> Signed-off-by: Jacob Pan <[email protected]> ---

[...]

Quoted 16 lines

Quoted 7 lines

include/uapi/linux/iommu.h new file +7 -0

+#ifndef _UAPI_IOMMU_H
+#define _UAPI_IOMMU_H
+
+#include <linux/types.h>
+
+/**
+ * PASID table data used to bind guest PASID table to the host

Quoted 8 lines

IOMMU. This will
+ * enable guest managed first level page tables.
+ * @version: for future extensions and identification of the data format
+ * @bytes: size of this structure
+ * @base_ptr: PASID table pointer
+ * @pasid_bits: number of bits supported in the guest
PASID table, must be

less

Quoted 14 lines

include/uapi/linux/iommu.h line 30

Quoted 8 lines

+ * or equal than the host supported PASID size.
+ */

include/uapi/linux/iommu.h new file +6 -0

+struct pasid_table_config {
+	__u32 version;
+#define PASID_TABLE_CFG_VERSION_1 1
+	__u32 bytes;
+	__u64 base_ptr;
+	__u8 pasid_bits;  

As reported in "[RFC 00/13] SMMUv3 Nested Stage Setup" thread, this API could be used for ARM SMMUv3 nested stage enablement without many changes. Assuming SMMUv3 nested stage is confirmed to be interesting for vendors and maintainers, we could try to unify the APIs.

Quoted 3 lines

Just a quick question on nested stage on SMMUv3. If virtualizer wants to enable nested stage on SMMUv3, does it link the whole guest CD table to host or do it in other manner?

Yes that's correct. On ARM SMMUv3 you have Stream Table Entries (STEs, indexed by ReqID=streamid). If stage 1 is used, the STE points to 1 or more contiguous Context Descriptors (CDs).
So STE looks like the VTD Context-Entry and CD table looks like the VTD PASID table as far as I understand.

Quoted 8 lines

Quoted 5 lines

As far as I understand the VTD PASID table is equivalent to the ARM SMMUv3 context descriptor table (CD). This corresponds to the stage 1 context table with one or more entries, each corresponding to one PASID.

PASID table is index by PASID, and have multiple entries. A PASID table would have 2^PASID_BITS entries.

On ARM SMMUv3 the number of CDs is 2 ^STE.S1CDMax.

Quoted 13 lines

Quoted 8 lines

maybe using the s1ctx_table_config terminology instead of pasid_table_config would be more generic, the pasid table being Intel naming.

on top of pasid_bits, I think an "asid_bits" field may be needed too. The guest IOMMU might support a different number of asid bits from the host one.

Maybe needed for SMMUv3. I've noticed you've placed it in struct iommu_smmu_s1_config.

Quoted 1 line

Quoted 8 lines

Quoted 5 lines

Although without having skimmed through the whole series yet, I wonder how you handle the case where stage1 is bypassed or disabled? The guest may define the S1 context entries but bypass or abort stage 1 translations globally. Looks something missing to me at first sight.

Sorry, I didn't quite follow here. What usage is case such for? like stage 1 is bypassed or disabled. IOVA or SVA?

Each STE entry has a config field which tells how S1 and S2 behave

Options are no traffic at all or any combination of the following:

S1        S2
bypass    bypass
transl    bypass
bypass    transl
transl    transl

host manages S2 info. guest sets S1 related fields.

To me the guest SET.Config should be passed to the host so that this latter writes the correct global Config field value in the STE, including S1 + S2 info.

Thanks

Eric

Quoted 4 lines

Thanks,
Yi Liu

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest:
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html

As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level page tables (request with PASID) which performs GVA->GPA translation. Second level page tables are owned by the host for GPA->HPA translation for both request with and without PASID.

A new IOMMU driver interface is therefore needed to perform tasks as follows:
* Enable nested translation and appropriate translation type
* Assign guest PASID table pointer (in GPA) and size to host IOMMU

This patch introduces new API functions to perform bind/unbind guest PASID tables. Based on common data, model specific IOMMU drivers can be extended to perform the specific steps for binding pasid table of assigned devices.

Signed-off-by Jean-Philippe Brucker <[email protected]>

Signed-off-by Liu, Yi L <[email protected]>

Signed-off-by Ashok Raj <[email protected]>

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/iommu/iommu.c      | 19 +++++++++++++++++++
 include/linux/iommu.h      | 24 ++++++++++++++++++++++++
 include/uapi/linux/iommu.h | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 include/uapi/linux/iommu.h

drivers/iommu/iommu.c +0 -0

index d2aa2320..3a69620 100644

drivers/iommu/iommu.c +17 -0

+{
+	if (unlikely(!domain->ops->bind_pasid_table))
+		return -ENODEV;
+
+	return domain->ops->bind_pasid_table(domain, dev, pasidt_binfo);
+}
+EXPORT_SYMBOL_GPL(iommu_bind_pasid_table);
+
+void iommu_unbind_pasid_table(struct iommu_domain *domain, struct device *dev)
+{
+	if (unlikely(!domain->ops->unbind_pasid_table))
+		return;
+
+	domain->ops->unbind_pasid_table(domain, dev);
+}
+EXPORT_SYMBOL_GPL(iommu_unbind_pasid_table);
+
 static void __iommu_detach_device(struct iommu_domain *domain,
 				  struct device *dev)
 {

include/linux/iommu.h +24 -0

index 19938ee..5199ca4 100644
@@ -25,6 +25,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/of.h>
+#include <uapi/linux/iommu.h>
 
 #define IOMMU_READ	(1 << 0)
 #define IOMMU_WRITE	(1 << 1)

@@ -187,6 +188,8 @@ struct iommu_resv_region {
  * @domain_get_windows: Return the number of windows for a domain
  * @of_xlate: add OF master IDs to iommu grouping
  * @pgsize_bitmap: bitmap of all possible supported page sizes
+ * @bind_pasid_table: bind pasid table pointer for guest SVM
+ * @unbind_pasid_table: unbind pasid table pointer and restore defaults
  */
 struct iommu_ops {
 	bool (*capable)(enum iommu_cap);

@@ -233,8 +236,14 @@ struct iommu_ops {
 	u32 (*domain_get_windows)(struct iommu_domain *domain);
 
 	int (*of_xlate)(struct device *dev, struct of_phandle_args *args);
+
 	bool (*is_attach_deferred)(struct iommu_domain *domain, struct device *dev);
 
+	int (*bind_pasid_table)(struct iommu_domain *domain, struct device *dev,
+				struct pasid_table_config *pasidt_binfo);
+	void (*unbind_pasid_table)(struct iommu_domain *domain,
+				struct device *dev);
+
 	unsigned long pgsize_bitmap;
 };
 

@@ -296,6 +305,10 @@ extern int iommu_attach_device(struct iommu_domain *domain,
 			       struct device *dev);
 extern void iommu_detach_device(struct iommu_domain *domain,
 				struct device *dev);
+extern int iommu_bind_pasid_table(struct iommu_domain *domain,
+		struct device *dev, struct pasid_table_config *pasidt_binfo);
+extern void iommu_unbind_pasid_table(struct iommu_domain *domain,
+				struct device *dev);
 extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev);
 extern int iommu_map(struct iommu_domain *domain, unsigned long iova,
 		     phys_addr_t paddr, size_t size, int prot);

@@ -696,6 +709,17 @@ const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode)
 	return NULL;
 }
 
+static inline
+int iommu_bind_pasid_table(struct iommu_domain *domain, struct device *dev,
+			struct pasid_table_config *pasidt_binfo)
+{
+	return -ENODEV;
+}
+static inline
+void iommu_unbind_pasid_table(struct iommu_domain *domain, struct device *dev)
+{
+}
+
 #endif /* CONFIG_IOMMU_API */
 
 #endif /* __LINUX_IOMMU_H */

include/uapi/linux/iommu.h new file +21 -0

new file mode 100644
index 0000000..cb2d625
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * IOMMU user API definitions
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _UAPI_IOMMU_H
+#define _UAPI_IOMMU_H
+
+#include <linux/types.h>
+
+/**
+ * PASID table data used to bind guest PASID table to the host IOMMU. This will
+ * enable guest managed first level page tables.
+ * @version: for future extensions and identification of the data format
+ * @bytes: size of this structure
+ * @base_ptr:	PASID table pointer

include/uapi/linux/iommu.h new file +2 -0

+
+#endif /* _UAPI_IOMMU_H */

Hi Jacob,

Quoted 37 lines · Jacob Pan

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest:
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html

As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level page tables (request with PASID) which performs GVA->GPA translation. Second level page tables are owned by the host for GPA->HPA translation for both request with and without PASID.

A new IOMMU driver interface is therefore needed to perform tasks as follows:
* Enable nested translation and appropriate translation type
* Assign guest PASID table pointer (in GPA) and size to host IOMMU

This patch introduces new API functions to perform bind/unbind guest PASID tables. Based on common data, model specific IOMMU drivers can be extended to perform the specific steps for binding pasid table of assigned devices.

Signed-off-by Jean-Philippe Brucker <[email protected]>

Signed-off-by Liu, Yi L <[email protected]>

Signed-off-by Ashok Raj <[email protected]>

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/iommu/iommu.c      | 19 +++++++++++++++++++
 include/linux/iommu.h      | 24 ++++++++++++++++++++++++
 include/uapi/linux/iommu.h | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 include/uapi/linux/iommu.h

drivers/iommu/iommu.c +0 -0

index d2aa2320..3a69620 100644

drivers/iommu/iommu.c int iommu_attach_device(struct iommu_domain · line 1330

Quoted 6 lines

drivers/iommu/iommu.c +2 -0

@@ -1325,6 +1325,25 @@ int iommu_attach_device(struct iommu_domain
 *domain, struct device *dev) }
 EXPORT_SYMBOL_GPL(iommu_attach_device);
 
+int iommu_bind_pasid_table(struct iommu_domain *domain, struct
 device *dev,
+			struct pasid_table_config *pasidt_binfo)  

As Jean-Philippe, I must confessed i am very confused by having both the iommu_domain and dev passed as argument.

I know this was discussed when the RFC was submitted and maybe I missed the main justification behind that choice. I understand that at the HW level we want to change the context entry or ARM CD in my case for a specific device. But on other hand, at the logical level, I understand the iommu_domain is representing a set of translation config & page tables shared by all the devices within the domain (hope this is fundamentally correct ?!). So to me we can't change the device translation setup without changing the whole iommu_device setup otherwise this would mean this device has a translation configuration that is not consistent anymore with the other devices in the same domain. Is that correct? So can't we only keep the iommu_domain arg?

Quoted 125 lines

drivers/iommu/iommu.c +15 -0

+{
+	if (unlikely(!domain->ops->bind_pasid_table))
+		return -ENODEV;
+
+	return domain->ops->bind_pasid_table(domain, dev,
 pasidt_binfo); +}
+EXPORT_SYMBOL_GPL(iommu_bind_pasid_table);
+
+void iommu_unbind_pasid_table(struct iommu_domain *domain, struct
 device *dev) +{
+	if (unlikely(!domain->ops->unbind_pasid_table))
+		return;
+
+	domain->ops->unbind_pasid_table(domain, dev);
+}
+EXPORT_SYMBOL_GPL(iommu_unbind_pasid_table);
+
 static void __iommu_detach_device(struct iommu_domain *domain,
 				  struct device *dev)
 {

include/linux/iommu.h +3 -0

index 19938ee..5199ca4 100644
@@ -25,6 +25,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/of.h>
+#include <uapi/linux/iommu.h>
 
 #define IOMMU_READ	(1 << 0)
 #define IOMMU_WRITE	(1 << 1)

@@ -187,6 +188,8 @@ struct iommu_resv_region {
  * @domain_get_windows: Return the number of windows for a domain
  * @of_xlate: add OF master IDs to iommu grouping
  * @pgsize_bitmap: bitmap of all possible supported page sizes
+ * @bind_pasid_table: bind pasid table pointer for guest SVM
+ * @unbind_pasid_table: unbind pasid table pointer and restore

defaults */
struct iommu_ops {

include/linux/iommu.h +8 -0

 	bool (*capable)(enum iommu_cap);

@@ -233,8 +236,14 @@ struct iommu_ops {
 	u32 (*domain_get_windows)(struct iommu_domain *domain);
 
 	int (*of_xlate)(struct device *dev, struct of_phandle_args
 *args); +
 	bool (*is_attach_deferred)(struct iommu_domain *domain,
 struct device *dev); 
+	int (*bind_pasid_table)(struct iommu_domain *domain,
 struct device *dev,
+				struct pasid_table_config
 *pasidt_binfo);
+	void (*unbind_pasid_table)(struct iommu_domain *domain,
+				struct device *dev);
+
 	unsigned long pgsize_bitmap;
 };

@@ -296,6 +305,10 @@ extern int iommu_attach_device(struct
 iommu_domain *domain, struct device *dev);
 extern void iommu_detach_device(struct iommu_domain *domain,
 				struct device *dev);
+extern int iommu_bind_pasid_table(struct iommu_domain *domain,
+		struct device *dev, struct pasid_table_config
 *pasidt_binfo); +extern void iommu_unbind_pasid_table(struct
 iommu_domain *domain,
+				struct device *dev);
 extern struct iommu_domain *iommu_get_domain_for_dev(struct device

*dev); extern int iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot);

include/linux/iommu.h +10 -0

@@ -696,6 +709,17 @@ const struct iommu_ops
 *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) return NULL;
 }
 
+static inline
+int iommu_bind_pasid_table(struct iommu_domain *domain, struct
 device *dev,
+			struct pasid_table_config *pasidt_binfo)
+{
+	return -ENODEV;
+}
+static inline
+void iommu_unbind_pasid_table(struct iommu_domain *domain, struct
 device *dev) +{
+}
+
 #endif /* CONFIG_IOMMU_API */
 
 #endif /* __LINUX_IOMMU_H */

include/uapi/linux/iommu.h new file +6 -0

new file mode 100644
index 0000000..cb2d625
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * IOMMU user API definitions
+ *
+ *
+ * This program is free software; you can redistribute it and/or

modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */

include/uapi/linux/iommu.h new file +8 -0

+
+#ifndef _UAPI_IOMMU_H
+#define _UAPI_IOMMU_H
+
+#include <linux/types.h>
+
+/**
+ * PASID table data used to bind guest PASID table to the host

IOMMU. This will
+ * enable guest managed first level page tables.
+ * @version: for future extensions and identification of the data format
+ * @bytes: size of this structure
+ * @base_ptr: PASID table pointer
+ * @pasid_bits: number of bits supported in the guest PASID
table, must be less
+ * or equal than the host supported PASID size.
+ */
+struct pasid_table_config {

include/uapi/linux/iommu.h line 31

Quoted 6 lines

include/uapi/linux/iommu.h new file +6 -0

+	__u32 version;
+#define PASID_TABLE_CFG_VERSION_1 1
+	__u32 bytes;
+	__u64 base_ptr;
+	__u8 pasid_bits;
+};  

Don't we need to index all structs with iommu_ to protect the naming spaces? Same comment on other patches impacting the uapi.

A question about the alignment. Don't we need to be 64b aligned? VFIO uapi structs are.

Thanks

Eric

include/uapi/linux/iommu.h

Quoted 3 lines

include/uapi/linux/iommu.h new file +2 -0

+
+#endif /* _UAPI_IOMMU_H */

Quoted 49 lines · On Fri, 24 Aug 2018 17:00:51 +0200 Auger Eric…

Hi Jacob,

Quoted 37 lines · Jacob Pan

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest:
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html

As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level page tables (request with PASID) which performs GVA->GPA translation. Second level page tables are owned by the host for GPA->HPA translation for both request with and without PASID.

A new IOMMU driver interface is therefore needed to perform tasks as follows:
* Enable nested translation and appropriate translation type
* Assign guest PASID table pointer (in GPA) and size to host IOMMU

This patch introduces new API functions to perform bind/unbind guest PASID tables. Based on common data, model specific IOMMU drivers can be extended to perform the specific steps for binding pasid table of assigned devices.

Signed-off-by Jean-Philippe Brucker <[email protected]>

Signed-off-by Liu, Yi L <yi.l.liu-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Ashok Raj <[email protected]>

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/iommu/iommu.c      | 19 +++++++++++++++++++
 include/linux/iommu.h      | 24 ++++++++++++++++++++++++
 include/uapi/linux/iommu.h | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 include/uapi/linux/iommu.h

drivers/iommu/iommu.c +0 -0

index d2aa2320..3a69620 100644

drivers/iommu/iommu.c int iommu_attach_device(struct iommu_domain · line 1330

Quoted 6 lines

drivers/iommu/iommu.c +2 -0

@@ -1325,6 +1325,25 @@ int iommu_attach_device(struct iommu_domain
 *domain, struct device *dev) }
 EXPORT_SYMBOL_GPL(iommu_attach_device);
 
+int iommu_bind_pasid_table(struct iommu_domain *domain, struct
 device *dev,
+			struct pasid_table_config *pasidt_binfo)  

As Jean-Philippe, I must confessed i am very confused by having both the iommu_domain and dev passed as argument.

Quoted 12 lines

I know this was discussed when the RFC was submitted and maybe I missed the main justification behind that choice. I understand that at the HW level we want to change the context entry or ARM CD in my case for a specific device. But on other hand, at the logical level, I understand the iommu_domain is representing a set of translation config & page tables shared by all the devices within the domain (hope this is fundamentally correct ?!). So to me we can't change the device translation setup without changing the whole iommu_device setup otherwise this would mean this device has a translation configuration that is not consistent anymore with the other devices in the same domain. Is that correct? So can't we only keep the iommu_domain arg?

I agree with you on your understanding of HW and logical level. I think there is a new twist to the definition of domain introduced by having PASID and vSVA. Up until now, domain only means 2nd level mapping. In that sense, bind guest PASID table does not alter domain. For VT-d 2.5 spec. implementation of the bind_pasid_table(), we needed some per device data, also flags such as indication for IO page fault handling.

Anyway, for the new VT-d 3.0 spec. we no longer need this API. In stead, I will introduce bind_guest_pasid() API, where per device PASID table is allocated by the host.

Quoted 126 lines

Quoted 126 lines

drivers/iommu/iommu.c +15 -0

+{
+	if (unlikely(!domain->ops->bind_pasid_table))
+		return -ENODEV;
+
+	return domain->ops->bind_pasid_table(domain, dev,
 pasidt_binfo); +}
+EXPORT_SYMBOL_GPL(iommu_bind_pasid_table);
+
+void iommu_unbind_pasid_table(struct iommu_domain *domain, struct
 device *dev) +{
+	if (unlikely(!domain->ops->unbind_pasid_table))
+		return;
+
+	domain->ops->unbind_pasid_table(domain, dev);
+}
+EXPORT_SYMBOL_GPL(iommu_unbind_pasid_table);
+
 static void __iommu_detach_device(struct iommu_domain *domain,
 				  struct device *dev)
 {

include/linux/iommu.h +3 -0

index 19938ee..5199ca4 100644
@@ -25,6 +25,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/of.h>
+#include <uapi/linux/iommu.h>
 
 #define IOMMU_READ	(1 << 0)
 #define IOMMU_WRITE	(1 << 1)

@@ -187,6 +188,8 @@ struct iommu_resv_region {
  * @domain_get_windows: Return the number of windows for a domain
  * @of_xlate: add OF master IDs to iommu grouping
  * @pgsize_bitmap: bitmap of all possible supported page sizes
+ * @bind_pasid_table: bind pasid table pointer for guest SVM
+ * @unbind_pasid_table: unbind pasid table pointer and restore

defaults */
struct iommu_ops {

include/linux/iommu.h +8 -0

 	bool (*capable)(enum iommu_cap);

@@ -233,8 +236,14 @@ struct iommu_ops {
 	u32 (*domain_get_windows)(struct iommu_domain *domain);
 
 	int (*of_xlate)(struct device *dev, struct of_phandle_args
 *args); +
 	bool (*is_attach_deferred)(struct iommu_domain *domain,
 struct device *dev); 
+	int (*bind_pasid_table)(struct iommu_domain *domain,
 struct device *dev,
+				struct pasid_table_config
 *pasidt_binfo);
+	void (*unbind_pasid_table)(struct iommu_domain *domain,
+				struct device *dev);
+
 	unsigned long pgsize_bitmap;
 };

@@ -296,6 +305,10 @@ extern int iommu_attach_device(struct
 iommu_domain *domain, struct device *dev);
 extern void iommu_detach_device(struct iommu_domain *domain,
 				struct device *dev);
+extern int iommu_bind_pasid_table(struct iommu_domain *domain,
+		struct device *dev, struct pasid_table_config
 *pasidt_binfo); +extern void iommu_unbind_pasid_table(struct
 iommu_domain *domain,
+				struct device *dev);
 extern struct iommu_domain *iommu_get_domain_for_dev(struct device

*dev); extern int iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot);

include/linux/iommu.h +10 -0

@@ -696,6 +709,17 @@ const struct iommu_ops
 *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) return NULL;
 }
 
+static inline
+int iommu_bind_pasid_table(struct iommu_domain *domain, struct
 device *dev,
+			struct pasid_table_config *pasidt_binfo)
+{
+	return -ENODEV;
+}
+static inline
+void iommu_unbind_pasid_table(struct iommu_domain *domain, struct
 device *dev) +{
+}
+
 #endif /* CONFIG_IOMMU_API */
 
 #endif /* __LINUX_IOMMU_H */

include/uapi/linux/iommu.h new file +6 -0

new file mode 100644
index 0000000..cb2d625
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * IOMMU user API definitions
+ *
+ *
+ * This program is free software; you can redistribute it and/or

modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */

include/uapi/linux/iommu.h new file +8 -0

+
+#ifndef _UAPI_IOMMU_H
+#define _UAPI_IOMMU_H
+
+#include <linux/types.h>
+
+/**
+ * PASID table data used to bind guest PASID table to the host

IOMMU. This will
+ * enable guest managed first level page tables.
+ * @version: for future extensions and identification of the data format
+ * @bytes: size of this structure
+ * @base_ptr: PASID table pointer
+ * @pasid_bits: number of bits supported in the guest PASID
table, must be less
+ * or equal than the host supported PASID size.
+ */
+struct pasid_table_config {

Quoted 9 lines

include/uapi/linux/iommu.h line 31

Quoted 6 lines

include/uapi/linux/iommu.h new file +6 -0

+	__u32 version;
+#define PASID_TABLE_CFG_VERSION_1 1
+	__u32 bytes;
+	__u64 base_ptr;
+	__u8 pasid_bits;
+};  

Don't we need to index all structs with iommu_ to protect the naming spaces? Same comment on other patches impacting the uapi.

yeah, it would be better to use iommu_ prefix, i was thinking vfio also uses it and pasid itself is a industry standard.

Quoted 3 lines

A question about the alignment. Don't we need to be 64b aligned? VFIO uapi structs are.

I am not sure about the benefit, this is not a HW interface nor on speed path.

Quoted 6 lines

Thanks

Eric

include/uapi/linux/iommu.h

Quoted 3 lines

include/uapi/linux/iommu.h new file +2 -0

+
+#endif /* _UAPI_IOMMU_H */

[Jacob Pan]

Quoted 3 lines

Anyway, for the new VT-d 3.0 spec. we no longer need this API. In stead, I will introduce bind_guest_pasid() API, where per device PASID table is allocated by the host.

So what is the exact state of this series? Is it outdated as you don't target VT-d 2.5 anymore? Will you keep the rest of the API?

Adding a flag in device domain into to track whether a guest or

user PASID table is bound to a device.

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 include/linux/intel-iommu.h | 1 +
 1 file changed, 1 insertion(+)

include/linux/intel-iommu.h +1 -0

index 304afae..ddc7d79 100644
@@ -473,6 +473,7 @@ struct device_domain_info {
 	u8 pri_enabled:1;
 	u8 ats_supported:1;
 	u8 ats_enabled:1;
+	u8 pasid_table_bound:1;
 	u8 ats_qdep;
 	u64 fault_mask;	/* selected IOMMU faults to be reported */
 	struct device *dev; /* it's NULL for PCIe-to-PCI bridge */

Hi,

Quoted 1 line · Jacob Pan

Adding a flag in device domain into to track whether a guest or

typo: ^^info

Best regards,
Lu Baolu

[...]

Adding a flag in device domain into to track whether a guest or user PASID table is bound to a device.

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 include/linux/intel-iommu.h | 1 +
 1 file changed, 1 insertion(+)

include/linux/intel-iommu.h +0 -0

index 304afae..ddc7d79 100644

include/linux/intel-iommu.h +0 -0

 	u8 ats_qdep;
 	u64 fault_mask;	/* selected IOMMU faults to be reported */
 	struct device *dev; /* it's NULL for PCIe-to-PCI bridge */

include/linux/intel-iommu.h struct device_domain_info { · line 476

Quoted 1 line

include/linux/intel-iommu.h +1 -0

+	u8 pasid_table_bound:1;  

Can you please add some comments here? So that, people can understand the purpose for this bit exactly.

Add Intel VT-d ops to the generic iommu_bind_pasid_table API functions.

The primary use case is for direct assignment of SVM capable device. Originated from emulated IOMMU in the guest, the request goes through many layers (e.g. VFIO). Upon calling host IOMMU driver, caller passes guest PASID table pointer (GPA) and size.

Device context table entry is modified by Intel IOMMU specific bind_pasid_table function. This will turn on nesting mode and matching translation type.

The unbind operation restores default context mapping.

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Liu, Yi L <yi.l.liu-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Ashok Raj <[email protected]>

---
 drivers/iommu/intel-iommu.c   | 122 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/dma_remapping.h |   1 +
 2 files changed, 123 insertions(+)

drivers/iommu/intel-iommu.c +6 -0

index a0f81a4..4623294 100644
@@ -2409,6 +2409,7 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
 	info->ats_supported = info->pasid_supported = info->pri_supported = 0;
 	info->ats_enabled = info->pasid_enabled = info->pri_enabled = 0;
 	info->ats_qdep = 0;
+	info->pasid_table_bound = 0;
 	info->dev = dev;
 	info->domain = domain;
 	info->iommu = iommu;

@@ -5132,6 +5133,7 @@ static void intel_iommu_put_resv_regions(struct device *dev,
 
 #ifdef CONFIG_INTEL_IOMMU_SVM
 #define MAX_NR_PASID_BITS (20)
+#define MIN_NR_PASID_BITS (5)
 static inline unsigned long intel_iommu_get_pts(struct intel_iommu *iommu)
 {
 	/*

@@ -5258,6 +5260,122 @@ struct intel_iommu *intel_svm_device_to_iommu(struct device *dev)
 
 	return iommu;
 }
+
+static int intel_iommu_bind_pasid_table(struct iommu_domain *domain,
+		struct device *dev, struct pasid_table_config *pasidt_binfo)
+{

drivers/iommu/intel-iommu.c +64 -0

+	spin_lock_irqsave(&iommu->lock, flags);
+	context = iommu_context_addr(iommu, bus, devfn, 0);
+	if (!context_present(context)) {
+		dev_err(dev, "Context not present\n");
+		ret = -EINVAL;
+		goto out_unlock;
+	}
+
+	/* Anticipate guest to use SVM and owns the first level, so we turn
+	 * nested mode on
+	 */
+	ctx_lo = context[0].lo;
+	ctx_lo |= CONTEXT_NESTE | CONTEXT_PRS | CONTEXT_PASIDE;
+	ctx_lo &= ~CONTEXT_TT_MASK;
+	ctx_lo |= CONTEXT_TT_DEV_IOTLB << 2;
+	context[0].lo = ctx_lo;
+
+	/* Assign guest PASID table pointer and size order */
+	ctx_lo = (pasidt_binfo->base_ptr & VTD_PAGE_MASK) |
+		(pasidt_binfo->pasid_bits - MIN_NR_PASID_BITS);
+	context[1].lo = ctx_lo;
+	/* make sure context entry is updated before flushing */
+	wmb();
+	did = dmar_domain->iommu_did[iommu->seq_id];
+	iommu->flush.flush_context(iommu, did,
+				(((u16)bus) << 8) | devfn,
+				DMA_CCMD_MASK_NOBIT,
+				DMA_CCMD_DEVICE_INVL);
+	iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
+	info->pasid_table_bound = 1;
+out_unlock:
+	spin_unlock_irqrestore(&iommu->lock, flags);
+out:
+	return ret;
+}
+
+static void intel_iommu_unbind_pasid_table(struct iommu_domain *domain,
+					struct device *dev)
+{
+	struct intel_iommu *iommu;
+	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
+	struct device_domain_info *info;
+	u8 bus, devfn;
+
+	info = dev->archdata.iommu;
+	if (!info) {
+		dev_err(dev, "Invalid device domain info\n");
+		return;
+	}
+	iommu = device_to_iommu(dev, &bus, &devfn);
+	if (!iommu) {
+		dev_err(dev, "No IOMMU for device to unbind PASID table\n");
+		return;
+	}
+
+	domain_context_clear(iommu, dev);
+
+	domain_context_mapping_one(dmar_domain, iommu, bus, devfn);
+	info->pasid_table_bound = 0;
+}
 #endif /* CONFIG_INTEL_IOMMU_SVM */
 
 const struct iommu_ops intel_iommu_ops = {

@@ -5266,6 +5384,10 @@ const struct iommu_ops intel_iommu_ops = {
 	.domain_free		= intel_iommu_domain_free,
 	.attach_dev		= intel_iommu_attach_device,
 	.detach_dev		= intel_iommu_detach_device,
+#ifdef CONFIG_INTEL_IOMMU_SVM
+	.bind_pasid_table	= intel_iommu_bind_pasid_table,
+	.unbind_pasid_table	= intel_iommu_unbind_pasid_table,
+#endif
 	.map			= intel_iommu_map,
 	.unmap			= intel_iommu_unmap,
 	.map_sg			= default_iommu_map_sg,

include/linux/dma_remapping.h +0 -0

index 21b3e7d..db290b2 100644

Hi,

Quoted 53 lines · Jacob Pan

Add Intel VT-d ops to the generic iommu_bind_pasid_table API functions.

The primary use case is for direct assignment of SVM capable device. Originated from emulated IOMMU in the guest, the request goes through many layers (e.g. VFIO). Upon calling host IOMMU driver, caller passes guest PASID table pointer (GPA) and size.

Device context table entry is modified by Intel IOMMU specific bind_pasid_table function. This will turn on nesting mode and matching translation type.

The unbind operation restores default context mapping.

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Liu, Yi L <yi.l.liu-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Ashok Raj <[email protected]>

---
 drivers/iommu/intel-iommu.c   | 122

++++++++++++++++++++++++++++++++++++++++++
include/linux/dma_remapping.h | 1 + 2 files changed, 123
insertions(+)

(quoted diff) +0 -0

b/drivers/iommu/intel-iommu.c index a0f81a4..4623294 100644

drivers/iommu/intel-iommu.c +0 -0

@@ -2409,6 +2409,7 @@ static struct dmar_domain
 *dmar_insert_one_dev_info(struct intel_iommu *iommu,

info->ats_supported = info->pasid_supported = info->pri_supported = 0; info->ats_enabled = info->pasid_enabled = info->pri_enabled = 0; info->ats_qdep = 0;

drivers/iommu/intel-iommu.c +5 -0

+	info->pasid_table_bound = 0;
 	info->dev = dev;
 	info->domain = domain;
 	info->iommu = iommu;

@@ -5132,6 +5133,7 @@ static void
 intel_iommu_put_resv_regions(struct device *dev, 
 #ifdef CONFIG_INTEL_IOMMU_SVM
 #define MAX_NR_PASID_BITS (20)
+#define MIN_NR_PASID_BITS (5)
 static inline unsigned long intel_iommu_get_pts(struct intel_iommu
 *iommu) {
 	/*

@@ -5258,6 +5260,122 @@ struct intel_iommu
 *intel_svm_device_to_iommu(struct device *dev) 
 	return iommu;
 }
+
+static int intel_iommu_bind_pasid_table(struct iommu_domain
 *domain,
+		struct device *dev, struct pasid_table_config
 *pasidt_binfo) +{

drivers/iommu/intel-iommu.c struct intel_iommu · line 5277

Quoted 10 lines

drivers/iommu/intel-iommu.c +10 -0

+	struct intel_iommu *iommu;
+	struct context_entry *context;
+	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
+	struct device_domain_info *info;
+	struct pci_dev *pdev;
+	u8 bus, devfn, host_table_pasid_bits;
+	u16 did, sid;
+	int ret = 0;
+	unsigned long flags;
+	u64 ctx_lo;  

I personally prefer to have this in order.

        struct dmar_domain *dmar_domain = to_dmar_domain(domain);
        u8 bus, devfn, host_table_pasid_bits;
        struct device_domain_info *info;
        struct context_entry *context;
        struct intel_iommu *iommu;
        struct pci_dev *pdev;
        unsigned long flags;
        u16 did, sid;
        int ret = 0;
        u64 ctx_lo;

Quoted 3 lines

drivers/iommu/intel-iommu.c +2 -0

+
+	if ((pasidt_binfo->version != PASID_TABLE_CFG_VERSION_1)

||

Unnecessary parentheses.

drivers/iommu/intel-iommu.c struct intel_iommu *intel_svm_device_to_iommu(struct device *dev) · line 5279

Quoted 1 line

drivers/iommu/intel-iommu.c +1 -0

+		pasidt_binfo->bytes != sizeof(*pasidt_binfo))  

Alignment should match open parenthesis.

Quoted 10 lines

drivers/iommu/intel-iommu.c +5 -0

+		return -EINVAL;
+	iommu = device_to_iommu(dev, &bus, &devfn);
+	if (!iommu)
+		return -ENODEV;
+	/* VT-d spec section 9.4 says pasid table size is encoded

as 2^(x+5) */

drivers/iommu/intel-iommu.c +1 -0

+	host_table_pasid_bits = intel_iommu_get_pts(iommu) +

MIN_NR_PASID_BITS;

drivers/iommu/intel-iommu.c +1 -0

+	if (!pasidt_binfo || pasidt_binfo->pasid_bits >

host_table_pasid_bits ||

"!pasidt_binfo" checking should be moved up to the version checking.

Quoted 3 lines

drivers/iommu/intel-iommu.c +2 -0

+		pasidt_binfo->pasid_bits < MIN_NR_PASID_BITS) {
+		pr_err("Invalid gPASID bits %d, host range %d -

%d\n",

How about dev_err()?

drivers/iommu/intel-iommu.c

Quoted 9 lines

drivers/iommu/intel-iommu.c +6 -0

+			pasidt_binfo->pasid_bits,
+			MIN_NR_PASID_BITS, host_table_pasid_bits);
+		return -ERANGE;
+	}
+	if (!ecap_nest(iommu->ecap)) {
+		dev_err(dev, "Cannot bind PASID table, no nested

translation\n");

drivers/iommu/intel-iommu.c +2 -0

+		ret = -ENODEV;
+		goto out;  

How about
+ return -ENODEV;
?

drivers/iommu/intel-iommu.c

Quoted 2 lines

drivers/iommu/intel-iommu.c +2 -0

+	}
+	pdev = to_pci_dev(dev);  

We can't always assume that it is a PCI device, right?

drivers/iommu/intel-iommu.c struct intel_iommu *intel_svm_device_to_iommu(struct device *dev) · line 5307

Quoted 9 lines

drivers/iommu/intel-iommu.c +9 -0

+	sid = PCI_DEVID(bus, devfn);
+	info = dev->archdata.iommu;
+
+	if (!info) {
+		dev_err(dev, "Invalid device domain info\n");
+		ret = -EINVAL;
+		goto out;
+	}
+	if (info->pasid_table_bound) {  

We should do this checking with lock hold.

Otherwise,

Thread A on CPUx Thread B on CPUy
=========== ============
check pasid_table_bound check pasid_table_bound

mutex_lock()
Setup context
pasid_table_bound = 1
mutex_unlock()

mutex_lock() Setup context pasid_table_bound = 1 mutex_unlock()

drivers/iommu/intel-iommu.c struct intel_iommu *intel_svm_device_to_iommu(struct device *dev) · line 5318

Quoted 12 lines

drivers/iommu/intel-iommu.c +6 -0

+		dev_err(dev, "Device PASID table already bound\n");
+		ret = -EBUSY;
+		goto out;
+	}
+	if (!info->pasid_enabled) {
+		ret = pci_enable_pasid(pdev, info->pasid_supported

& ~1);

drivers/iommu/intel-iommu.c +5 -0

+		if (ret) {
+			dev_err(dev, "Failed to enable PASID\n");
+			goto out;
+		}
+	}  

I prefer a blank line here.

[...]

Best regards,
Lu Baolu

When SRIOV VF device IOTLB is invalidated, we need to provide the PF source ID such that IOMMU hardware can gauge the depth of invalidation queue which is shared among VFs. This is needed when device invalidation throttle (DIT) capability is supported.

This patch adds bit definitions for checking and tracking PFSID.

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 include/linux/intel-iommu.h | 4 ++++
 1 file changed, 4 insertions(+)

include/linux/intel-iommu.h +2 -0

index ddc7d79..dfacd49 100644
@@ -114,6 +114,7 @@
  * Extended Capability Register
  */
 
+#define ecap_dit(e)		((e >> 41) & 0x1)
 #define ecap_pasid(e)		((e >> 40) & 0x1)
 #define ecap_pss(e)		((e >> 35) & 0x1f)
 #define ecap_eafs(e)		((e >> 34) & 0x1)

@@ -284,6 +285,7 @@ enum {
 #define QI_DEV_IOTLB_SID(sid)	((u64)((sid) & 0xffff) << 32)
 #define QI_DEV_IOTLB_QDEP(qdep)	(((qdep) & 0x1f) << 16)
 #define QI_DEV_IOTLB_ADDR(addr)	((u64)(addr) & VTD_PAGE_MASK)
+#define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xff0) << 48))
 #define QI_DEV_IOTLB_SIZE	1
 #define QI_DEV_IOTLB_MAX_INVS	32
 

Hi,

Quoted 6 lines · Jacob Pan

When SRIOV VF device IOTLB is invalidated, we need to provide the PF source ID such that IOMMU hardware can gauge the depth of invalidation queue which is shared among VFs. This is needed when device invalidation throttle (DIT) capability is supported.

This patch adds bit definitions for checking and tracking PFSID.

Patch 6 and 7 could be posted in a separated patch series.

Quoted 27 lines

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 include/linux/intel-iommu.h | 4 ++++
 1 file changed, 4 insertions(+)

(quoted diff) +0 -0

b/include/linux/intel-iommu.h index ddc7d79..dfacd49 100644

include/linux/intel-iommu.h +1 -0

@@ -114,6 +114,7 @@
  * Extended Capability Register
  */
 
+#define ecap_dit(e)		((e >> 41) & 0x1)
 #define ecap_pasid(e)		((e >> 40) & 0x1)
 #define ecap_pss(e)		((e >> 35) & 0x1f)
 #define ecap_eafs(e)		((e >> 34) & 0x1)

@@ -284,6 +285,7 @@ enum {
 #define QI_DEV_IOTLB_SID(sid)	((u64)((sid) & 0xffff) << 32)
 #define QI_DEV_IOTLB_QDEP(qdep)	(((qdep) & 0x1f) << 16)
 #define QI_DEV_IOTLB_ADDR(addr)	((u64)(addr) &

VTD_PAGE_MASK) +#define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xff0) << 48)) #define
QI_DEV_IOTLB_SIZE 1 #define QI_DEV_IOTLB_MAX_INVS 32

include/linux/intel-iommu.h enum { · line 314

Quoted 5 lines

include/linux/intel-iommu.h +1 -0

@@ -308,6 +310,7 @@ enum {
 #define QI_DEV_EIOTLB_PASID(p)	(((u64)p) << 32)
 #define QI_DEV_EIOTLB_SID(sid)	((u64)((sid) & 0xffff) << 16)
 #define QI_DEV_EIOTLB_QDEP(qd)	((u64)((qd) & 0x1f) << 4)
+#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) |
 ((u64)(pfsid & 0xff0) << 48))  

PFSID[15:4] are stored in Descriptor [63:52], hence it should look like:

+#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff0) << 48))

include/linux/intel-iommu.h struct device_domain_info { · line 476

Quoted 12 lines

include/linux/intel-iommu.h +0 -0

 #define QI_DEV_EIOTLB_MAX_INVS	32
 

#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)

include/linux/intel-iommu.h +1 -0

@@ -467,6 +470,7 @@ struct device_domain_info {
 	struct list_head global; /* link to global list */
 	u8 bus;			/* PCI bus number */
 	u8 devfn;		/* PCI devfn number */
+	u16 pfsid;		/* SRIOV physical function
 source ID */ u8 pasid_supported:3;
 	u8 pasid_enabled:1;
 	u8 pri_supported:1;  

Best regards,
Lu Baolu

PFSID should be used in the invalidation descriptor for flushing device IOTLBs on SRIOV VFs.

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/iommu/dmar.c        |  6 +++---
 drivers/iommu/intel-iommu.c | 16 +++++++++++++++-
 include/linux/intel-iommu.h |  5 ++---
 3 files changed, 20 insertions(+), 7 deletions(-)

drivers/iommu/dmar.c +3 -3

index 460bed4..7852678 100644
@@ -1339,8 +1339,8 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
 	qi_submit_sync(&desc, iommu);
 }
 
-void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
-			u64 addr, unsigned mask)
+void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
+			u16 qdep, u64 addr, unsigned mask)
 {
 	struct qi_desc desc;
 

@@ -1355,7 +1355,7 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
 		qdep = 0;
 
 	desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
-		   QI_DIOTLB_TYPE;
+		   QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
 
 	qi_submit_sync(&desc, iommu);
 }

drivers/iommu/intel-iommu.c +0 -0

index 4623294..732a10f 100644
@@ -1459,6 +1459,19 @@ static void iommu_enable_dev_iotlb(struct device_domain_info *info)
 		return;
 
 	pdev = to_pci_dev(info->dev);

drivers/iommu/intel-iommu.c +0 -0

 	}
 	spin_unlock_irqrestore(&device_domain_lock, flags);
 }

include/linux/intel-iommu.h +0 -0

index dfacd49..678a0f4 100644

Quoted 21 lines

(quoted diff) +0 -0

b/drivers/iommu/intel-iommu.c index 4623294..732a10f 100644

drivers/iommu/intel-iommu.c +1 -0

@@ -1459,6 +1459,19 @@ static void iommu_enable_dev_iotlb(struct
 device_domain_info *info) return;
 
 	pdev = to_pci_dev(info->dev);
+	/* For IOMMU that supports device IOTLB throttling (DIT),

we assign

drivers/iommu/intel-iommu.c +1 -0

+	 * PFSID to the invalidation desc of a VF such that IOMMU

HW can gauge

drivers/iommu/intel-iommu.c +1 -0

+	 * queue depth at PF level. If DIT is not set, PFSID will

be treated as

drivers/iommu/intel-iommu.c +7 -0

+	 * reserved, which should be set to 0.
+	 */
+	if (!ecap_dit(info->iommu->ecap))
+		info->pfsid = 0;
+	else if (pdev && pdev->is_virtfn) {
+		if (ecap_(info->iommu->ecap))
+			dev_warn(&pdev->dev, "SRIOV VF device

Quoted 1 line

IOTLB enabled without flow control\n");

I can't understand these two lines.

Isn't the condition always true? What does the error message mean?

When Shared Virtual Memory is exposed to a guest via vIOMMU, extended IOTLB invalidation may be passed down from outside IOMMU subsystems. This patch adds invalidation functions that can be used for additional translation cache types.

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/iommu/dmar.c        | 44 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/intel-iommu.h | 21 +++++++++++++++++++--
 2 files changed, 63 insertions(+), 2 deletions(-)

drivers/iommu/dmar.c +0 -0

index 7852678..0b5b052 100644

drivers/iommu/dmar.c +10 -0

+{
+	struct qi_desc desc;
+
+	desc.low = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
+		QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE;
+	desc.high = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_GL(global) |
+		QI_EIOTLB_IH(0) | QI_EIOTLB_AM(size_order);
+	qi_submit_sync(&desc, iommu);
+}
+
 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
 			u16 qdep, u64 addr, unsigned mask)
 {

drivers/iommu/dmar.c +25 -0

+	desc.high |= QI_DEV_EIOTLB_GLOB(granu);
+
+	/* If S bit is 0, we only flush a single page. If S bit is set,
+	 * The least significant zero bit indicates the size. VT-d spec
+	 * 6.5.2.6
+	 */
+	if (!size)
+		desc.high = QI_DEV_EIOTLB_ADDR(addr) & ~QI_DEV_EIOTLB_SIZE;
+	else {
+		unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size);
+
+		desc.high = QI_DEV_EIOTLB_ADDR(addr & ~mask) | QI_DEV_EIOTLB_SIZE;
+	}
+	qi_submit_sync(&desc, iommu);
+}
+
+void qi_flush_pasid(struct intel_iommu *iommu, u16 did, u64 granu, int pasid)
+{
+	struct qi_desc desc;
+
+	desc.high = 0;
+	desc.low = QI_PC_TYPE | QI_PC_DID(did) | QI_PC_GRAN(granu) | QI_PC_PASID(pasid);
+
+	qi_submit_sync(&desc, iommu);
+}
 /*
  * Disable Queued Invalidation interface.
  */

include/linux/intel-iommu.h +14 -2

index 678a0f4..5ac0c28 100644
@@ -262,6 +262,10 @@ enum {
 #define QI_PGRP_RESP_TYPE	0x9
 #define QI_PSTRM_RESP_TYPE	0xa
 
+#define QI_DID(did)		(((u64)did & 0xffff) << 16)
+#define QI_DID_MASK		GENMASK(31, 16)
+#define QI_TYPE_MASK		GENMASK(3, 0)
+
 #define QI_IEC_SELECTIVE	(((u64)1) << 4)
 #define QI_IEC_IIDEX(idx)	(((u64)(idx & 0xffff) << 32))
 #define QI_IEC_IM(m)		(((u64)(m & 0x1f) << 27))

@@ -293,8 +297,9 @@ enum {
 #define QI_PC_DID(did)		(((u64)did) << 16)
 #define QI_PC_GRAN(gran)	(((u64)gran) << 4)
 
-#define QI_PC_ALL_PASIDS	(QI_PC_TYPE | QI_PC_GRAN(0))
-#define QI_PC_PASID_SEL		(QI_PC_TYPE | QI_PC_GRAN(1))
+/* PASID cache invalidation granu */
+#define QI_PC_ALL_PASIDS	0
+#define QI_PC_PASID_SEL		1
 
 #define QI_EIOTLB_ADDR(addr)	((u64)(addr) & VTD_PAGE_MASK)
 #define QI_EIOTLB_GL(gl)	(((u64)gl) << 7)

@@ -304,6 +309,10 @@ enum {
 #define QI_EIOTLB_DID(did)	(((u64)did) << 16)
 #define QI_EIOTLB_GRAN(gran) 	(((u64)gran) << 4)
 
+/* QI Dev-IOTLB inv granu */
+#define QI_DEV_IOTLB_GRAN_ALL		1
+#define QI_DEV_IOTLB_GRAN_PASID_SEL	0
+
 #define QI_DEV_EIOTLB_ADDR(a)	((u64)(a) & VTD_PAGE_MASK)
 #define QI_DEV_EIOTLB_SIZE	(((u64)1) << 11)
 #define QI_DEV_EIOTLB_GLOB(g)	((u64)g)

@@ -332,6 +341,7 @@ enum {
 #define QI_RESP_INVALID		0x1
 #define QI_RESP_FAILURE		0xf
 
+/* QI EIOTLB inv granu */
 #define QI_GRAN_ALL_ALL			0
 #define QI_GRAN_NONG_ALL		1
 #define QI_GRAN_NONG_PASID		2

@@ -504,8 +514,15 @@ extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
 			     u8 fm, u64 type);
 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
 			  unsigned int size_order, u64 type);
+extern void qi_flush_eiotlb(struct intel_iommu *iommu, u16 did, u64 addr,
+			u32 pasid, unsigned int size_order, u64 type, bool global);

Hi,

Quoted 17 lines · Jacob Pan

When Shared Virtual Memory is exposed to a guest via vIOMMU, extended IOTLB invalidation may be passed down from outside IOMMU subsystems. This patch adds invalidation functions that can be used for additional translation cache types.

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/iommu/dmar.c        | 44

++++++++++++++++++++++++++++++++++++++++++++
include/linux/intel-iommu.h | 21 +++++++++++++++++++-- 2 files changed, 63 insertions(+), 2 deletions(-)

drivers/iommu/dmar.c +0 -0

index 7852678..0b5b052 100644

drivers/iommu/dmar.c void qi_flush_iotlb(struct intel_iommu · line 1344

Quoted 6 lines

drivers/iommu/dmar.c +2 -0

@@ -1339,6 +1339,18 @@ void qi_flush_iotlb(struct intel_iommu
 *iommu, u16 did, u64 addr, qi_submit_sync(&desc, iommu);
 }
 
+void qi_flush_eiotlb(struct intel_iommu *iommu, u16 did, u64 addr,
 u32 pasid,
+		unsigned int size_order, u64 granu, bool global)  

Alignment should match open parenthesis.

Quoted 14 lines

drivers/iommu/dmar.c +10 -0

+{
+	struct qi_desc desc;
+
+	desc.low = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
+		QI_EIOTLB_GRAN(granu) | QI_EIOTLB_TYPE;
+	desc.high = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_GL(global) |
+		QI_EIOTLB_IH(0) | QI_EIOTLB_AM(size_order);
+	qi_submit_sync(&desc, iommu);
+}
+
 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16
 pfsid, u16 qdep, u64 addr, unsigned mask)

{

drivers/iommu/dmar.c void qi_flush_dev_iotlb(struct intel_iommu · line 1377

Quoted 6 lines

drivers/iommu/dmar.c +2 -0

@@ -1360,6 +1372,38 @@ void qi_flush_dev_iotlb(struct intel_iommu
 *iommu, u16 sid, u16 pfsid, qi_submit_sync(&desc, iommu);
 }
 
+void qi_flush_dev_eiotlb(struct intel_iommu *iommu, u16 sid,
+		u32 pasid,  u16 qdep, u64 addr, unsigned size, u64
 granu)  

Ditto.

drivers/iommu/dmar.c void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, · line 1381

Quoted 6 lines

drivers/iommu/dmar.c +4 -0

+{
+	struct qi_desc desc;
+
+	desc.low = QI_DEV_EIOTLB_PASID(pasid) |

QI_DEV_EIOTLB_SID(sid) |

drivers/iommu/dmar.c +1 -0

+		QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE;  

Have you forgotten PFSID, or I missed anything here?

[...]

Best regards,
Lu Baolu

When Shared Virtual Address (SVA) is enabled for a guest OS via vIOMMU, we need to provide invalidation support at IOMMU API and driver level. This patch adds Intel VT-d specific function to implement iommu passdown invalidate API for shared virtual address.

The use case is for supporting caching structure invalidation of assigned SVM capable devices. Emulated IOMMU exposes queue invalidation capability and passes down all descriptors from the guest to the physical IOMMU.

The assumption is that guest to host device ID mapping should be resolved prior to calling IOMMU driver. Based on the device handle, host IOMMU driver can replace certain fields before submit to the invalidation queue.

Signed-off-by Liu, Yi L <yi.l.liu-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Ashok Raj <[email protected]>

Signed-off-by Jacob Pan <jacob.jun.pan-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/iommu/intel-iommu.c | 129 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)

drivers/iommu/intel-iommu.c +32 -0

index 732a10f..684bd98 100644
@@ -4973,6 +4973,134 @@ static void intel_iommu_detach_device(struct iommu_domain *domain,
 	dmar_remove_one_dev_info(to_dmar_domain(domain), dev);
 }
 
+/*
+ * 2D array for converting and sanitizing IOMMU generic TLB granularity to
+ * VT-d granularity. Invalidation is typically included in the unmap operation
+ * as a result of DMA or VFIO unmap. However, for assigned device where guest
+ * could own the first level page tables without being shadowed by QEMU. In
+ * this case there is no pass down unmap to the host IOMMU as a result of unmap
+ * in the guest. Only invalidations are trapped and passed down.
+ * In all cases, only first level TLB invalidation (request with PASID) can be
+ * passed down, therefore we do not include IOTLB granularity for request
+ * without PASID (second level).
+ *
+ * For an example, to find the VT-d granularity encoding for IOTLB
+ * type and page selective granularity within PASID:
+ * X: indexed by enum iommu_inv_type
+ * Y: indexed by enum iommu_inv_granularity
+ * [IOMMU_INV_TYPE_TLB][IOMMU_INV_GRANU_PAGE_PASID]
+ *
+ * Granu_map array indicates validity of the table. 1: valid, 0: invalid
+ *
+ */
+const static int inv_type_granu_map[IOMMU_INV_NR_TYPE][IOMMU_INV_NR_GRANU] = {
+	/* Extended dev TLBs */
+	{1, 1, 1},
+	/* Extended IOTLB */
+	{1, 1, 1},
+	/* PASID cache */
+	{1, 1, 0}
+};
+
+const static u64 inv_type_granu_table[IOMMU_INV_NR_TYPE][IOMMU_INV_NR_GRANU] = {
+	/* extended dev IOTLBs */
+	{QI_DEV_IOTLB_GRAN_ALL, QI_DEV_IOTLB_GRAN_PASID_SEL, 0},

drivers/iommu/intel-iommu.c +46 -0

+		return -EINVAL;
+
+	iommu = device_to_iommu(dev, &bus, &devfn);
+	if (!iommu)
+		return -ENODEV;
+
+	if (!dev || !dev_is_pci(dev))
+		return -ENODEV;
+
+	did = dmar_domain->iommu_did[iommu->seq_id];
+	sid = PCI_DEVID(bus, devfn);
+	ret = to_vtd_granularity(inv_info->hdr.type, inv_info->granularity,
+				&granu);
+	if (ret) {
+		pr_err("Invalid range type %d, granu %d\n", inv_info->hdr.type,
+			inv_info->granularity);
+		return ret;
+	}
+
+	spin_lock(&iommu->lock);
+	spin_lock_irqsave(&device_domain_lock, flags);
+
+	switch (inv_info->hdr.type) {
+	case IOMMU_INV_TYPE_TLB:
+		if (inv_info->size &&
+			(inv_info->addr & ((1 << (VTD_PAGE_SHIFT + inv_info->size)) - 1))) {
+			pr_err("Addr out of range, addr 0x%llx, size order %d\n",
+				inv_info->addr, inv_info->size);
+			ret = -ERANGE;
+			goto out_unlock;
+		}
+
+		qi_flush_eiotlb(iommu, did, mm_to_dma_pfn(inv_info->addr),
+				inv_info->pasid,
+				inv_info->size, granu,
+				inv_info->flags & IOMMU_INVALIDATE_GLOBAL_PAGE);
+		/**
+		 * Always flush device IOTLB if ATS is enabled since guest
+		 * vIOMMU exposes CM = 1, no device IOTLB flush will be passed
+		 * down.
+		 */
+		info = iommu_support_dev_iotlb(dmar_domain, iommu, bus, devfn);
+		if (info && info->ats_enabled) {
+			qi_flush_dev_eiotlb(iommu, sid,
+					inv_info->pasid, info->ats_qdep,
+					inv_info->addr, inv_info->size,

drivers/iommu/intel-iommu.c +9 -0

+		ret = -EINVAL;
+	}
+out_unlock:
+	spin_unlock(&iommu->lock);
+	spin_unlock_irqrestore(&device_domain_lock, flags);
+
+	return ret;
+}
+
 static int intel_iommu_map(struct iommu_domain *domain,
 			   unsigned long iova, phys_addr_t hpa,
 			   size_t size, int iommu_prot)

Quoted 43 lines

drivers/iommu/intel-iommu.c +4 -0

+	switch (inv_info->hdr.type) {
+	case IOMMU_INV_TYPE_TLB:
+		if (inv_info->size &&
+			(inv_info->addr & ((1 << (VTD_PAGE_SHIFT +

inv_info->size)) - 1))) {

(quoted diff) +1 -0

+			pr_err("Addr out of range, addr 0x%llx,

size order %d\n",

drivers/iommu/intel-iommu.c +6 -0

+				inv_info->addr, inv_info->size);
+			ret = -ERANGE;
+			goto out_unlock;
+		}
+
+		qi_flush_eiotlb(iommu, did,

mm_to_dma_pfn(inv_info->addr),

drivers/iommu/intel-iommu.c +3 -0

+				inv_info->pasid,
+				inv_info->size, granu,
+				inv_info->flags &

IOMMU_INVALIDATE_GLOBAL_PAGE);

(quoted diff) +2 -0

+		/**
+		 * Always flush device IOTLB if ATS is enabled

since guest

(quoted diff) +1 -0

+		 * vIOMMU exposes CM = 1, no device IOTLB flush

will be passed

drivers/iommu/intel-iommu.c +3 -0

+		 * down.
+		 */
+		info = iommu_support_dev_iotlb(dmar_domain, iommu,

bus, devfn);

drivers/iommu/intel-iommu.c +3 -0

+		if (info && info->ats_enabled) {
+			qi_flush_dev_eiotlb(iommu, sid,
+					inv_info->pasid,

info->ats_qdep,

(quoted diff) +1 -0

+					inv_info->addr,

inv_info->size,

drivers/iommu/intel-iommu.c +9 -0

+					granu);
+		}
+		break;
+	case IOMMU_INV_TYPE_PASID:
+		qi_flush_pasid(iommu, did, granu, inv_info->pasid);
+
+		break;
+	default:
+		dev_err(dev, "Unknown IOMMU invalidation type

%d\n",

drivers/iommu/intel-iommu.c static void intel_iommu_detach_device(struct iommu_domain *domain, · line 5094

Quoted 1 line

drivers/iommu/intel-iommu.c +1 -0

+			inv_info->hdr.type);  

There are three types of invalidation: