db820c: set clk node to be probed before relocation
Subsystems (4)
PATCH v2 1/7 db820c: set clk node to be probed before relocation
The clock and serial nodes are needed before relocation. This patch ensures that the msm-serial driver will probe and provide uart output before relocation.
---
v2: fixed alignment
arch/arm/dts/dragonboard820c-uboot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/dts/dragonboard820c-uboot.dtsi +14 -0
@@ -5,6 +5,20 @@ * (C) Copyright 2017 Jorge Ramirez-Ortiz <[email protected]> */ +/ { + soc { + u-boot,dm-pre-reloc; + + clock-controller at 300000 { + u-boot,dm-pre-reloc; + }; + + serial at 75b0000 { + u-boot,dm-pre-reloc; + }; + }; +}; + &pm8994_pon { key_vol_down { gpios = <&pm8994_pon 1 0>;
Signature · 1 line
2.17.0
PATCH v2 2/7 serial: serial_msm: fail probe if settings clocks fails
Failure to set the clocks will causes data abort exception when trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock setting failed.
---
v2: on failure, return actual return code from msm_uart_clk_init
drivers/serial/serial_msm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/serial/serial_msm.c +4 -2
@@ -181,10 +181,12 @@ static int msm_uart_clk_init(struct udevice *dev)static int msm_serial_probe (struct udevice *dev) { +int ret;struct msm_serial_data *priv =dev_get_priv (dev); -msm_uart_clk_init (dev);/* Ignore return value and hope clock was -properly initialized by earlier loaders */ + ret =msm_uart_clk_init (dev); +if (ret) +return ret;if (readl (priv->base +UARTDM_SR ) &UARTDM_SR_UART_OVERRUN )writel (UARTDM_CR_CMD_RESET_ERR , priv->base +UARTDM_CR );
Signature · 1 line
2.17.0
PATCH v2 2/7 serial: serial_msm: fail probe if settings clocks fails
Quoted 11 lines · Ramon Fried
Failure to set the clocks will causes data abort exception when trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock setting failed.Signed-off-by Ramon Fried <[email protected]>---
v2: on failure, return actual return code frommsm_uart_clk_initdrivers/serial/serial_msm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
PATCH v2 2/7 serial: serial_msm: fail probe if settings clocks fails
In reply to Ramon FriedQuoted 7 lines · Ramon Fried
Failure to set the clocks will causes data abort exception when trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock setting failed.Signed-off-by Ramon Fried <[email protected]>Reviewed-by Simon Glass <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/e380ba72/attachment.sig>
PATCH v2 3/7 serial: serial_msm: initialize uart only before relocation
In reply to Ramon FriedThe uart is already initialized prior to relocation, reinitialization after relocation is unnecessary.
---
v2: removed extra parenthesis
drivers/serial/serial_msm.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/serial/serial_msm.c +4 -0
@@ -184,6 +184,10 @@ static int msm_serial_probe(struct udevice *dev)int ret;struct msm_serial_data *priv =dev_get_priv (dev); +/* No need to reinitialize the UART after relocation */ +if (gd->flags &GD_FLG_RELOC ) +return 0 ; + ret =msm_uart_clk_init (dev);if (ret)return ret;
Signature · 1 line
2.17.0
PATCH v2 3/7 serial: serial_msm: initialize uart only before relocation
Quoted 9 lines · Ramon Fried
The uart is already initialized prior to relocation, reinitialization after relocation is unnecessary.
Signed-off-by Ramon Fried <[email protected]>---
v2: removed extra parenthesisdrivers/serial/serial_msm.c | 4 ++++ 1 file changed, 4 insertions(+)
PATCH v2 3/7 serial: serial_msm: initialize uart only before relocation
In reply to Ramon FriedQuoted 5 lines · Ramon Fried
The uart is already initialized prior to relocation, reinitialization after relocation is unnecessary.
Signed-off-by Ramon Fried <[email protected]>Reviewed-by Simon Glass <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/08b4604b/attachment.sig>
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
In reply to Ramon FriedUART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.
--- arch/arm/mach-snapdragon/clock-apq8016.c | 23 +++++++++++++------ arch/arm/mach-snapdragon/clock-apq8096.c | 4 ++-- arch/arm/mach-snapdragon/clock-snapdragon.c | 17 +++++++++++++- arch/arm/mach-snapdragon/clock-snapdragon.h | 9 ++++++-- .../include/mach/sysmap-apq8016.h | 1 + 5 files changed, 42 insertions(+), 12 deletions(-)
arch/arm/mach-snapdragon/clock-apq8016.c +16 -7
@@ -17,7 +17,6 @@/* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) -#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)static const struct bcr_regs sdc_regs[] = { {
@@ -36,11 +35,17 @@ static const struct bcr_regs sdc_regs[] = { } }; -static struct gpll0_ctrl gpll0_ctrl = { +static struct pll_vote_clk gpll0_vote_clk = { .status =GPLL0_STATUS , .status_bit =GPLL0_STATUS_ACTIVE , .ena_vote =APCS_GPLL_ENA_VOTE , - .vote_bit =APCS_GPLL_ENA_VOTE_GPLL0 , + .vote_bit =BIT (0 ), +}; + +static struct vote_clk gcc_blsp1_ahb_clk = { + .cbcr_reg =BLSP1_AHB_CBCR , + .ena_vote =APCS_CLOCK_BRANCH_ENA_VOTE , + .vote_bit =BIT (10 ), };/* SDHCI */
@@ -55,7 +60,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)/* 800Mhz/div, gpll0 */ clk_rcg_set_rate_mnd (priv->base, &sdc_regs[slot], div,0 ,0 ,CFG_CLK_SRC_GPLL0 ); -clk_enable_gpll0 (priv->base, &gpll0_ctrl); +clk_enable_gpll0 (priv->base, &gpll0_vote_clk);clk_enable_cbc (priv->base +SDCC_APPS_CBCR (slot));return rate;
@@ -72,12 +77,16 @@ static const struct bcr_regs uart2_regs = {/* UART: 115200 */ static int clk_init_uart (struct msm_clk_priv *priv) { -/* Enable iface clk */ -clk_enable_cbc (priv->base +BLSP1_AHB_CBCR ); +/* Enable AHB clock */ +clk_enable_vote_clk (priv->base, &gcc_blsp1_ahb_clk); +/* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd (priv->base, &uart2_regs,1 ,144 ,15625 ,CFG_CLK_SRC_GPLL0 ); -clk_enable_gpll0 (priv->base, &gpll0_ctrl); + +/* Vote for gpll0 clock */ +clk_enable_gpll0 (priv->base, &gpll0_vote_clk); +/* Enable core clk */ clk_enable_cbc (priv->base +BLSP1_UART2_APPS_CBCR );
arch/arm/mach-snapdragon/clock-apq8096.c +2 -2
@@ -27,7 +27,7 @@ static const struct bcr_regs sdc_regs = { .D = SDCC2_D, }; -static const struct gpll0_ctrl gpll0_ctrl = { +static const struct pll_vote_clk gpll0_vote_clk = { .status =GPLL0_STATUS , .status_bit =GPLL0_STATUS_ACTIVE , .ena_vote =APCS_GPLL_ENA_VOTE ,
@@ -41,7 +41,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)clk_enable_cbc (priv->base +SDCC2_AHB_CBCR );clk_rcg_set_rate_mnd (priv->base, &sdc_regs, div,0 ,0 ,CFG_CLK_SRC_GPLL0 ); -clk_enable_gpll0 (priv->base, &gpll0_ctrl); +clk_enable_gpll0 (priv->base, &gpll0_vote_clk);clk_enable_cbc (priv->base +SDCC2_APPS_CBCR );return rate;
arch/arm/mach-snapdragon/clock-snapdragon.c +16 -1
@@ -30,7 +30,7 @@ void clk_enable_cbc(phys_addr_t cbcr) ; } -void clk_enable_gpll0 (phys_addr_t base,const struct gpll0_ctrl *gpll0) +void clk_enable_gpll0 (phys_addr_t base,const struct pll_vote_clk *gpll0) {if (readl (base + gpll0->status) & gpll0->status_bit)return ;/* clock already enabled */
@@ -41,6 +41,21 @@ void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0) ; } +#define BRANCH_ON_VAL (0) +#define BRANCH_NOC_FSM_ON_VAL BIT(29) +#define BRANCH_CHECK_MASK GENMASK(31, 28) + +void clk_enable_vote_clk (phys_addr_t base,const struct vote_clk *vclk) +{ +u32 val; + +setbits_le32 (base + vclk->ena_vote, vclk->vote_bit); +do { + val =readl (base + vclk->cbcr_reg); + val &=BRANCH_CHECK_MASK ; + }while ((val !=BRANCH_ON_VAL ) && (val !=BRANCH_NOC_FSM_ON_VAL )); +} +#define APPS_CMD_RGCR_UPDATE BIT(0)/* Update clock command via CMD_RGCR */
arch/arm/mach-snapdragon/clock-snapdragon.h +7 -2
@@ -11,13 +11,18 @@#define CFG_CLK_SRC_GPLL0 (1 << 8)#define CFG_CLK_SRC_MASK (7 << 8) -struct gpll0_ctrl { +struct pll_vote_clk {uintptr_t status;int status_bit;uintptr_t ena_vote;int vote_bit; }; +struct vote_clk { +uintptr_t cbcr_reg; +uintptr_t ena_vote; +int vote_bit; +};struct bcr_regs {uintptr_t cfg_rcgr;uintptr_t cmd_rcgr;
@@ -30,7 +35,7 @@ struct msm_clk_priv {phys_addr_t base; }; -void clk_enable_gpll0 (phys_addr_t base,const struct gpll0_ctrl *pll0); +void clk_enable_gpll0 (phys_addr_t base,const struct pll_vote_clk *gpll0);void clk_bcr_update (phys_addr_t apps_cmd_rgcr);void clk_enable_cbc (phys_addr_t cbcr); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +1 -0
@@ -13,6 +13,7 @@/* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C)#define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)#define SDCC_BCR (n) ((n * 0x1000) + 0x41000)#define SDCC_CMD_RCGR (n) ((n * 0x1000) + 0x41004)
Signature · 1 line
2.17.0
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/295419ee/attachment.sig>
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
I think it introduces a regression but I'll let Ramon to confirm.
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 9 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>
Quoted 8 lines
Quoted 2 lines
Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours. Thanks,
Ramon.
Quoted 1 line
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 18 lines · Ramon Fried
Quoted 16 lines · Jorge Ramirez-Ortiz
Quoted 10 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
Quoted 6 lines
Quoted 1 line
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours.
Yeah, sorry guys, I didn't see anything in public about problems so I fixed up the one new warning. Please let me know if you need me to revert these or if it's an "easy" fix, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/9c15c661/attachment.sig>
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 26 lines · Tom Rini
Quoted 18 lines · Ramon Fried
Quoted 16 lines · Jorge Ramirez-Ortiz
Quoted 10 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
Quoted 6 lines
Quoted 1 line
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours.
Quoted 3 lines
Yeah, sorry guys, I didn't see anything in public about problems so I fixed up the one new warning. Please let me know if you need me to revert these or if it's an "easy" fix, thanks!
Sure.
I'll keep you posted. but without any doubt, the following patch is necessary to make it work:
https://patchwork.ozlabs.org/patch/921407/
Can you please merge it as well ?
Quoted 3 lines
--
Tom
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 27 lines · Ramon Fried
Quoted 26 lines · Tom Rini
Quoted 24 lines · Ramon Fried
Quoted 9 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Quoted 8 lines
Quoted 2 lines
Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours.
Quoted 8 lines
Quoted 3 lines
Yeah, sorry guys, I didn't see anything in public about problems so I fixed up the one new warning. Please let me know if you need me to revert these or if it's an "easy" fix, thanks!
Sure.
I'll keep you posted. but without any doubt, the following patch is necessary to make it work:
https://patchwork.ozlabs.org/patch/921407/
Can you please merge it as well ?
0x0800 is still pretty small. We're talking about (and oops, I think I need to for v2018.07..) bump it to 0x2000 for all TI platforms. Can you v2 doing that size if it works for you (it ought...) and as a default VAL if ARCH_SNAPDRAGON ? Thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/f29c47ba/attachment.sig>
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 37 lines · Tom Rini
Quoted 27 lines · Ramon Fried
Quoted 26 lines · Tom Rini
Quoted 24 lines · Ramon Fried
Quoted 9 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Quoted 8 lines
Quoted 2 lines
Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours.Quoted 8 lines
Quoted 3 lines
Yeah, sorry guys, I didn't see anything in public about problems so I fixed up the one new warning. Please let me know if you need me to revert these or if it's an "easy" fix, thanks!
Sure.
I'll keep you posted. but without any doubt, the following patch is necessary to make it work:
https://patchwork.ozlabs.org/patch/921407/
Can you please merge it as well ?
Quoted 4 lines
0x0800is still pretty small. We're talking about (and oops, I think I need to for v2018.07..) bump it to0x2000for all TI platforms. Can you v2 doing that size if it works for you (it ought...) and as a default VAL ifARCH_SNAPDRAGON? Thanks!
Sure. I'll test and resend.
Quoted 3 lines
--
Tom
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
In reply to Ramon FriedQuoted 18 lines · Ramon Fried
Quoted 16 lines · Jorge Ramirez-Ortiz
Quoted 10 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
Quoted 9 lines
Quoted 1 line
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours. Thanks,
Ramon.Quoted 1 line
I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master to see if it's working ?
Thanks.
Ramon.
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 24 lines · Ramon Fried
Quoted 15 lines · Ramon Fried
Quoted 13 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
Quoted 8 lines
Quoted 1 line
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours. Thanks,
Ramon.
Quoted 7 lines
I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master to see if it's working ?
so just pull your master branch again and retest?
Quoted 2 lines
Thanks.
Ramon.
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 42 lines · Jorge Ramirez-Ortiz
Quoted 32 lines · Ramon Fried
Quoted 21 lines · Ramon Fried
Quoted 10 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Quoted 7 lines
Quoted 2 lines
Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
I think it introduces a regression but I'll let Ramon to confirm.
Quoted 7 lines
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours. Thanks,
Ramon.Quoted 7 lines
I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master to see if it's working ?
Quoted 1 line
so just pull your master branch again and retest?
not mine. upstream master.
Quoted 6 lines
Quoted 4 lines
Thanks.
Ramon.
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 36 lines · Ramon Fried
Quoted 34 lines · Jorge Ramirez-Ortiz
Quoted 32 lines · Ramon Fried
Quoted 15 lines · Ramon Fried
Quoted 13 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
Quoted 8 lines
Quoted 1 line
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours. Thanks,
Ramon.I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master to see if it's working ?
Quoted 2 lines
Quoted 1 line
so just pull your master branch again and retest?
not mine. upstream master.
2 days ago ffada23 db820c: set clk node to be probed before relocation Ramon Fr..[Tom Rini]
2 days ago 0ed34aa Remove CONFIG_MVGBE from config_whitelist.txt Chris Pa..[Tom Rini]
2 days ago 5ce9aca PCI: Document
pciauto_region_allocate() Tuomas T..[Tom Rini] 2 days ago d71975a PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit.. Tuomas T..[Tom Rini]
2 days ago ed12a89 PCI: Add newlines to debug prints in pci_auto_common.c Tuomas T..[Tom Rini]
the one on top is the last commit that works on the 820 from the current uboot master branch.
Quoted 4 lines
Quoted 4 lines
Quoted 3 lines
Thanks.
Ramon.
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 63 lines · Jorge Ramirez-Ortiz
Quoted 46 lines · Ramon Fried
Quoted 43 lines · Jorge Ramirez-Ortiz
Quoted 39 lines · Ramon Fried
Quoted 21 lines · Ramon Fried
Quoted 10 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Quoted 7 lines
Quoted 2 lines
Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
I think it introduces a regression but I'll let Ramon to confirm.
Quoted 7 lines
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours. Thanks,
Ramon.I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master to see if it's working ?Quoted 3 lines
Quoted 1 line
so just pull your master branch again and retest?
not mine. upstream master.
2 days ago ffada23 db820c: set clk node to be probed before relocation Ramon Fr..[Tom Rini]
2 days ago 0ed34aa RemoveCONFIG_MVGBEfrom config_whitelist.txt Chris Pa..[Tom Rini]
2 days ago 5ce9aca PCI: Documentpciauto_region_allocate()Tuomas T..[Tom Rini]
2 days ago d71975a PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit.. Tuomas T..[Tom Rini]
2 days ago ed12a89 PCI: Add newlines to debug prints inpci_auto_common.cTuomas T..[Tom Rini]
Quoted 2 lines
the one on top is the last commit that works on the 820 from the current uboot master branch.
Thanks Jorge.
I see where the problem is. there's no clock defintions in 820 device tree, so msm_uart_clk_init() fails. I'll add dummy definitions meanwhile and after I'll finish
with 410, I'll work on the correct clock values for 820. nevertheless the UART will work as
LK already initalizes it with the right values.
expect a fix patch shortly.
Thanks,
Ramon.
Quoted 7 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines
Thanks.
Ramon.
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 76 lines · Ramon Fried
Quoted 63 lines · Jorge Ramirez-Ortiz
Quoted 46 lines · Ramon Fried
Quoted 43 lines · Jorge Ramirez-Ortiz
Quoted 39 lines · Ramon Fried
Quoted 21 lines · Ramon Fried
Quoted 10 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Quoted 7 lines
Quoted 2 lines
Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
I think it introduces a regression but I'll let Ramon to confirm.
Quoted 7 lines
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours. Thanks,
Ramon.I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master to see if it's working ?Quoted 3 lines
Quoted 1 line
so just pull your master branch again and retest?
not mine. upstream master.
2 days ago ffada23 db820c: set clk node to be probed before relocation Ramon Fr..[Tom Rini]
2 days ago 0ed34aa RemoveCONFIG_MVGBEfrom config_whitelist.txt Chris Pa..[Tom Rini]
2 days ago 5ce9aca PCI: Documentpciauto_region_allocate()Tuomas T..[Tom Rini]
2 days ago d71975a PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit.. Tuomas T..[Tom Rini]
2 days ago ed12a89 PCI: Add newlines to debug prints inpci_auto_common.cTuomas T..[Tom Rini]Quoted 2 lines
the one on top is the last commit that works on the 820 from the current uboot master branch.
Thanks Jorge.
I see where the problem is. there's no clock defintions in 820 device tree, somsm_uart_clk_init()fails. I'll add dummy definitions meanwhile and after I'll finish
with 410, I'll work on the correct clock values for 820. nevertheless the UART will work as
LK already initalizes it with the right values.
expect a fix patch shortly.
Quoted 2 lines
Thanks,
Ramon.
Jorge, I just sent you a fix. can you test it and if it works I'll push it upstream.
Thanks ! and sorry for the trouble...
Quoted 7 lines
Quoted 7 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines
Thanks.
Ramon.
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 65 lines · Ramon Fried
Quoted 64 lines · Ramon Fried
Quoted 51 lines · Jorge Ramirez-Ortiz
Quoted 36 lines · Ramon Fried
Quoted 34 lines · Jorge Ramirez-Ortiz
Quoted 32 lines · Ramon Fried
Quoted 15 lines · Ramon Fried
Quoted 13 lines · Jorge Ramirez-Ortiz
Quoted 8 lines · Tom Rini
Quoted 4 lines · Ramon Fried
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.Signed-off-by Ramon Fried <[email protected]>Applied to u-boot/master, thanks!
Ramon, did you re-test this one on the 820 as we discussed? Sorry Tom, when I tested this on Friday it broke my 820 (I should have reported it to the ML).
Quoted 8 lines
Quoted 1 line
I think it introduces a regression but I'll let Ramon to confirm.
Hi.
It's funny, I'm debugging it now. don't have any conclusions yet but I was under the assumption that it won't get merged as it was missing Reviewed-by.
Let me get back to you on these one in couple of hours. Thanks,
Ramon.I just toasted my 820 board...:(
I can only get a replacement by Thursday.
I can't find any explanation why the 820 should be affected, as the clock configuration for it is empty.
and it's pre-initalized by the uart.
Jorge, you previously tested from my branch, care to test from master to see if it's working ?Quoted 2 lines
Quoted 1 line
so just pull your master branch again and retest?
not mine. upstream master.
2 days ago ffada23 db820c: set clk node to be probed before relocation Ramon Fr..[Tom Rini]
2 days ago 0ed34aa RemoveCONFIG_MVGBEfrom config_whitelist.txt Chris Pa..[Tom Rini]
2 days ago 5ce9aca PCI: Documentpciauto_region_allocate()Tuomas T..[Tom Rini]
2 days ago d71975a PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit.. Tuomas T..[Tom Rini]
2 days ago ed12a89 PCI: Add newlines to debug prints inpci_auto_common.cTuomas T..[Tom Rini]Quoted 2 lines
the one on top is the last commit that works on the 820 from the current uboot master branch.
Thanks Jorge.
I see where the problem is. there's no clock defintions in 820 device tree, somsm_uart_clk_init()fails. I'll add dummy definitions meanwhile and after I'll finish
with 410, I'll work on the correct clock values for 820. nevertheless the UART will work as
LK already initalizes it with the right values.
expect a fix patch shortly.
Quoted 4 lines
Quoted 2 lines
Thanks,
Ramon.Jorge, I just sent you a fix. can you test it and if it works I'll push it upstream.
yes I can see the console now so that fix is good.
however there must be some other regression lurking because the system wont boot a kernel from the SD card
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 7 lines · Jorge Ramirez-Ortiz
Quoted 2 lines
Jorge, I just sent you a fix. can you test it and if it works I'll push it upstream.
yes I can see the console now so that fix is good.
however there must be some other regression lurking because the system wont boot a kernel from the SD card
sorry forgot the trace.
I think you might have fixed this one as well Ramon (I remember you mentioning it in some other thread?)
U-Boot 2018.05-00430-g5ce9aca (May 28 2018 - 23:09:02) [15/592] Qualcomm-DragonBoard 820C
DRAM: 3 GiB
PSCI: v1.0
MMC: sdhci at 74a4900: 0
In: serial at 75b0000
Out: serial at 75b0000
Err: serial at 75b0000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
Card did not respond to voltage select! <---------------
PATCH v2 4/7 mach-snapdragon: Fix UART clock flow
Quoted 11 lines · Jorge Ramirez-Ortiz
On 05/28/2018 11:07 PM, Jorge Ramirez-Ortiz wrote:
Jorge, I just sent you a fix. can you test it and if it works I'll push it upstream.
yes I can see the console now so that fix is good.
however there must be some other regression lurking because the system wont boot a kernel from the SD card
Sorry, I don't recall seeing this ever, perhaps the regression is caused by another patch ?
are you sure it's from the latest uart fixes ? can you bisect ? Thanks,
Ramon.
Quoted 18 lines
sorry forgot the trace.
I think you might have fixed this one as well Ramon (I remember you mentioning it in some other thread?)U-Boot 2018.05-00430-g5ce9aca (May 28 2018 - 23:09:02) [15/592]
Qualcomm-DragonBoard 820CDRAM: 3 GiB PSCI: v1.0 MMC: sdhci at 74a4900: 0 In: serial at 75b0000 Out: serial at 75b0000 Err: serial at 75b0000 Net: Net Initialization SkippedNo ethernet found.
Hit any key to stop autoboot: 0
Card did not respond to voltage select! <---------------
PATCH v2 5/7 mach-snapdragon: Introduce pinctrl driver
In reply to Ramon FriedThis patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is generic and 8096 can be added easily.
Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet).
---
v2: * restructred the code to be more generic
* Reduced pin table size by snprintf on runtime as suggested by Simon.
arch/arm/mach-snapdragon/Makefile | 2 + arch/arm/mach-snapdragon/pinctrl-apq8016.c | 62 +++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 128 ++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 29 ++++ configs/dragonboard410c_defconfig | 5 + .../dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 +++ 6 files changed, 248 insertions(+) create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h
arch/arm/mach-snapdragon/Makefile +2 -0
@@ -6,4 +6,6 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o obj-y += clock-snapdragon.o
arch/arm/mach-snapdragon/pinctrl-apq8016.c new file +62 -0
62 lines not on this page · raw message
arch/arm/mach-snapdragon/pinctrl-snapdragon.c new file +128 -0
128 lines not on this page · raw message
arch/arm/mach-snapdragon/pinctrl-snapdragon.h new file +30 -0
@@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* Qualcomm Pin control +* +* (C) Copyright 2018 Ramon Fried <[email protected]> +* +*/ +#ifndef _PINCTRL_SNAPDRAGON_H +#define _PINCTRL_SNAPDRAGON_H + +#include <common.h> + +struct msm_pinctrl_data { +int pin_count; +int functions_count; +const char *(*get_function_name)(struct udevice *dev, +unsigned int selector); +unsigned int (*get_function_mux)(unsigned int selector); +const char *(*get_pin_name)(struct udevice *dev, +unsigned int selector); +}; + +struct pinctrl_function { +const char *name; +int val; +}; + +extern struct msm_pinctrl_data apq8016_data; + +#endif
configs/dragonboard410c_defconfig +5 -0
@@ -45,3 +45,8 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_FULL=y +CONFIG_PINCTRL_GENERIC=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y
include/dt-bindings/pinctrl/pinctrl-snapdragon.h new file +22 -0
@@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* +* This header provides constants for Qualcomm Snapdragon pinctrl bindings. +* +* (C) Copyright 2018 Ramon Fried <[email protected]> +* +*/ + +#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H +#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H + +/* GPIO Drive Strength */ +#define DRIVE_STRENGTH_2MA 0 +#define DRIVE_STRENGTH_4MA 1 +#define DRIVE_STRENGTH_6MA 2 +#define DRIVE_STRENGTH_8MA 3 +#define DRIVE_STRENGTH_10MA 4 +#define DRIVE_STRENGTH_12MA 5 +#define DRIVE_STRENGTH_14MA 6 +#define DRIVE_STRENGTH_16MA 7 + +#endif
Signature · 1 line
2.17.0
PATCH v2 5/7 mach-snapdragon: Introduce pinctrl driver
Quoted 14 lines · Ramon Fried
This patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is generic and 8096 can be added easily.Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet).
Signed-off-by Ramon Fried <[email protected]>---
v2: * restructred the code to be more generic
* Reduced pin table size by snprintf on runtime as suggested by Simon.
Quoted 11 lines
arch/arm/mach-snapdragon/Makefile | 2 + arch/arm/mach-snapdragon/pinctrl-apq8016.c | 62 +++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 128 ++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 29 ++++ configs/dragonboard410c_defconfig | 5 + .../dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 +++ 6 files changed, 248 insertions(+) create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h
PATCH v2 5/7 mach-snapdragon: Introduce pinctrl driver
In reply to Ramon FriedQuoted 10 lines · Ramon Fried
This patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is generic and 8096 can be added easily.Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet).
Signed-off-by Ramon Fried <[email protected]>Reviewed-by Simon Glass <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/df7bf24f/attachment.sig>
PATCH v2 6/7 db410: added pinctrl node and serial bindings
In reply to Ramon FriedAdded TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.
--- arch/arm/dts/dragonboard410c.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/dts/dragonboard410c.dts +14 -0
@@ -8,6 +8,7 @@ /dts-v1/; #include "skeleton64.dtsi" +#include <dt-bindings/pinctrl/pinctrl-snapdragon.h> / { model = "Qualcomm Technologies, Inc. Dragonboard 410c";
@@ -38,6 +39,17 @@ ranges = <0x0 0x0 0x0 0xffffffff>; compatible = "simple-bus"; + pinctrl: qcom,tlmm at 1000000 { + compatible = "qcom,tlmm-apq8016"; + reg = <0x1000000 0x400000>; + + blsp1_uart: uart { + function = "blsp1_uart"; + pins = "GPIO_4", "GPIO_5"; + drive-strength = <DRIVE_STRENGTH_8MA>; + bias-disable; + }; + }; clkc: qcom,gcc at 1800000 { compatible = "qcom,gcc-apq8016"; reg = <0x1800000 0x80000>;
@@ -49,6 +61,8 @@ compatible = "qcom,msm-uartdm-v1.4"; reg = <0x78b0000 0x200>; clock = <&clkc 4>; + pinctrl-names = "uart"; + pinctrl-0 = <&blsp1_uart>; }; soc_gpios: pinctrl at 1000000 {
Signature · 1 line
2.17.0
PATCH v2 6/7 db410: added pinctrl node and serial bindings
Quoted 4 lines · Ramon Fried
Added TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.Signed-off-by Ramon Fried <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/f1cc29f3/attachment.sig>
PATCH v2 7/7 serial: serial_msm: added pinmux & config
In reply to Ramon FriedSerial port configuration was missing from previous implementation. It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.
--- drivers/serial/serial_msm.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-)
drivers/serial/serial_msm.c +18 -6
@@ -16,6 +16,7 @@#include <watchdog.h> #include <asm/io.h> #include <linux/compiler.h> +#include <dm/pinctrl.h> /* Serial registers - this driver works in uartdm mode*/
@@ -25,6 +26,9 @@#define UARTDM_RXFS 0x50/* RX channel status register */ #define UARTDM_RXFS_BUF_SHIFT 0x7/* Number of bytes in the packing buffer */ #define UARTDM_RXFS_BUF_MASK 0x7 +#define UARTDM_MR1 0x00 +#define UARTDM_MR2 0x04 +#define UARTDM_CSR 0xA0#define UARTDM_SR 0xA4/* Status register */ #define UARTDM_SR_RX_READY (1 << 0)/* Word is the receiver FIFO */
@@ -45,6 +49,10 @@#define UARTDM_TF 0x100/* UART Transmit FIFO register */ #define UARTDM_RF 0x140/* UART Receive FIFO register */ +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20DECLARE_GLOBAL_DATA_PTR ;
@@ -179,6 +187,14 @@ static int msm_uart_clk_init(struct udevice *dev)return 0 ; } +static void uart_dm_init (struct msm_serial_data *priv) +{ +writel (UART_DM_CLK_RX_TX_BIT_RATE , priv->base +UARTDM_CSR ); +writel (0x0 , priv->base +UARTDM_MR1 ); +writel (MSM_BOOT_UART_DM_8_N_1_MODE , priv->base +UARTDM_MR2 ); +writel (MSM_BOOT_UART_DM_CMD_RESET_RX , priv->base +UARTDM_CR ); +writel (MSM_BOOT_UART_DM_CMD_RESET_TX , priv->base +UARTDM_CR ); +}static int msm_serial_probe (struct udevice *dev) {int ret;
@@ -192,12 +208,8 @@ static int msm_serial_probe(struct udevice *dev)if (ret)return ret; -if (readl (priv->base +UARTDM_SR ) &UARTDM_SR_UART_OVERRUN ) -writel (UARTDM_CR_CMD_RESET_ERR , priv->base +UARTDM_CR ); - -writel (0 , priv->base +UARTDM_IMR ); -writel (UARTDM_CR_CMD_STALE_EVENT_DISABLE , priv->base +UARTDM_CR ); -msm_serial_fetch (dev); +pinctrl_select_state (dev,"uart" ); +uart_dm_init (priv);return 0 ; }
Signature · 1 line
2.17.0
PATCH v2 7/7 serial: serial_msm: added pinmux & config
Quoted 6 lines · Ramon Fried
Serial port configuration was missing from previous implementation. It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.Signed-off-by Ramon Fried <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/ac6afc83/attachment.sig>
PATCH v2 1/7 db820c: set clk node to be probed before relocation
In reply to Ramon FriedQuoted 9 lines · Ramon Fried
The clock and serial nodes are needed before relocation. This patch ensures that the msm-serial driver will probe and provide uart output before relocation.
Signed-off-by Ramon Fried <[email protected]>---
v2: fixed alignmentarch/arm/dts/dragonboard820c-uboot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
PATCH v2 1/7 db820c: set clk node to be probed before relocation
In reply to Ramon FriedQuoted 6 lines · Ramon Fried
The clock and serial nodes are needed before relocation. This patch ensures that the msm-serial driver will probe and provide uart output before relocation.
Signed-off-by Ramon Fried <[email protected]>Reviewed-by Simon Glass <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180528/6a761cbd/attachment.sig>