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SSB Fix #1

PATCH In review [email protected] 2 participants 2 messages May 18, 2018 x86

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PATCH 1/2 SSB Fix #1

The "336996 Speculative Execution Side Channel Mitigations" from May defines this as SSB_NO, hence lets sync-up.

Signed-off-by Konrad Rzeszutek Wilk <[email protected]>
---
 arch/x86/include/asm/msr-index.h | 2 +-
 arch/x86/kernel/cpu/common.c     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/x86/include/asm/msr-index.h +1 -1
index 562414d5b834..fda2114197b3 100644
@@ -70,7 +70,7 @@
 #define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
 #define ARCH_CAP_RDCL_NO		(1 << 0)   /* Not susceptible to Meltdown */
 #define ARCH_CAP_IBRS_ALL		(1 << 1)   /* Enhanced IBRS support */
-#define ARCH_CAP_SSBD_NO		(1 << 4)   /*
+#define ARCH_CAP_SSB_NO			(1 << 4)   /*
 						    * Not susceptible to Speculative Store Bypass
 						    * attack, so no Speculative Store Bypass
 						    * control required.
arch/x86/kernel/cpu/common.c +1 -1
index 68282514c025..9cc8cca21b39 100644
@@ -973,7 +973,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
 		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
 
 	if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
-	   !(ia32_cap & ARCH_CAP_SSBD_NO))
+	   !(ia32_cap & ARCH_CAP_SSB_NO))
 		setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
 
 	if (x86_match_cpu(cpu_no_speculation))
Signature · 1 line
2.14.3
#1 lore raw
Quoted 4 lines · speck for konrad.wilk_at_oracle.com

x86/bugs: s/SSBD_NO/SSB_NO/

The "336996 Speculative Execution Side Channel Mitigations" from May defines this as SSB_NO, hence lets sync-up.

Applied and pushed out to the git repository.