Correct wlcore irqs for PM improvments for omap4 boards

Hi all,

Looks like we can get omap4 devices to do some PM with mainline kernel mostly with just few dts tweaks. Mostly we just try to remove any GPIO level interrupts and debounce clocks. But let's fix the wlcore irq for all the boards as we know for sure it should be a level interrupt.

These changes allow pandaboard-es and duovero parlor to enter core retention during idle, and droid4 to enter per retention during idle.

To have the devices enter idle, the UARTs need to be idled, and USB related modules need to be unloaded or unbound. Additionally pandaboard-es somehow needs also rmmod ti_soc_thermal which I don't quite understand.

On droid4, GPIO bank 1 needs to be somehow reset after init to not block core retention. I also don't quite understand why this is, maybe because of kexec booting?

For dealing with GPIO level interrupts, we're missing some GPIO PM runtime patches that will be posted later after some more testing.

Regards,

Tony

Tony Lindgren (4):
ARM: OMAP2+: Make sure LOGICRETSTATE bits are not cleared
ARM: dts: Fix omap l4per idling with wlcore edge sensitive interrupt
ARM: dts: Configure duovero for to allow core retention during idle
omap4-droid4: Use software debounce for gpio-keys

 arch/arm/boot/dts/am335x-baltos.dtsi              |  2 +-
 arch/arm/boot/dts/am335x-evm.dts                  |  2 +-
 arch/arm/boot/dts/am335x-evmsk.dts                |  2 +-
 arch/arm/boot/dts/am437x-gp-evm.dts               |  2 +-
 arch/arm/boot/dts/logicpd-som-lv.dtsi             |  2 +-
 arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts |  2 +-
 arch/arm/boot/dts/omap3-cm-t3517.dts              |  2 +-
 arch/arm/boot/dts/omap3-cm-t3730.dts              |  2 +-
 arch/arm/boot/dts/omap3-evm-common.dtsi           |  2 +-
 arch/arm/boot/dts/omap3-igep0020-rev-f.dts        |  2 +-
 arch/arm/boot/dts/omap3-igep0030-rev-g.dts        |  2 +-
 arch/arm/boot/dts/omap3-zoom3.dts                 |  2 +-
 arch/arm/boot/dts/omap4-droid4-xt894.dts          |  5 +++--
 arch/arm/boot/dts/omap4-duovero-parlor.dts        |  3 ++-
 arch/arm/boot/dts/omap4-duovero.dtsi              |  1 +
 arch/arm/boot/dts/omap4-panda-common.dtsi         |  2 +-
 arch/arm/boot/dts/omap4-sdp.dts                   |  2 +-
 arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi    |  2 +-
 arch/arm/boot/dts/omap5-board-common.dtsi         |  2 +-
 arch/arm/mach-omap2/pm44xx.c                      | 13 +++++++++++++
 20 files changed, 35 insertions(+), 19 deletions(-)

2.17.0

We may have LOGICRETSTATE cleared by the bootloader or kexec boot.

Currently this means we will see lost GPIO interrupts at least for network interfaces such as wlcore and smsc911x if PER hits retention.

Let's fix the issue by making sure LOGICRETSTATE is set. Once we have GPIOs working with wakeirqs then we should be able to clear it.

---
 arch/arm/mach-omap2/pm44xx.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

@@ -131,6 +131,19 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 		return 0;
 	}
 
+	/*
+	 * Bootloader or kexec boot may have LOGICRETSTATE cleared
+	 * for some domains. This is the case when kexec booting from
+	 * Android kernels that support off mode for example.
+	 * Make sure it's set at least for core and per, otherwise
+	 * we currently will see lost GPIO interrupts for wlcore and
+	 * smsc911x at least if per hits retention during idle.
+	 */
+	if (!strncmp(pwrdm->name, "core", 4) ||
+	    !strncmp(pwrdm->name, "l4per", 5) ||
+	    !strncmp(pwrdm->name, "wkup", 4))
+		pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET);
+
 	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 	if (!pwrst)
 		return -ENOMEM;

2.17.0

The wl1835mod.pdf data sheet says this pretty clearly for WL_IRQ line:

"WLAN SDIO out-of-band interrupt line. Set to rising edge (active high) by default."

And it seems this interrupt can be optionally configured to use falling edge too since commit bd763482c82e ("wl18xx: wlan_irq: support platform dependent interrupt types").

On omaps, if the wlcore interrupt is configured as level instead of edge, L4PER will stop doing hardware based idling after ifconfig wlan0 down is done and the WL_EN line is pulled down.

The symptoms show up with L4PER status registers no longer showing the IDLEST bits as 2 but as 0 for all the active GPIO banks and for L4PER_CLKCTRL. Also the l4per_pwrdm RET count stops increasing in the /sys/kernel/debug/pm_debug/count.

I'm guessing wlcore was at some point configured to use level interrupts because of edge handling issues in gpio-omap. However, with the recent fixes to gpio-omap the edge interrupts seem to be working just fine.

Let's fix the issue for all omap boards with wlcore interrupt set as level.

---
 arch/arm/boot/dts/am335x-baltos.dtsi              | 2 +-
 arch/arm/boot/dts/am335x-evm.dts                  | 2 +-
 arch/arm/boot/dts/am335x-evmsk.dts                | 2 +-
 arch/arm/boot/dts/am437x-gp-evm.dts               | 2 +-
 arch/arm/boot/dts/logicpd-som-lv.dtsi             | 2 +-
 arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts | 2 +-
 arch/arm/boot/dts/omap3-cm-t3517.dts              | 2 +-
 arch/arm/boot/dts/omap3-cm-t3730.dts              | 2 +-
 arch/arm/boot/dts/omap3-evm-common.dtsi           | 2 +-
 arch/arm/boot/dts/omap3-igep0020-rev-f.dts        | 2 +-
 arch/arm/boot/dts/omap3-igep0030-rev-g.dts        | 2 +-
 arch/arm/boot/dts/omap3-zoom3.dts                 | 2 +-
 arch/arm/boot/dts/omap4-droid4-xt894.dts          | 2 +-
 arch/arm/boot/dts/omap4-panda-common.dtsi         | 2 +-
 arch/arm/boot/dts/omap4-sdp.dts                   | 2 +-
 arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi    | 2 +-
 arch/arm/boot/dts/omap5-board-common.dtsi         | 2 +-
 17 files changed, 17 insertions(+), 17 deletions(-)

@@ -396,7 +396,7 @@
 		compatible = "ti,wl1835";
 		reg = <2>;
 		interrupt-parent = <&gpio3>;
-		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <7 IRQ_TYPE_EDGE_RISING>;
 	};
 };
 

@@ -771,7 +771,7 @@
 		compatible = "ti,wl1835";
 		reg = <2>;
 		interrupt-parent = <&gpio3>;
-		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 	};
 };
 

@@ -682,7 +682,7 @@
 		compatible = "ti,wl1271";
 		reg = <2>;
 		interrupt-parent = <&gpio0>;
-		interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
+		interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */
 		ref-clock-frequency = <38400000>;
 	};
 };

@@ -790,7 +790,7 @@
 		compatible = "ti,wl1835";
 		reg = <2>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <23 IRQ_TYPE_EDGE_RISING>;
 	};
 };
 

@@ -113,7 +113,7 @@
 		compatible = "ti,wl1273";
 		reg = <2>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */
+		interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */
 		ref-clock-frequency = <26000000>;
 	};
 };

@@ -48,7 +48,7 @@
 		compatible = "ti,wl1283";
 		reg = <2>;
 		interrupt-parent = <&gpio5>;
-		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */
+		interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */
 		ref-clock-frequency = <26000000>;
 		tcxo-clock-frequency = <26000000>;
 	};

@@ -141,7 +141,7 @@
 		compatible = "ti,wl1271";
 		reg = <2>;
 		interrupt-parent = <&gpio5>;
-		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 145 */
+		interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 145 */
 		ref-clock-frequency = <38400000>;
 	};
 };

@@ -81,7 +81,7 @@
 		compatible = "ti,wl1271";
 		reg = <2>;
 		interrupt-parent = <&gpio5>;
-		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */
+		interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */
 		ref-clock-frequency = <38400000>;
 	};
 };

@@ -133,7 +133,7 @@
 		compatible = "ti,wl1271";
 		reg = <2>;
 		interrupt-parent = <&gpio5>;
-		interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */
+		interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 149 */
 		ref-clock-frequency = <38400000>;
 	};
 };

@@ -49,6 +49,6 @@
 		compatible = "ti,wl1835";
 		reg = <2>;
 		interrupt-parent = <&gpio6>;
-		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 177 */
+		interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */
 	};
 };

@@ -71,6 +71,6 @@
 		compatible = "ti,wl1835";
 		reg = <2>;
 		interrupt-parent = <&gpio5>;
-		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */
+		interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */
 	};
 };

@@ -202,7 +202,7 @@
 		compatible = "ti,wl1271";
 		reg = <2>;
 		interrupt-parent = <&gpio6>;
-		interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */
+		interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */
 		ref-clock-frequency = <26000000>;
 	};
 };

@@ -372,7 +372,7 @@
 		compatible = "ti,wl1285", "ti,wl1283";
 		reg = <2>;
 		interrupt-parent = <&gpio4>;
-		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */
+		interrupts = <4 IRQ_TYPE_EDGE_RISING>; /* gpio100 */
 		ref-clock-frequency = <26000000>;
 		tcxo-clock-frequency = <26000000>;
 	};

@@ -464,7 +464,7 @@
 		compatible = "ti,wl1271";
 		reg = <2>;
 		interrupt-parent = <&gpio2>;
-		interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
+		interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */
 		ref-clock-frequency = <38400000>;
 	};
 };

@@ -493,7 +493,7 @@
 		compatible = "ti,wl1281";
 		reg = <2>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
+		interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */
 		ref-clock-frequency = <26000000>;
 		tcxo-clock-frequency = <26000000>;
 	};

@@ -72,7 +72,7 @@
 		compatible = "ti,wl1271";
 		reg = <2>;
 		interrupt-parent = <&gpio2>;
-		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
+		interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */
 		ref-clock-frequency = <38400000>;
 	};
 };

@@ -364,7 +364,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&wlcore_irq_pin>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;	/* gpio 14 */
+		interrupts = <14 IRQ_TYPE_EDGE_RISING>;	/* gpio 14 */
 		ref-clock-frequency = <26000000>;
 	};
 };

2.17.0

By reconfiguring few GPIOs in the dts file we can make duovero parlor hit retention during idle:

1. Let's a larger debounce value for gpio-keys

This will then make gpio-keys use software debounce and the GPIO debounce clock is not enabled.

2. Let's allow WLAN suspend for mwifiex

This can be done just by adding keep-power-in-suspend.

3. Let's reconfigure smsc911x driver to use GPIO edge interrupt

This will allow using NFSroot while the system idles, and the kernel has quite a few dts files with "smsc,lan9115" compatible using edge interrupts.

Then to have the system hit core retention during idle, the UARTs needs to be idled and USB modules need to be unloaded or unbound.

---
 arch/arm/boot/dts/omap4-duovero-parlor.dts | 3 ++-
 arch/arm/boot/dts/omap4-duovero.dtsi       | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

@@ -36,6 +36,7 @@
 			label = "button0";
 			linux,code = <BTN_0>;
 			gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;	/* gpio_121 */
+			debounce-interval = <10>;
 			wakeup-source;
 		};
 	};

@@ -140,7 +141,7 @@
 	ethernet at gpmc {
 		reg = <5 0 0xff>;
 		interrupt-parent = <&gpio2>;
-		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;		/* gpio_44 */
+		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;	/* gpio_44 */
 
 		phy-mode = "mii";
 

@@ -248,6 +248,7 @@
 	ti,bus-width = <4>;
 	ti,non-removable;
 	cap-power-off-card;
+	keep-power-in-suspend;
 };
 
 &twl_usb_comparator {

2.17.0

The default value of 5ms will use GPIO hardware based debounce clocks that will keep L4PER from idling consuming about extra 30mW.

Use a value of 10ms that is above the hardware debounce maximum of 7.95ms forcing software based debouncing.

This allows droid4 to enter PER retention during idle as long as UARTs are idled and USB modules unloaded or unbound.

Note that there seems to be a pending issue with having droid 4 enter core retention during idle where GPIO bank 1 needs to be reset late after init for some reason to not block core retention. In addition to that, we are also missing GPIO related PM runtime calls for omap4 that will be posted separately.

---
 arch/arm/boot/dts/omap4-droid4-xt894.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

@@ -128,6 +128,7 @@
 			gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */
 			linux,code = <KEY_VOLUMEDOWN>;
 			linux,can-disable;
+			debounce-interval = <10>;
 		};
 
 		slider {

@@ -136,7 +137,7 @@
 			linux,input-type = <EV_SW>;
 			linux,code = <SW_KEYPAD_SLIDE>;
 			linux,can-disable;
-
+			debounce-interval = <10>;
 		};
 	};
 

2.17.0

Hi!

Thanks, will take a look.

BTW, did you notice that debouncing is wrong on most of the keyboard? If you double click a key (most will do, for example "J") it will fail to recognize second release and instead of expected "jj", you get autorepeat ("jjjjjjjjjjjjjjjjjjjjjj...").

Ok, I guess main keyboard is not on GPIO...

Best regards,

Pavel

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20180518/a68804eb/attachment.sig>

Hmm OK I have not seen that one.

No it's using omap4-keypad.c.

Good idea, I'll add a comment "Value above 7.95ms for no GPIO hardware debounce". I'll do it also for duovero.

Regards,

Tony