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sf: Enable FSR polling on N25Q256(A)

PATCH New Marek Vasut 3 participants 11 messages May 24, 2018 – Jun 29, 2018 Memory technology devices (MTD)

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Marek Vasut

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#0 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +2 -2
index 3b8f254ca2..fbc1bb6a5e 100644
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
 	{"n25q64a",	   INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
 	{"n25q128",	   INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
 	{"n25q128a",	   INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-	{"n25q256",	   INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-	{"n25q256a",	   INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
+	{"n25q256",	   INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+	{"n25q256a",	   INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
 	{"n25q512",	   INFO(0x20ba20, 0x0,  64 * 1024,  1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
 	{"n25q512a",	   INFO(0x20bb20, 0x0,  64 * 1024,  1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
 	{"n25q1024",	   INFO(0x20ba21, 0x0,  64 * 1024,  2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
Signature · 1 line
2.16.2
#1 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

+ Siva

Quoted 17 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -0
index 3b8f254ca2..fbc1bb6a5e 100644

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 134

Quoted 7 lines
drivers/mtd/spi/spi_flash_ids.c +2 -2
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
        {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
        {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
+       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

FSR is required to poll flag status instead of read status only from Micron n25q512 because 512 is divided into two 256 dies so FSR is used for polling each die. In case of n25q256 the flash is single entity (doesn't have die concept) so there is no need to poll FSR.

This is what I understood when I add initial FSR support 0f6232801cee4f45dbdb0cec45f71172c9b617ca

Jagan.

Signature · 4 lines
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
#2 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

Hi,

Quoted 44 lines

-----Original Message-----
From: Jagan Teki [mailto:jagannadh.teki at gmail.com]
Sent: Tuesday, May 29, 2018 10:22 AM
To: Marek Vasut <[email protected]>; Siva Durga Prasad Paladugu <[email protected]>
Cc: U-Boot Mailing List <[email protected]>; Tom Rini <[email protected]>
Subject: Re: [U-Boot] [PATCH] sf: Enable FSR polling on N25Q256(A)

+ Siva

Quoted 17 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
(quoted diff) +0 -0

b/drivers/mtd/spi/spi_flash_ids.c index 3b8f254ca2..fbc1bb6a5e 100644

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 130

Quoted 1 line
drivers/mtd/spi/spi_flash_ids.c +0 -0
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL |

WR_QPP | SECT_4K) },

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 131

Quoted 1 line
drivers/mtd/spi/spi_flash_ids.c +0 -0
        {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL |

WR_QPP) },

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 132

Quoted 1 line
drivers/mtd/spi/spi_flash_ids.c +0 -0
        {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL |

WR_QPP) },

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 133

Quoted 1 line
drivers/mtd/spi/spi_flash_ids.c +0 -1
-       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL |

WR_QPP | SECT_4K) },

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 134

Quoted 1 line
drivers/mtd/spi/spi_flash_ids.c +0 -1
-       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL |

WR_QPP | SECT_4K) },

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 133

Quoted 1 line
drivers/mtd/spi/spi_flash_ids.c +1 -0
+       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL |

WR_QPP | E_FSR | SECT_4K) },

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 134

Quoted 1 line
drivers/mtd/spi/spi_flash_ids.c +1 -0
+       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL |

WR_QPP | E_FSR | SECT_4K) },

Quoted 7 lines

FSR is required to poll flag status instead of read status only from Micron n25q512 because 512 is divided into two 256 dies so FSR is used for polling each die. In case of n25q256 the flash is single entity (doesn't have die concept) so there is no need to poll FSR.

This is what I understood when I add initial FSR support 0f6232801cee4f45dbdb0cec45f71172c9b617ca

PEC bit in Flag status register on N25Q256A will apply only for PROGRAM/ERASE commands but not to WRITE command cycles where as WIP bit in Status register will be applicable to all(PROGRAM/ERASE and WRITE). Here is the snippet from N25Q256A datasheet about PEC bit in FSR.
"These program/erase controller settings apply only to PROGRAM or ERASE command cycles
in progress; they do not apply to a WRITE command cycle in progress."

Regarding PEC bit in FSR of N25Q512(where it has two 256MB dies) here, it is mostly used to find out whether WRITE command(Write Status and Write Non volatile config Register) completed successfully for both dies. This is ensured by reading FSR twice with S# toggled in between and checking the PEC bit to be 1 in both the cases.

Thanks,
Siva

Quoted 8 lines

Jagan.

--
Jagan Teki
Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.

author
#3 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

In reply to Jagan Teki
Quoted 33 lines · Jagan Teki

+ Siva

Quoted 17 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -0
index 3b8f254ca2..fbc1bb6a5e 100644

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 134

Quoted 7 lines
drivers/mtd/spi/spi_flash_ids.c +2 -2
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
        {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
        {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
+       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

FSR is required to poll flag status instead of read status only from Micron n25q512 because 512 is divided into two 256 dies so FSR is used for polling each die. In case of n25q256 the flash is single entity (doesn't have die concept) so there is no need to poll FSR.

Quoted 2 lines

This is what I understood when I add initial FSR support 0f6232801cee4f45dbdb0cec45f71172c9b617ca

The datasheet for N25Q256A (which is probably a better reference than a commit in the U-Boot tree) claims the FSR is an indication of PROGRAM/ERASE completion. We use SR and FSR (if it is avaiable) to check whether all of the SNOR operations finished, so if FSR is available, we should use it. Plus, I have an impression that the SR polling is not reliable on the N25Q256A.

Signature · 2 lines
Best regards,
Marek Vasut
#4 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

Quoted 37 lines · Marek Vasut
Quoted 33 lines · Jagan Teki

+ Siva

Quoted 17 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -0
index 3b8f254ca2..fbc1bb6a5e 100644

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 134

Quoted 7 lines
drivers/mtd/spi/spi_flash_ids.c +2 -2
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
        {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
        {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
+       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

FSR is required to poll flag status instead of read status only from Micron n25q512 because 512 is divided into two 256 dies so FSR is used for polling each die. In case of n25q256 the flash is single entity (doesn't have die concept) so there is no need to poll FSR.

Quoted 2 lines

This is what I understood when I add initial FSR support 0f6232801cee4f45dbdb0cec45f71172c9b617ca

Quoted 6 lines

The datasheet for N25Q256A (which is probably a better reference than a commit in the U-Boot tree) claims the FSR is an indication of PROGRAM/ERASE completion. We use SR and FSR (if it is avaiable) to check whether all of the SNOR operations finished, so if FSR is available, we should use it. Plus, I have an impression that the SR polling is not reliable on the N25Q256A.

Does this the same case with Linux? I never see n25q256a to use FSR. did you find any issue/correction with current master?

Jagan.

Signature · 4 lines
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
#5 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

Quoted 38 lines · Jagan Teki
Quoted 37 lines · Marek Vasut
Quoted 35 lines · Jagan Teki

+ Siva

Quoted 17 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -0
index 3b8f254ca2..fbc1bb6a5e 100644

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 134

Quoted 7 lines
drivers/mtd/spi/spi_flash_ids.c +2 -2
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
        {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
        {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
+       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

FSR is required to poll flag status instead of read status only from Micron n25q512 because 512 is divided into two 256 dies so FSR is used for polling each die. In case of n25q256 the flash is single entity (doesn't have die concept) so there is no need to poll FSR.

This is what I understood when I add initial FSR support 0f6232801cee4f45dbdb0cec45f71172c9b617ca

Quoted 6 lines
Quoted 6 lines

The datasheet for N25Q256A (which is probably a better reference than a commit in the U-Boot tree) claims the FSR is an indication of PROGRAM/ERASE completion. We use SR and FSR (if it is avaiable) to check whether all of the SNOR operations finished, so if FSR is available, we should use it. Plus, I have an impression that the SR polling is not reliable on the N25Q256A.

Applied to u-boot-spi/master

author
#6 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

Quoted 39 lines · Jagan Teki
Quoted 38 lines · Jagan Teki
Quoted 37 lines · Marek Vasut
Quoted 35 lines · Jagan Teki

+ Siva

Quoted 17 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -0
index 3b8f254ca2..fbc1bb6a5e 100644

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 134

Quoted 7 lines
drivers/mtd/spi/spi_flash_ids.c +2 -2
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
        {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
        {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
+       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

FSR is required to poll flag status instead of read status only from Micron n25q512 because 512 is divided into two 256 dies so FSR is used for polling each die. In case of n25q256 the flash is single entity (doesn't have die concept) so there is no need to poll FSR.

This is what I understood when I add initial FSR support 0f6232801cee4f45dbdb0cec45f71172c9b617ca

Quoted 8 lines
Quoted 6 lines
Quoted 6 lines

The datasheet for N25Q256A (which is probably a better reference than a commit in the U-Boot tree) claims the FSR is an indication of PROGRAM/ERASE completion. We use SR and FSR (if it is avaiable) to check whether all of the SNOR operations finished, so if FSR is available, we should use it. Plus, I have an impression that the SR polling is not reliable on the N25Q256A.

Applied to u-boot-spi/master

So why did you apply this patch only now, now that it missed all RCs ? Since you seem to be quite keen on lecturing other maintainers how they should do their job, I'm really curious.

Signature · 2 lines
Best regards,
Marek Vasut
#7 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

Quoted 47 lines · Marek Vasut
Quoted 46 lines · Jagan Teki
Quoted 44 lines · Jagan Teki
Quoted 43 lines · Marek Vasut
Quoted 33 lines · Jagan Teki

+ Siva

Quoted 17 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -0
index 3b8f254ca2..fbc1bb6a5e 100644

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 134

Quoted 7 lines
drivers/mtd/spi/spi_flash_ids.c +2 -2
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
        {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
        {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
+       {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+       {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

FSR is required to poll flag status instead of read status only from Micron n25q512 because 512 is divided into two 256 dies so FSR is used for polling each die. In case of n25q256 the flash is single entity (doesn't have die concept) so there is no need to poll FSR.

Quoted 2 lines

This is what I understood when I add initial FSR support 0f6232801cee4f45dbdb0cec45f71172c9b617ca

The datasheet for N25Q256A (which is probably a better reference than a commit in the U-Boot tree) claims the FSR is an indication of PROGRAM/ERASE completion. We use SR and FSR (if it is avaiable) to check whether all of the SNOR operations finished, so if FSR is available, we should use it. Plus, I have an impression that the SR polling is not reliable on the N25Q256A.

Quoted 3 lines
Quoted 1 line

Applied to u-boot-spi/master

So why did you apply this patch only now, now that it missed all RCs ?

It's because of taking time for me to verify on hardware. ie reason I asked you about how Linux deal this.

Quoted 2 lines

Since you seem to be quite keen on lecturing other maintainers how they should do their job, I'm really curious.

As per as I know I commented to know why the patche apply such fast, Sorry If I made any wrong words on this.

author
#8 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

In reply to Marek Vasut
Quoted 18 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -0
index 3b8f254ca2..fbc1bb6a5e 100644

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 137

Quoted 10 lines
drivers/mtd/spi/spi_flash_ids.c +2 -2
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
 	{"n25q64a",	   INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
 	{"n25q128",	   INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
 	{"n25q128a",	   INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-	{"n25q256",	   INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-	{"n25q256a",	   INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
+	{"n25q256",	   INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+	{"n25q256a",	   INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
 	{"n25q512",	   INFO(0x20ba20, 0x0,  64 * 1024,  1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
 	{"n25q512a",	   INFO(0x20bb20, 0x0,  64 * 1024,  1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
 	{"n25q1024",	   INFO(0x20ba21, 0x0,  64 * 1024,  2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

So, where is this stuff, I don't see it in u-boot/master ?

Signature · 2 lines
Best regards,
Marek Vasut
#9 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

Quoted 23 lines · Marek Vasut
Quoted 22 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -2
index 3b8f254ca2..fbc1bb6a5e 100644
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
      {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
      {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
      {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-     {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-     {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
Quoted 8 lines

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 137

Quoted 6 lines
drivers/mtd/spi/spi_flash_ids.c +2 -0
+     {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+     {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
      {"n25q512",        INFO(0x20ba20, 0x0,  64 * 1024,  1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
      {"n25q512a",       INFO(0x20bb20, 0x0,  64 * 1024,  1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
      {"n25q1024",       INFO(0x20ba21, 0x0,  64 * 1024,  2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

So, where is this stuff, I don't see it in u-boot/master ?

Why it should be in u-boot/master? it's neither in u-boot-spi/master nor with PR. still under discussion.

author
#10 lore raw

PATCH 1/1 sf: Enable FSR polling on N25Q256(A)

Quoted 33 lines · Jagan Teki
Quoted 23 lines · Marek Vasut
Quoted 22 lines · Marek Vasut

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by Marek Vasut <[email protected]>
Cc Jagan Teki <[email protected]>
Cc Tom Rini <[email protected]>
---
 drivers/mtd/spi/spi_flash_ids.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/spi/spi_flash_ids.c +0 -2
index 3b8f254ca2..fbc1bb6a5e 100644
@@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
      {"n25q64a",        INFO(0x20bb17, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
      {"n25q128",        INFO(0x20ba18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
      {"n25q128a",       INFO(0x20bb18, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
-     {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
-     {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
Quoted 8 lines

drivers/mtd/spi/spi_flash_ids.c const struct spi_flash_info spi_flash_ids[] = { · line 137

Quoted 6 lines
drivers/mtd/spi/spi_flash_ids.c +2 -0
+     {"n25q256",        INFO(0x20ba19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
+     {"n25q256a",       INFO(0x20bb19, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
      {"n25q512",        INFO(0x20ba20, 0x0,  64 * 1024,  1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
      {"n25q512a",       INFO(0x20bb20, 0x0,  64 * 1024,  1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
      {"n25q1024",       INFO(0x20ba21, 0x0,  64 * 1024,  2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },

So, where is this stuff, I don't see it in u-boot/master ?

Quoted 2 lines

Why it should be in u-boot/master? it's neither in u-boot-spi/master nor with PR. still under discussion.

So what is the problem with this patch exactly ?

Signature · 2 lines
Best regards,
Marek Vasut