amd/include: Move register declarations from display to include/asic_reg
Subsystems (3)
PATCH 1/1 amd/include: Move register declarations from display to include/asic_reg
A few register addresses were declared inamd/display/dc/dce*/dce*_resource.c.
They have been consolidated with the appropriate
master list of registers in
amd/include/asic_reg/dce/...
This will make them accessible to external tools that need direct asic register access
Signed-off-by David Francis <[email protected]>
--- .../amd/display/dc/dce100/dce100_resource.c | 35 ------------------- .../amd/display/dc/dce110/dce110_resource.c | 35 ------------------- .../amd/display/dc/dce112/dce112_resource.c | 35 ------------------- .../drm/amd/display/dc/dce80/dce80_resource.c | 34 ------------------ .../drm/amd/include/asic_reg/dce/dce_10_0_d.h | 18 ++++++++++ .../drm/amd/include/asic_reg/dce/dce_11_0_d.h | 10 ++++++ .../drm/amd/include/asic_reg/dce/dce_11_2_d.h | 10 ++++++ .../drm/amd/include/asic_reg/dce/dce_8_0_d.h | 15 ++++++++ 8 files changed, 53 insertions(+), 139 deletions(-)
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +0 -35
@@ -59,46 +59,11 @@#include "gmc/gmc_8_2_sh_mask.h" #endif -#ifndef mmDP_DPHY_INTERNAL_CTRL -#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 -#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 -#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 -#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 -#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 -#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 -#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 -#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 -#endif -#ifndef mmBIOS_SCRATCH_2#define mmBIOS_SCRATCH_2 0x05CB#define mmBIOS_SCRATCH_6 0x05CF#endif -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL -#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC -#endif - -#ifndef mmDP_DPHY_FAST_TRAINING -#define mmDP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC -#define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC -#define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC -#define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC -#define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC -#define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC -#endif -static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { { .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +0 -35
@@ -68,46 +68,11 @@#include "gmc/gmc_8_2_sh_mask.h" #endif -#ifndef mmDP_DPHY_INTERNAL_CTRL -#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 -#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 -#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 -#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 -#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 -#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 -#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 -#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 -#endif -#ifndef mmBIOS_SCRATCH_2#define mmBIOS_SCRATCH_2 0x05CB#define mmBIOS_SCRATCH_6 0x05CF#endif -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL -#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC -#endif - -#ifndef mmDP_DPHY_FAST_TRAINING -#define mmDP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC -#define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC -#define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC -#define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC -#define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC -#define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC -#endif -#ifndef DPHY_RX_FAST_TRAINING_CAPABLE #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1#endif
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +0 -35
@@ -59,46 +59,11 @@#define DC_LOGGER \ dc->ctx->logger -#ifndef mmDP_DPHY_INTERNAL_CTRL -#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 -#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 -#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 -#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 -#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 -#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 -#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 -#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 -#endif -#ifndef mmBIOS_SCRATCH_2#define mmBIOS_SCRATCH_2 0x05CB#define mmBIOS_SCRATCH_6 0x05CF#endif -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL -#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC -#endif - -#ifndef mmDP_DPHY_FAST_TRAINING -#define mmDP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC -#define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC -#define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC -#define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC -#define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC -#define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC -#endif -enum dce112_clk_src_array_id {DCE112_CLK_SRC_PLL0 ,DCE112_CLK_SRC_PLL1 ,
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +0 -34
@@ -62,45 +62,11 @@#include "gmc/gmc_7_1_sh_mask.h" #endif -#ifndef mmDP_DPHY_INTERNAL_CTRL -#define mmDP_DPHY_INTERNAL_CTRL 0x1CDE -#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE -#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE -#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE -#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE -#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE -#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE -#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE -#endif - -#ifndef mmBIOS_SCRATCH_2#define mmBIOS_SCRATCH_2 0x05CB#define mmBIOS_SCRATCH_6 0x05CF#endif -#ifndef mmDP_DPHY_FAST_TRAINING -#define mmDP_DPHY_FAST_TRAINING 0x1CCE -#define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE -#define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE -#define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE -#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE -#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE -#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE -#define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE -#endif - - -#ifndef mmHPD_DC_HPD_CONTROL -#define mmHPD_DC_HPD_CONTROL 0x189A -#define mmHPD0_DC_HPD_CONTROL 0x189A -#define mmHPD1_DC_HPD_CONTROL 0x18A2 -#define mmHPD2_DC_HPD_CONTROL 0x18AA -#define mmHPD3_DC_HPD_CONTROL 0x18B2 -#define mmHPD4_DC_HPD_CONTROL 0x18BA -#define mmHPD5_DC_HPD_CONTROL 0x18C2 -#endif -#define DCE11_DIG_FE_CNTL 0x4a00#define DCE11_DIG_BE_CNTL 0x4a47#define DCE11_DP_SEC 0x4ac3
drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h +18 -0
@@ -7354,5 +7354,23 @@#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a +#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 +#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 +#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 +#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 +#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 +#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 +#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 +#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 +#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc#endif /* DCE_10_0_D_H */
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h +10 -0
@@ -7653,5 +7653,15 @@#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a +#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 +#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 +#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 +#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 +#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 +#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 +#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 +#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7#endif /* DCE_11_0_D_H */
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h +10 -0
@@ -10080,5 +10080,15 @@#define mmDPCSTX5_DPCSTX_TEST_DEBUG_DATA 0x9bfd#define mmDPCSTX6_DPCSTX_TEST_DEBUG_DATA 0x9c9d#define mmDPCSTX7_DPCSTX_TEST_DEBUG_DATA 0x9d3d +#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 +#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 +#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 +#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 +#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 +#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 +#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 +#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7#endif /* DCE_11_2_D_H */
drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h +15 -0
@@ -5708,5 +5708,20 @@#define mmXDMA_PG_STATUS 0x3fb#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd +#define mmDP_DPHY_INTERNAL_CTRL 0x1cde +#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1cde +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1fde +#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42de +#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45de +#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48de +#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4bde +#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4ede +#define mmHPD_DC_HPD_CONTROL 0x189a +#define mmHPD0_DC_HPD_CONTROL 0x189a +#define mmHPD1_DC_HPD_CONTROL 0x18a2 +#define mmHPD2_DC_HPD_CONTROL 0x18aa +#define mmHPD3_DC_HPD_CONTROL 0x18b2 +#define mmHPD4_DC_HPD_CONTROL 0x18ba +#define mmHPD5_DC_HPD_CONTROL 0x18c2#endif /* DCE_8_0_D_H */
Signature · 6 lines
2.17.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
A message that is not in the archive (sent off-list or not yet received): 20180531131905.32017-1-David.Francis-5C7GfCeVMHo@public.gmane.org
Harry Wentland
Reviewed-byQuoted 282 lines · David Francis
A few register addresses were declared in
amd/display/dc/dce*/dce*_resource.c.They have been consolidated with the appropriate
master list of registers in
amd/include/asic_reg/dce/...This will make them accessible to external tools that need direct asic register access
Signed-off-by David Francis <[email protected]>--- .../amd/display/dc/dce100/dce100_resource.c | 35 ------------------- .../amd/display/dc/dce110/dce110_resource.c | 35 ------------------- .../amd/display/dc/dce112/dce112_resource.c | 35 ------------------- .../drm/amd/display/dc/dce80/dce80_resource.c | 34 ------------------ .../drm/amd/include/asic_reg/dce/dce_10_0_d.h | 18 ++++++++++ .../drm/amd/include/asic_reg/dce/dce_11_0_d.h | 10 ++++++ .../drm/amd/include/asic_reg/dce/dce_11_2_d.h | 10 ++++++ .../drm/amd/include/asic_reg/dce/dce_8_0_d.h | 15 ++++++++ 8 files changed, 53 insertions(+), 139 deletions(-)drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +0
-35@@ -59,46 +59,11 @@#include "gmc/gmc_8_2_sh_mask.h" #endif -#ifndef mmDP_DPHY_INTERNAL_CTRL -#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 -#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 -#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 -#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 -#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 -#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 -#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 -#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 -#endif -#ifndef mmBIOS_SCRATCH_2#define mmBIOS_SCRATCH_2 0x05CB#define mmBIOS_SCRATCH_6 0x05CF#endif -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL -#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC -#endif - -#ifndef mmDP_DPHY_FAST_TRAINING -#define mmDP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC -#define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC -#define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC -#define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC -#define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC -#define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC -#endif -static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { { .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +0
-35@@ -68,46 +68,11 @@#include "gmc/gmc_8_2_sh_mask.h" #endif -#ifndef mmDP_DPHY_INTERNAL_CTRL -#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 -#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 -#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 -#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 -#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 -#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 -#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 -#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 -#endif -#ifndef mmBIOS_SCRATCH_2#define mmBIOS_SCRATCH_2 0x05CB#define mmBIOS_SCRATCH_6 0x05CF#endif -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL -#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC -#endif - -#ifndef mmDP_DPHY_FAST_TRAINING -#define mmDP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC -#define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC -#define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC -#define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC -#define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC -#define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC -#endif -#ifndef DPHY_RX_FAST_TRAINING_CAPABLE #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1#endif drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +0
-35@@ -59,46 +59,11 @@#define DC_LOGGER \ dc->ctx->logger -#ifndef mmDP_DPHY_INTERNAL_CTRL -#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 -#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 -#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 -#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 -#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 -#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 -#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 -#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 -#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 -#endif -#ifndef mmBIOS_SCRATCH_2#define mmBIOS_SCRATCH_2 0x05CB#define mmBIOS_SCRATCH_6 0x05CF#endif -#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL -#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC -#endif - -#ifndef mmDP_DPHY_FAST_TRAINING -#define mmDP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC -#define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC -#define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC -#define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC -#define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC -#define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC -#define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC -#endif -enum dce112_clk_src_array_id {DCE112_CLK_SRC_PLL0 ,DCE112_CLK_SRC_PLL1 ,drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +0
-34@@ -62,45 +62,11 @@#include "gmc/gmc_7_1_sh_mask.h" #endif -#ifndef mmDP_DPHY_INTERNAL_CTRL -#define mmDP_DPHY_INTERNAL_CTRL 0x1CDE -#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE -#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE -#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE -#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE -#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE -#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE -#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE -#endif - -#ifndef mmBIOS_SCRATCH_2#define mmBIOS_SCRATCH_2 0x05CB#define mmBIOS_SCRATCH_6 0x05CF#endif -#ifndef mmDP_DPHY_FAST_TRAINING -#define mmDP_DPHY_FAST_TRAINING 0x1CCE -#define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE -#define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE -#define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE -#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE -#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE -#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE -#define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE -#endif - - -#ifndef mmHPD_DC_HPD_CONTROL -#define mmHPD_DC_HPD_CONTROL 0x189A -#define mmHPD0_DC_HPD_CONTROL 0x189A -#define mmHPD1_DC_HPD_CONTROL 0x18A2 -#define mmHPD2_DC_HPD_CONTROL 0x18AA -#define mmHPD3_DC_HPD_CONTROL 0x18B2 -#define mmHPD4_DC_HPD_CONTROL 0x18BA -#define mmHPD5_DC_HPD_CONTROL 0x18C2 -#endif -#define DCE11_DIG_FE_CNTL 0x4a00#define DCE11_DIG_BE_CNTL 0x4a47#define DCE11_DP_SEC 0x4ac3drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h +18
-0@@ -7354,5 +7354,23 @@#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a +#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 +#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 +#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 +#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 +#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 +#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 +#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 +#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 +#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc#endif /* DCE_10_0_D_H */ drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h +10
-0@@ -7653,5 +7653,15 @@#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a +#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 +#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 +#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 +#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 +#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 +#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 +#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 +#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7#endif /* DCE_11_0_D_H */ drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h +1
-0@@ -10080,5 +10080,15 @@#define mmDPCSTX5_DPCSTX_TEST_DEBUG_DATA 0x9bfd#define mmDPCSTX6_DPCSTX_TEST_DEBUG_DATA 0x9c9d#define mmDPCSTX7_DPCSTX_TEST_DEBUG_DATA 0x9d3d +#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h line 10093
Quoted 10 lines
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h +9
-0+#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 +#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 +#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 +#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 +#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 +#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 +#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 +#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
Can we add these below the DP_MSA_MISC registers and above DP_VID_TIMING?
Same for other DCE versions.
With that fixed this change is
Reviewed-by Harry Wentland <[email protected]>
Harry
Quoted 17 lines
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h +0
-0#endif /* DCE_11_2_D_H */ drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h +7
-0@@ -5708,5 +5708,20 @@#define mmXDMA_PG_STATUS 0x3fb#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd +#define mmDP_DPHY_INTERNAL_CTRL 0x1cde +#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1cde +#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1fde +#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42de +#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45de +#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48de +#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4bde
drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h line 5727
Quoted 10 lines
drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h +8
-0+#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4ede +#define mmHPD_DC_HPD_CONTROL 0x189a +#define mmHPD0_DC_HPD_CONTROL 0x189a +#define mmHPD1_DC_HPD_CONTROL 0x18a2 +#define mmHPD2_DC_HPD_CONTROL 0x18aa +#define mmHPD3_DC_HPD_CONTROL 0x18b2 +#define mmHPD4_DC_HPD_CONTROL 0x18ba +#define mmHPD5_DC_HPD_CONTROL 0x18c2#endif /* DCE_8_0_D_H */
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