switch mips to use the generic dma map ops

RFC In review Christoph Hellwig 3 participants 32 messages May 25, 2018 – Jul 11, 2018 6 messages not in the archive

Subsystems (5)

Library code MIPS MIPS/LOONGSON64 architecture Broadcom bmips MIPS architecture +1 more subsystems

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Christoph Hellwig

author

2018-05-25 09:20 UTC #0 lore raw

Hi all,

this huge series does a deep cleaning of the mips dma mapping code and moves most architectures over to use the generic dma_direct_ops or dma_noncoherent_ops. The Jazz architectures grows a new dma_map_ops tailered to its bare bones iommu implementation, and the swiotlb code use by Loongson-3 and Octeon is merged into a single implementation, pending further unification with the generic swiotlb_ops in another step.

Note that all this has been compile tested only, and I've probably missed even that for some platforms..

A git tree is available here:

git://git.infradead.org/users/hch/misc.git mips-direct-ops

Gitweb:

http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/mips-direct-ops

A message that is not in the archive (sent off-list or not yet received): [email protected]

Christoph Hellwig

author

2018-05-25 09:20 UTC #2 lore raw

PATCH 1/25 MIPS: remove a dead ifdef from mach-ath25/dma-coherence.h

ath25 is alwas non-coherent, so keeping these ifdefs doesn't make any sense.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/include/asm/mach-ath25/dma-coherence.h | 5 -----
 1 file changed, 5 deletions(-)

arch/mips/include/asm/mach-ath25/dma-coherence.h +0 -5

index d5defdde32db..124755d4f079 100644
@@ -61,12 +61,7 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
 
 static inline int plat_device_is_coherent(struct device *dev)
 {
-#ifdef CONFIG_DMA_COHERENT
-	return 1;
-#endif
-#ifdef CONFIG_DMA_NONCOHERENT
 	return 0;
-#endif
 }
 
 static inline void plat_post_dma_flush(struct device *dev)

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #3 lore raw

PATCH 2/25 MIPS: simplify CONFIG_DMA_NONCOHERENT ifdefs

In reply to a message not in the archive

CONFIG_DMA_MAYBE_COHERENT already selects CONFIG_DMA_NONCOHERENT, so we can remove the extra conditions.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/include/asm/io.h | 4 ++--
 arch/mips/mm/c-r4k.c       | 4 ++--
 arch/mips/mm/cache.c       | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

arch/mips/include/asm/io.h +2 -2

index a7d0b836f2f7..6d6bdc6a48eb 100644
@@ -588,7 +588,7 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
  *
  * This API used to be exported; it now is for arch code internal use only.
  */
-#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
+#ifdef CONFIG_DMA_NONCOHERENT
 
 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);

@@ -607,7 +607,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 #define dma_cache_inv(start,size)	\
 	do { (void) (start); (void) (size); } while (0)
 
-#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
+#endif /* CONFIG_DMA_NONCOHERENT */
 
 /*
  * Read a 32-bit register that requires a 64-bit read cycle on the bus.

arch/mips/mm/c-r4k.c +2 -2

index 6f534b209971..dcfff4f6cd88 100644
@@ -830,7 +830,7 @@ static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
 	return __r4k_flush_icache_range(start, end, true);
 }
 
-#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
+#ifdef CONFIG_DMA_NONCOHERENT
 
 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 {

@@ -901,7 +901,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 	bc_inv(addr, size);
 	__sync();
 }
-#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
+#endif /* CONFIG_DMA_NONCOHERENT */
 
 struct flush_cache_sigtramp_args {
 	struct mm_struct *mm;

arch/mips/mm/cache.c +2 -2

index 0d3c656feba0..70a523151ff3 100644
@@ -56,7 +56,7 @@ EXPORT_SYMBOL_GPL(local_flush_data_cache_page);
 EXPORT_SYMBOL(flush_data_cache_page);
 EXPORT_SYMBOL(flush_icache_all);
 
-#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
+#ifdef CONFIG_DMA_NONCOHERENT
 
 /* DMA cache operations. */
 void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);

@@ -65,7 +65,7 @@ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 
 EXPORT_SYMBOL(_dma_cache_wback_inv);
 
-#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
+#endif /* CONFIG_DMA_NONCOHERENT */
 
 /*
  * We could optimize the case where the cache argument is not BCACHE but

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #4 lore raw

PATCH 3/25 MIPS: remove CONFIG_DMA_COHERENT

In reply to a message not in the archive

We can just check for !CONFIG_DMA_NONCOHERENT instead and simplify things a lot.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                            | 16 ----------------
 arch/mips/include/asm/dma-coherence.h        |  6 +++---
 arch/mips/include/asm/mach-generic/kmalloc.h |  3 +--
 arch/mips/mti-malta/malta-setup.c            |  4 ++--
 arch/mips/sibyte/Kconfig                     |  1 -
 5 files changed, 6 insertions(+), 24 deletions(-)

arch/mips/Kconfig +0 ~~-16~~

index 2dcdc13cd65d..43bb037301f6 100644
@@ -660,7 +660,6 @@ config SGI_IP27
 	select FW_ARC64
 	select BOOT_ELF64
 	select DEFAULT_SGI_PARTITION
-	select DMA_COHERENT
 	select SYS_HAS_EARLY_PRINTK
 	select HW_HAS_PCI
 	select NR_CPUS_DEFAULT_64

@@ -737,7 +736,6 @@ config SGI_IP32
 config SIBYTE_CRHINE
 	bool "Sibyte BCM91120C-CRhine"
 	select BOOT_ELF32
-	select DMA_COHERENT
 	select SIBYTE_BCM1120
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -747,7 +745,6 @@ config SIBYTE_CRHINE
 config SIBYTE_CARMEL
 	bool "Sibyte BCM91120x-Carmel"
 	select BOOT_ELF32
-	select DMA_COHERENT
 	select SIBYTE_BCM1120
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -757,7 +754,6 @@ config SIBYTE_CARMEL
 config SIBYTE_CRHONE
 	bool "Sibyte BCM91125C-CRhone"
 	select BOOT_ELF32
-	select DMA_COHERENT
 	select SIBYTE_BCM1125
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -768,7 +764,6 @@ config SIBYTE_CRHONE
 config SIBYTE_RHONE
 	bool "Sibyte BCM91125E-Rhone"
 	select BOOT_ELF32
-	select DMA_COHERENT
 	select SIBYTE_BCM1125H
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -778,7 +773,6 @@ config SIBYTE_RHONE
 config SIBYTE_SWARM
 	bool "Sibyte BCM91250A-SWARM"
 	select BOOT_ELF32
-	select DMA_COHERENT
 	select HAVE_PATA_PLATFORM
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE

@@ -791,7 +785,6 @@ config SIBYTE_SWARM
 config SIBYTE_LITTLESUR
 	bool "Sibyte BCM91250C2-LittleSur"
 	select BOOT_ELF32
-	select DMA_COHERENT
 	select HAVE_PATA_PLATFORM
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE

@@ -803,7 +796,6 @@ config SIBYTE_LITTLESUR
 config SIBYTE_SENTOSA
 	bool "Sibyte BCM91250E-Sentosa"
 	select BOOT_ELF32
-	select DMA_COHERENT
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -813,7 +805,6 @@ config SIBYTE_SENTOSA
 config SIBYTE_BIGSUR
 	bool "Sibyte BCM91480B-BigSur"
 	select BOOT_ELF32
-	select DMA_COHERENT
 	select NR_CPUS_DEFAULT_4
 	select SIBYTE_BCM1x80
 	select SWAP_IO_SPACE

@@ -890,7 +881,6 @@ config CAVIUM_OCTEON_SOC
 	select CEVT_R4K
 	select ARCH_HAS_PHYS_TO_DMA
 	select PHYS_ADDR_T_64BIT
-	select DMA_COHERENT
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select EDAC_SUPPORT

@@ -939,7 +929,6 @@ config NLM_XLR_BOARD
 	select PHYS_ADDR_T_64BIT
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_HIGHMEM
-	select DMA_COHERENT
 	select NR_CPUS_DEFAULT_32
 	select CEVT_R4K
 	select CSRC_R4K

@@ -967,7 +956,6 @@ config NLM_XLP_BOARD
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	select SYS_SUPPORTS_HIGHMEM
-	select DMA_COHERENT
 	select NR_CPUS_DEFAULT_32
 	select CEVT_R4K
 	select CSRC_R4K

@@ -986,7 +974,6 @@ config MIPS_PARAVIRT
 	bool "Para-Virtualized guest system"
 	select CEVT_R4K
 	select CSRC_R4K
-	select DMA_COHERENT
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN

@@ -1112,9 +1099,6 @@ config DMA_PERDEV_COHERENT
 	bool
 	select DMA_MAYBE_COHERENT
 
-config DMA_COHERENT
-	bool
-
 config DMA_NONCOHERENT
 	bool
 	select NEED_DMA_MAP_STATE

arch/mips/include/asm/dma-coherence.h +3 -3

index 72d0eab02afc..8eda48748ed5 100644
@@ -21,10 +21,10 @@ enum coherent_io_user_state {
 extern enum coherent_io_user_state coherentio;
 extern int hw_coherentio;
 #else
-#ifdef CONFIG_DMA_COHERENT
-#define coherentio	IO_COHERENCE_ENABLED
-#else
+#ifdef CONFIG_DMA_NONCOHERENT
 #define coherentio	IO_COHERENCE_DISABLED
+#else
+#define coherentio	IO_COHERENCE_ENABLED
 #endif
 #define hw_coherentio	0
 #endif /* CONFIG_DMA_MAYBE_COHERENT */

arch/mips/include/asm/mach-generic/kmalloc.h +1 -2

index 74207c7bd00d..649a98338886 100644
@@ -2,8 +2,7 @@
 #ifndef __ASM_MACH_GENERIC_KMALLOC_H
 #define __ASM_MACH_GENERIC_KMALLOC_H
 
-
-#ifndef CONFIG_DMA_COHERENT
+#ifdef CONFIG_DMA_NONCOHERENT
 /*
  * Total overkill for most systems but need as a safe default.
  * Set this one if any device in the system might do non-coherent DMA.

arch/mips/mti-malta/malta-setup.c +2 -2

index 7b63914d2e58..4d5cdfeee3db 100644
@@ -227,7 +227,7 @@ static void __init bonito_quirks_setup(void)
 	} else
 		BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
 
-#ifdef CONFIG_DMA_COHERENT
+#ifndef CONFIG_DMA_NONCOHERENT
 	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
 		BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
 		pr_info("Enabled Bonito CPU coherency\n");

@@ -279,7 +279,7 @@ void __init plat_mem_setup(void)
 	 */
 	enable_dma(4);
 
-#ifdef CONFIG_DMA_COHERENT
+#ifndef CONFIG_DMA_NONCOHERENT
 	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
 		panic("Hardware DMA cache coherency not supported");
 #endif

arch/mips/sibyte/Kconfig +0 -1

index f4dbce25bc6a..7ec278d72096 100644
@@ -70,7 +70,6 @@ config SIBYTE_BCM1x55
 
 config SIBYTE_SB1xxx_SOC
 	bool
-	select DMA_COHERENT
 	select IRQ_MIPS_CPU
 	select SWAP_IO_SPACE
 	select SYS_SUPPORTS_32BIT_KERNEL

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #5 lore raw

PATCH 4/25 MIPS: Octeon: unexport __phys_to_dma and __dma_to_phys

In reply to a message not in the archive

These functions are just low-level helpers for the swiotlb and dma-direct implementations, and should never be used by drivers.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/cavium-octeon/dma-octeon.c | 3 ---
 1 file changed, 3 deletions(-)

arch/mips/cavium-octeon/dma-octeon.c +0 -3

index 7b335ab21697..e5d00c79bd26 100644
@@ -13,7 +13,6 @@
 #include <linux/dma-direct.h>
 #include <linux/scatterlist.h>
 #include <linux/bootmem.h>
-#include <linux/export.h>
 #include <linux/swiotlb.h>
 #include <linux/types.h>
 #include <linux/init.h>

@@ -190,7 +189,6 @@ dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
 
 	return ops->phys_to_dma(dev, paddr);
 }
-EXPORT_SYMBOL(__phys_to_dma);
 
 phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
 {

@@ -200,7 +198,6 @@ phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
 
 	return ops->dma_to_phys(dev, daddr);
 }
-EXPORT_SYMBOL(__dma_to_phys);
 
 static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
 	.dma_map_ops = {

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #6 lore raw

PATCH 5/25 MIPS: Octeon: refactor swiotlb code

In reply to a message not in the archive

Share a common set of swiotlb operations, and to instead branch out in __phys_to_dma/__dma_to_phys for the PCI vs non-PCI case. Also use const structures for the PCI methods so that attackers can't use them as exploit vectors.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/cavium-octeon/dma-octeon.c          | 169 ++++++++----------
 .../asm/mach-cavium-octeon/dma-coherence.h    |   2 -
 arch/mips/pci/pci-octeon.c                    |   2 -
 3 files changed, 70 insertions(+), 103 deletions(-)

arch/mips/cavium-octeon/dma-octeon.c +70 ~~-99~~

index e5d00c79bd26..1e68636c9137 100644
@@ -23,10 +23,16 @@
 #include <asm/octeon/octeon.h>
 
 #ifdef CONFIG_PCI
+#include <linux/pci.h>
 #include <asm/octeon/pci-octeon.h>
 #include <asm/octeon/cvmx-npi-defs.h>
 #include <asm/octeon/cvmx-pci-defs.h>
 
+struct octeon_dma_map_ops {
+	dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
+	phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
+};
+
 static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
 {
 	if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))

@@ -43,6 +49,11 @@ static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
 		return daddr;
 }
 
+static const struct octeon_dma_map_ops octeon_gen2_ops = {
+	.phys_to_dma	= octeon_hole_phys_to_dma,
+	.dma_to_phys	= octeon_hole_dma_to_phys,
+};
+
 static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)

@@ -60,15 +71,10 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
 	return daddr;
 }
 
-static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
-{
-	return octeon_hole_phys_to_dma(paddr);
-}
-
-static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
-{
-	return octeon_hole_dma_to_phys(daddr);
-}
+static const struct octeon_dma_map_ops octeon_gen1_ops = {
+	.phys_to_dma	= octeon_gen1_phys_to_dma,
+	.dma_to_phys	= octeon_gen1_dma_to_phys,
+};
 
 static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {

@@ -92,6 +98,11 @@ static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
 	return daddr;
 }
 
+static const struct octeon_dma_map_ops octeon_big_ops = {
+	.phys_to_dma	= octeon_big_phys_to_dma,
+	.dma_to_phys	= octeon_big_dma_to_phys,
+};
+
 static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
 					   phys_addr_t paddr)
 {

@@ -120,6 +131,32 @@ static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
 	return daddr;
 }
 
+static const struct octeon_dma_map_ops octeon_small_ops = {
+	.phys_to_dma	= octeon_small_phys_to_dma,
+	.dma_to_phys	= octeon_small_dma_to_phys,
+};
+
+static const struct octeon_dma_map_ops *octeon_pci_dma_ops;
+
+void __init octeon_pci_dma_init(void)
+{
+	switch (octeon_dma_bar_type) {
+	case OCTEON_DMA_BAR_TYPE_PCIE2:
+		octeon_pci_dma_ops = &octeon_gen2_ops;
+		break;
+	case OCTEON_DMA_BAR_TYPE_PCIE:
+		octeon_pci_dma_ops = &octeon_gen1_ops;
+		break;
+	case OCTEON_DMA_BAR_TYPE_BIG:
+		octeon_pci_dma_ops = &octeon_big_ops;
+		break;
+	case OCTEON_DMA_BAR_TYPE_SMALL:
+		octeon_pci_dma_ops = &octeon_small_ops;
+		break;
+	default:
+		BUG();
+	}
+}
 #endif /* CONFIG_PCI */
 
 static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,

@@ -165,57 +202,37 @@ static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
 	return ret;
 }
 
-static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
-{
-	return paddr;
-}
-
-static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
-{
-	return daddr;
-}
-
-struct octeon_dma_map_ops {
-	const struct dma_map_ops dma_map_ops;
-	dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
-	phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
-};
-
 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
-	struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
-						      struct octeon_dma_map_ops,
-						      dma_map_ops);
-
-	return ops->phys_to_dma(dev, paddr);
+#ifdef CONFIG_PCI
+	if (dev && dev_is_pci(dev))
+		return octeon_pci_dma_ops->phys_to_dma(dev, paddr);
+#endif
+	return paddr;
 }
 
 phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
 {
-	struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
-						      struct octeon_dma_map_ops,
-						      dma_map_ops);
-
-	return ops->dma_to_phys(dev, daddr);
+#ifdef CONFIG_PCI
+	if (dev && dev_is_pci(dev))
+		return octeon_pci_dma_ops->dma_to_phys(dev, daddr);
+#endif
+	return daddr;
 }
 
-static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
-	.dma_map_ops = {
-		.alloc = octeon_dma_alloc_coherent,
-		.free = swiotlb_free,
-		.map_page = octeon_dma_map_page,
-		.unmap_page = swiotlb_unmap_page,
-		.map_sg = octeon_dma_map_sg,
-		.unmap_sg = swiotlb_unmap_sg_attrs,
-		.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
-		.sync_single_for_device = octeon_dma_sync_single_for_device,
-		.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
-		.sync_sg_for_device = octeon_dma_sync_sg_for_device,
-		.mapping_error = swiotlb_dma_mapping_error,
-		.dma_supported = swiotlb_dma_supported
-	},
-	.phys_to_dma = octeon_unity_phys_to_dma,
-	.dma_to_phys = octeon_unity_dma_to_phys
+static const struct dma_map_ops octeon_swiotlb_ops = {
+	.alloc			= octeon_dma_alloc_coherent,
+	.free			= swiotlb_free,
+	.map_page		= octeon_dma_map_page,
+	.unmap_page		= swiotlb_unmap_page,
+	.map_sg			= octeon_dma_map_sg,
+	.unmap_sg		= swiotlb_unmap_sg_attrs,
+	.sync_single_for_cpu	= swiotlb_sync_single_for_cpu,
+	.sync_single_for_device	= octeon_dma_sync_single_for_device,
+	.sync_sg_for_cpu	= swiotlb_sync_sg_for_cpu,
+	.sync_sg_for_device	= octeon_dma_sync_sg_for_device,
+	.mapping_error		= swiotlb_dma_mapping_error,
+	.dma_supported		= swiotlb_dma_supported
 };
 
 char *octeon_swiotlb;

@@ -281,51 +298,5 @@ void __init plat_swiotlb_setup(void)
 	if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
 		panic("Cannot allocate SWIOTLB buffer");
 
-	mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
-}
-
-#ifdef CONFIG_PCI
-static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
-	.dma_map_ops = {
-		.alloc = octeon_dma_alloc_coherent,
-		.free = swiotlb_free,
-		.map_page = octeon_dma_map_page,
-		.unmap_page = swiotlb_unmap_page,
-		.map_sg = octeon_dma_map_sg,
-		.unmap_sg = swiotlb_unmap_sg_attrs,
-		.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
-		.sync_single_for_device = octeon_dma_sync_single_for_device,
-		.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
-		.sync_sg_for_device = octeon_dma_sync_sg_for_device,
-		.mapping_error = swiotlb_dma_mapping_error,
-		.dma_supported = swiotlb_dma_supported
-	},
-};
-
-const struct dma_map_ops *octeon_pci_dma_map_ops;
-
-void __init octeon_pci_dma_init(void)
-{
-	switch (octeon_dma_bar_type) {
-	case OCTEON_DMA_BAR_TYPE_PCIE2:
-		_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
-		_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
-		break;
-	case OCTEON_DMA_BAR_TYPE_PCIE:
-		_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
-		_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
-		break;
-	case OCTEON_DMA_BAR_TYPE_BIG:
-		_octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
-		_octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
-		break;
-	case OCTEON_DMA_BAR_TYPE_SMALL:
-		_octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
-		_octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
-		break;
-	default:
-		BUG();
-	}
-	octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
+	mips_dma_map_ops = &octeon_swiotlb_ops;
 }
-#endif /* CONFIG_PCI */

arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +0 -2

index 6eb1ee548b11..c5cdeea495f8 100644
@@ -72,8 +72,6 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
 phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
 
-struct dma_map_ops;
-extern const struct dma_map_ops *octeon_pci_dma_map_ops;
 extern char *octeon_swiotlb;
 
 #endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */

arch/mips/pci/pci-octeon.c +0 -2

index 3e92a06fa772..a20697df3539 100644
@@ -166,8 +166,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 		pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
 	}
 
-	dev->dev.dma_ops = octeon_pci_dma_map_ops;
-
 	return 0;
 }

Signature · 1 line

2.17.0

A message that is not in the archive (sent off-list or not yet received): [email protected]

Paul Burton

Reviewed-by

2018-05-30 23:25 UTC #8 lore raw

Re: [PATCH 05/25] MIPS: Octeon: refactor swiotlb code

Hi Christoph,

For patches 1-4:

Reviewed-by Paul Burton <[email protected]>

Comment below for this patch though.

Quoted 22 lines · Christoph Hellwig

arch/mips/cavium-octeon/dma-octeon.c +6 -0

index e5d00c79bd26..1e68636c9137 100644
@@ -23,10 +23,16 @@
 #include <asm/octeon/octeon.h>
 
 #ifdef CONFIG_PCI
+#include <linux/pci.h>
 #include <asm/octeon/pci-octeon.h>
 #include <asm/octeon/cvmx-npi-defs.h>
 #include <asm/octeon/cvmx-pci-defs.h>
 
+struct octeon_dma_map_ops {
+	dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
+	phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
+};
+
 static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
 {
 	if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))

arch/mips/cavium-octeon/dma-octeon.c static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr) · line 55

Quoted 7 lines

arch/mips/cavium-octeon/dma-octeon.c +4 -0

@@ -43,6 +49,11 @@ static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
 		return daddr;
 }
 
+static const struct octeon_dma_map_ops octeon_gen2_ops = {
+	.phys_to_dma	= octeon_hole_phys_to_dma,
+	.dma_to_phys	= octeon_hole_dma_to_phys,
+};

These are pointers to functions of the wrong type, right? phys_to_dma & dma_to_phys have the struct device * argument but the octeon_hole_* functions do not. I'd expect we either need to restore the octeon_gen2_* wrappers that you remove below or change the definition of the octeon_hole_* functions.

Thanks,
Paul

Quoted 16 lines

arch/mips/cavium-octeon/dma-octeon.c +0 -9

 static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)

@@ -60,15 +71,10 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
 	return daddr;
 }
 
-static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
-{
-	return octeon_hole_phys_to_dma(paddr);
-}
-
-static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
-{
-	return octeon_hole_dma_to_phys(daddr);
-}

Christoph Hellwig

author

2018-05-31 16:32 UTC #9 lore raw

Re: [PATCH 05/25] MIPS: Octeon: refactor swiotlb code

Quoted 10 lines · Paul Burton

arch/mips/cavium-octeon/dma-octeon.c static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr) · line 55
Quoted 4 lines
arch/mips/cavium-octeon/dma-octeon.c +4 -0
+static const struct octeon_dma_map_ops octeon_gen2_ops = {
+	.phys_to_dma	= octeon_hole_phys_to_dma,
+	.dma_to_phys	= octeon_hole_dma_to_phys,
+};
These are pointers to functions of the wrong type, right? phys_to_dma & dma_to_phys have the struct device * argument but the octeon_hole_* functions do not. I'd expect we either need to restore the octeon_gen2_* wrappers that you remove below or change the definition of the octeon_hole_* functions.

That is true. I have no idea how that passed the buildbot, which reported all kinds of other issues in the original octeon conversion.

I'll fix this for the next respin.

Christoph Hellwig

author

2018-05-25 09:20 UTC #10 lore raw

PATCH 6/25 MIPS: loongson: remove loongson_dma_supported

In reply to a message not in the archive

swiotlb_dma_supported will always return true for the a mask large enough to be covered by wired up physical address, so this function is pointless.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/loongson64/common/dma-swiotlb.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

arch/mips/loongson64/common/dma-swiotlb.c +1 -8

index 6a739f8ae110..a5e50f2ec301 100644
@@ -56,13 +56,6 @@ static void loongson_dma_sync_sg_for_device(struct device *dev,
 	mb();
 }
 
-static int loongson_dma_supported(struct device *dev, u64 mask)
-{
-	if (mask > DMA_BIT_MASK(loongson_sysconf.dma_mask_bits))
-		return 0;
-	return swiotlb_dma_supported(dev, mask);
-}
-
 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
 	long nid;

@@ -99,7 +92,7 @@ static const struct dma_map_ops loongson_dma_map_ops = {
 	.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
 	.sync_sg_for_device = loongson_dma_sync_sg_for_device,
 	.mapping_error = swiotlb_dma_mapping_error,
-	.dma_supported = loongson_dma_supported,
+	.dma_supported = swiotlb_dma_supported,
 };
 
 void __init plat_swiotlb_setup(void)

Signature · 1 line

2.17.0

A message that is not in the archive (sent off-list or not yet received): [email protected]

Paul Burton

2018-05-31 23:12 UTC #12 lore raw

Re: [PATCH 06/25] MIPS: loongson: remove loongson_dma_supported

Hi Christoph,

Quoted 3 lines · Christoph Hellwig

swiotlb_dma_supported will always return true for the a mask large enough to be covered by wired up physical address, so this function is pointless.

Shouldn't this be "large enough to cover all wired up physical addresses"? Or maybe even more correctly "large enough to cover all DMA addresses that might be used"?

Also, there's a spurious "the" on the first line.

Quoted 10 lines

Signed-off-by Christoph Hellwig <[email protected]>
---
 arch/mips/loongson64/common/dma-swiotlb.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)
arch/mips/loongson64/common/dma-swiotlb.c +0 -0
index 6a739f8ae110..a5e50f2ec301 100644

arch/mips/loongson64/common/dma-swiotlb.c static void loongson_dma_sync_sg_for_device(struct device *dev, · line 62

Quoted 7 lines

arch/mips/loongson64/common/dma-swiotlb.c +0 -4

@@ -56,13 +56,6 @@ static void loongson_dma_sync_sg_for_device(struct device *dev,
 	mb();
 }
 
-static int loongson_dma_supported(struct device *dev, u64 mask)
-{
-	if (mask > DMA_BIT_MASK(loongson_sysconf.dma_mask_bits))
-		return 0;

The comparison here will only evaluate true (indicating that DMA is not supported) if the mask is larger than that supported by the system, right? Therefore is this not essentially a check that the mask is appropriately small, whilst swiotlb_dma_supported() checks that the mask is appropriately large?

I'm struggling to understand how it follows that this function is pointless given the behaviour of swiotlb_dma_supported(), which is what the commit message suggests.

Thanks,
Paul

Quoted 19 lines

arch/mips/loongson64/common/dma-swiotlb.c +1 -4

-	return swiotlb_dma_supported(dev, mask);
-}
-
 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
 	long nid;

@@ -99,7 +92,7 @@ static const struct dma_map_ops loongson_dma_map_ops = {
 	.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
 	.sync_sg_for_device = loongson_dma_sync_sg_for_device,
 	.mapping_error = swiotlb_dma_mapping_error,
-	.dma_supported = loongson_dma_supported,
+	.dma_supported = swiotlb_dma_supported,
 };
 
 void __init plat_swiotlb_setup(void)

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #13 lore raw

PATCH 7/25 MIPS: consolidate the swiotlb implementations

In reply to a message not in the archive

Octeon and Loongson share exactly the same code, move it into a common implementation, and use that implementation directly from get_arch_dma_ops.

Also provide the expected dma-direct.h helpers directly instead of delegating to platform dma-coherence.h headers.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/cavium-octeon/dma-octeon.c          | 61 ----------------
 arch/mips/include/asm/dma-direct.h            | 17 ++++-
 arch/mips/include/asm/dma-mapping.h           |  5 ++
 .../asm/mach-cavium-octeon/dma-coherence.h    | 11 ---
 .../asm/mach-loongson64/dma-coherence.h       | 10 ---
 arch/mips/loongson64/common/dma-swiotlb.c     | 71 +------------------
 arch/mips/mm/Makefile                         |  1 +
 arch/mips/mm/dma-swiotlb.c                    | 61 ++++++++++++++++
 8 files changed, 84 insertions(+), 153 deletions(-)
 create mode 100644 arch/mips/mm/dma-swiotlb.c

arch/mips/cavium-octeon/dma-octeon.c +0 ~~-61~~

index 1e68636c9137..939620b90164 100644
@@ -11,7 +11,6 @@
  * Copyright (C) 2010 Cavium Networks, Inc.
  */
 #include <linux/dma-direct.h>
-#include <linux/scatterlist.h>
 #include <linux/bootmem.h>
 #include <linux/swiotlb.h>
 #include <linux/types.h>

@@ -159,49 +158,6 @@ void __init octeon_pci_dma_init(void)
 }
 #endif /* CONFIG_PCI */
 
-static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
-	unsigned long offset, size_t size, enum dma_data_direction direction,
-	unsigned long attrs)
-{
-	dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
-					    direction, attrs);
-	mb();
-
-	return daddr;
-}
-
-static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
-	int nents, enum dma_data_direction direction, unsigned long attrs)
-{
-	int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
-	mb();
-	return r;
-}
-
-static void octeon_dma_sync_single_for_device(struct device *dev,
-	dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
-{
-	swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
-	mb();
-}
-
-static void octeon_dma_sync_sg_for_device(struct device *dev,
-	struct scatterlist *sg, int nelems, enum dma_data_direction direction)
-{
-	swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
-	mb();
-}
-
-static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
-	dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
-	void *ret = swiotlb_alloc(dev, size, dma_handle, gfp, attrs);
-
-	mb();
-
-	return ret;
-}
-
 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
 #ifdef CONFIG_PCI

@@ -220,21 +176,6 @@ phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
 	return daddr;
 }
 
-static const struct dma_map_ops octeon_swiotlb_ops = {
-	.alloc			= octeon_dma_alloc_coherent,
-	.free			= swiotlb_free,
-	.map_page		= octeon_dma_map_page,
-	.unmap_page		= swiotlb_unmap_page,
-	.map_sg			= octeon_dma_map_sg,
-	.unmap_sg		= swiotlb_unmap_sg_attrs,
-	.sync_single_for_cpu	= swiotlb_sync_single_for_cpu,
-	.sync_single_for_device	= octeon_dma_sync_single_for_device,
-	.sync_sg_for_cpu	= swiotlb_sync_sg_for_cpu,
-	.sync_sg_for_device	= octeon_dma_sync_sg_for_device,
-	.mapping_error		= swiotlb_dma_mapping_error,
-	.dma_supported		= swiotlb_dma_supported
-};
-
 char *octeon_swiotlb;
 
 void __init plat_swiotlb_setup(void)

@@ -297,6 +238,4 @@ void __init plat_swiotlb_setup(void)
 
 	if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
 		panic("Cannot allocate SWIOTLB buffer");
-
-	mips_dma_map_ops = &octeon_swiotlb_ops;
 }

arch/mips/include/asm/dma-direct.h +16 -1

index f32f15530aba..b5c240806e1b 100644
@@ -1 +1,16 @@
-#include <asm/dma-coherence.h>
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MIPS_DMA_DIRECT_H
+#define _MIPS_DMA_DIRECT_H 1
+
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+	if (!dev->dma_mask)
+		return false;
+
+	return addr + size - 1 <= *dev->dma_mask;
+}
+
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
+
+#endif /* _MIPS_DMA_DIRECT_H */

arch/mips/include/asm/dma-mapping.h +5 -0

index 886e75a383f2..ebcce3e22297 100644
@@ -11,10 +11,15 @@
 #endif
 
 extern const struct dma_map_ops *mips_dma_map_ops;
+extern const struct dma_map_ops mips_swiotlb_ops;
 
 static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 {
+#ifdef CONFIG_SWIOTLB
+	return &mips_swiotlb_ops;
+#else
 	return mips_dma_map_ops;
+#endif
 }
 
 #define arch_setup_dma_ops arch_setup_dma_ops

arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +0 ~~-11~~

index c5cdeea495f8..c0254c72d97b 100644
@@ -61,17 +61,6 @@ static inline void plat_post_dma_flush(struct device *dev)
 {
 }
 
-static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
-{
-	if (!dev->dma_mask)
-		return false;
-
-	return addr + size - 1 <= *dev->dma_mask;
-}
-
-dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
-phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
-
 extern char *octeon_swiotlb;
 
 #endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */

arch/mips/include/asm/mach-loongson64/dma-coherence.h +0 ~~-10~~

index 64fc44dec0a8..b8825a7d1279 100644
@@ -17,16 +17,6 @@
 
 struct device;
 
-static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
-{
-	if (!dev->dma_mask)
-		return false;
-
-	return addr + size - 1 <= *dev->dma_mask;
-}
-
-extern dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
-extern phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
 static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
 					  size_t size)
 {

arch/mips/loongson64/common/dma-swiotlb.c +1 ~~-70~~

84 lines not on this page · raw message

arch/mips/mm/Makefile +1 -0

index c463bdad45c7..b87e4258fd78 100644
@@ -17,6 +17,7 @@ obj-$(CONFIG_32BIT)		+= ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)		+= pgtable-64.o
 obj-$(CONFIG_HIGHMEM)		+= highmem.o
 obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
+obj-$(CONFIG_SWIOTLB)		+= dma-swiotlb.o
 
 obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_R3000)		+= c-r3k.o tlb-r3k.o

arch/mips/mm/dma-swiotlb.c new file +61 -0

61 lines not on this page · raw message

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #14 lore raw

PATCH 8/25 MIPS: remove the mips_dma_map_ops indirection

In reply to a message not in the archive

And use mips_default_dma_map_ops directly.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/include/asm/dma-mapping.h | 4 ++--
 arch/mips/mm/dma-default.c          | 6 ++----
 2 files changed, 4 insertions(+), 6 deletions(-)

arch/mips/include/asm/dma-mapping.h +2 -2

index ebcce3e22297..f24b052ec740 100644
@@ -10,7 +10,7 @@
 #include <dma-coherence.h>
 #endif
 
-extern const struct dma_map_ops *mips_dma_map_ops;
+extern const struct dma_map_ops mips_default_dma_map_ops;
 extern const struct dma_map_ops mips_swiotlb_ops;
 
 static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)

@@ -18,7 +18,7 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 #ifdef CONFIG_SWIOTLB
 	return &mips_swiotlb_ops;
 #else
-	return mips_dma_map_ops;
+	return &mips_default_dma_map_ops;
 #endif
 }

arch/mips/mm/dma-default.c +2 -4

index f9fef0028ca2..2db6c2a6f964 100644
@@ -384,7 +384,7 @@ static void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 		__dma_sync_virtual(vaddr, size, direction);
 }
 
-static const struct dma_map_ops mips_default_dma_map_ops = {
+const struct dma_map_ops mips_default_dma_map_ops = {
 	.alloc = mips_dma_alloc_coherent,
 	.free = mips_dma_free_coherent,
 	.mmap = mips_dma_mmap,

@@ -399,6 +399,4 @@ static const struct dma_map_ops mips_default_dma_map_ops = {
 	.dma_supported = mips_dma_supported,
 	.cache_sync = mips_dma_cache_sync,
 };
-
-const struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops;
-EXPORT_SYMBOL(mips_dma_map_ops);
+EXPORT_SYMBOL(mips_default_dma_map_ops);

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #15 lore raw

PATCH 9/25 MIPS: make the default mips dma implementation optional

In reply to a message not in the archive

Octeon and loonson64 already don't use it at all, and we're going to migrate more plaforms away from it.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                   | 40 +++++++++++++++++++++++++++++
 arch/mips/include/asm/dma-mapping.h |  4 ++-
 arch/mips/jazz/Kconfig              |  3 +++
 arch/mips/loongson32/Kconfig        |  2 ++
 arch/mips/loongson64/Kconfig        |  2 ++
 arch/mips/mm/Makefile               |  3 ++-
 arch/mips/pic32/Kconfig             |  1 +
 arch/mips/txx9/Kconfig              |  1 +
 arch/mips/vr41xx/Kconfig            |  5 ++++
 9 files changed, 59 insertions(+), 2 deletions(-)

arch/mips/Kconfig +40 -0

index 43bb037301f6..92cc7943d940 100644
@@ -71,6 +71,9 @@ config MIPS
 	select SYSCTL_EXCEPTION_TRACE
 	select VIRT_TO_BUS
 
+config MIPS_DMA_DEFAULT
+	bool
+
 menu "Machine selection"
 
 choice

@@ -92,6 +95,7 @@ config MIPS_GENERIC
 	select IRQ_MIPS_CPU
 	select LIBFDT
 	select MIPS_CPU_SCACHE
+	select MIPS_DMA_DEFAULT
 	select MIPS_GIC
 	select MIPS_L1_CACHE_SHIFT_7
 	select NO_EXCEPT_FILL

@@ -135,6 +139,7 @@ config MIPS_ALCHEMY
 	select CEVT_R4K
 	select CSRC_R4K
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select DMA_MAYBE_COHERENT	# Au1000,1500,1100 aren't, rest is
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -150,6 +155,7 @@ config AR7
 	select CEVT_R4K
 	select CSRC_R4K
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select NO_EXCEPT_FILL
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_MIPS32_R1

@@ -172,6 +178,7 @@ config ATH25
 	select DMA_NONCOHERENT
 	select IRQ_MIPS_CPU
 	select IRQ_DOMAIN
+	select MIPS_DMA_DEFAULT
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -191,6 +198,7 @@ config ATH79
 	select COMMON_CLK
 	select CLKDEV_LOOKUP
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select MIPS_MACHINE
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_HAS_EARLY_PRINTK

@@ -217,6 +225,7 @@ config BMIPS_GENERIC
 	select BCM7120_L2_IRQ
 	select BRCMSTB_L2_IRQ
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select DMA_NONCOHERENT
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN

@@ -247,6 +256,7 @@ config BCM47XX
 	select HW_HAS_PCI
 	select IRQ_MIPS_CPU
 	select SYS_HAS_CPU_MIPS32_R1
+	select MIPS_DMA_DEFAULT
 	select NO_EXCEPT_FILL
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN

@@ -270,6 +280,7 @@ config BCM63XX
 	select SYNC_R4K
 	select DMA_NONCOHERENT
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_HAS_EARLY_PRINTK

@@ -292,6 +303,7 @@ config MIPS_COBALT
 	select I8259
 	select IRQ_MIPS_CPU
 	select IRQ_GT641XX
+	select MIPS_DMA_DEFAULT
 	select PCI_GT64XXX_PCI0
 	select PCI
 	select SYS_HAS_CPU_NEVADA

@@ -312,6 +324,7 @@ config MACH_DECSTATION
 	select CPU_R4000_WORKAROUNDS if 64BIT
 	select CPU_R4400_WORKAROUNDS if 64BIT
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select NO_IOPORT_MAP
 	select IRQ_MIPS_CPU
 	select SYS_HAS_CPU_R3000

@@ -371,6 +384,7 @@ config MACH_INGENIC
 	select SYS_SUPPORTS_ZBOOT_UART16550
 	select DMA_NONCOHERENT
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select PINCTRL
 	select GPIOLIB
 	select COMMON_CLK

@@ -385,6 +399,7 @@ config LANTIQ
 	select IRQ_MIPS_CPU
 	select CEVT_R4K
 	select CSRC_R4K
+	select MIPS_DMA_DEFAULT
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_BIG_ENDIAN

@@ -412,6 +427,7 @@ config LASAT
 	select SYS_HAS_EARLY_PRINTK
 	select HW_HAS_PCI
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select PCI_GT64XXX_PCI0
 	select MIPS_NILE4
 	select R5000_CPU_SCACHE

@@ -458,6 +474,7 @@ config MACH_PISTACHIO
 	select LIBFDT
 	select MFD_SYSCON
 	select MIPS_CPU_SCACHE
+	select MIPS_DMA_DEFAULT
 	select MIPS_GIC
 	select PINCTRL
 	select REGULATOR

@@ -490,6 +507,7 @@ config MIPS_MALTA
 	select GENERIC_ISA_DMA
 	select HAVE_PCSPKR_PLATFORM
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select MIPS_GIC
 	select HW_HAS_PCI
 	select I8253

@@ -546,6 +564,7 @@ config NEC_MARKEINS
 	bool "NEC EMMA2RH Mark-eins board"
 	select SOC_EMMA2RH
 	select HW_HAS_PCI
+	select MIPS_DMA_DEFAULT
 	help
 	  This enables support for the NEC Electronics Mark-eins boards.

@@ -559,12 +578,14 @@ config MACH_VR41XX
 
 config NXP_STB220
 	bool "NXP STB220 board"
+	select MIPS_DMA_DEFAULT
 	select SOC_PNX833X
 	help
 	 Support for NXP Semiconductors STB220 Development Board.
 
 config NXP_STB225
 	bool "NXP 225 board"
+	select MIPS_DMA_DEFAULT
 	select SOC_PNX833X
 	select SOC_PNX8335
 	help

@@ -584,6 +605,7 @@ config PMC_MSP
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_MIPS16
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select SERIAL_8250
 	select SERIAL_8250_CONSOLE
 	select USB_EHCI_BIG_ENDIAN_MMIO

@@ -601,6 +623,7 @@ config RALINK
 	select BOOT_RAW
 	select DMA_NONCOHERENT
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select USE_OF
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_HAS_CPU_MIPS32_R2

@@ -627,6 +650,7 @@ config SGI_IP22
 	select I8259
 	select IP22_CPU_SCACHE
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select GENERIC_ISA_DMA_SUPPORT_BROKEN
 	select SGI_HAS_I8042
 	select SGI_HAS_INDYDOG

@@ -660,6 +684,7 @@ config SGI_IP27
 	select FW_ARC64
 	select BOOT_ELF64
 	select DEFAULT_SGI_PARTITION
+	select MIPS_DMA_DEFAULT
 	select SYS_HAS_EARLY_PRINTK
 	select HW_HAS_PCI
 	select NR_CPUS_DEFAULT_64

@@ -686,6 +711,7 @@ config SGI_IP28
 	select DMA_NONCOHERENT
 	select GENERIC_ISA_DMA_SUPPORT_BROKEN
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select HW_HAS_EISA
 	select I8253
 	select I8259

@@ -722,6 +748,7 @@ config SGI_IP32
 	select DMA_NONCOHERENT
 	select HW_HAS_PCI
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select R5000_CPU_SCACHE
 	select RM7000_CPU_SCACHE
 	select SYS_HAS_CPU_R5000

@@ -736,6 +763,7 @@ config SGI_IP32
 config SIBYTE_CRHINE
 	bool "Sibyte BCM91120C-CRhine"
 	select BOOT_ELF32
+	select MIPS_DMA_DEFAULT
 	select SIBYTE_BCM1120
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -745,6 +773,7 @@ config SIBYTE_CRHINE
 config SIBYTE_CARMEL
 	bool "Sibyte BCM91120x-Carmel"
 	select BOOT_ELF32
+	select MIPS_DMA_DEFAULT
 	select SIBYTE_BCM1120
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -754,6 +783,7 @@ config SIBYTE_CARMEL
 config SIBYTE_CRHONE
 	bool "Sibyte BCM91125C-CRhone"
 	select BOOT_ELF32
+	select MIPS_DMA_DEFAULT
 	select SIBYTE_BCM1125
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -764,6 +794,7 @@ config SIBYTE_CRHONE
 config SIBYTE_RHONE
 	bool "Sibyte BCM91125E-Rhone"
 	select BOOT_ELF32
+	select MIPS_DMA_DEFAULT
 	select SIBYTE_BCM1125H
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -774,6 +805,7 @@ config SIBYTE_SWARM
 	bool "Sibyte BCM91250A-SWARM"
 	select BOOT_ELF32
 	select HAVE_PATA_PLATFORM
+	select MIPS_DMA_DEFAULT
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -786,6 +818,7 @@ config SIBYTE_LITTLESUR
 	bool "Sibyte BCM91250C2-LittleSur"
 	select BOOT_ELF32
 	select HAVE_PATA_PLATFORM
+	select MIPS_DMA_DEFAULT
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -796,6 +829,7 @@ config SIBYTE_LITTLESUR
 config SIBYTE_SENTOSA
 	bool "Sibyte BCM91250E-Sentosa"
 	select BOOT_ELF32
+	select MIPS_DMA_DEFAULT
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -805,6 +839,7 @@ config SIBYTE_SENTOSA
 config SIBYTE_BIGSUR
 	bool "Sibyte BCM91480B-BigSur"
 	select BOOT_ELF32
+	select MIPS_DMA_DEFAULT
 	select NR_CPUS_DEFAULT_4
 	select SIBYTE_BCM1x80
 	select SWAP_IO_SPACE

@@ -835,6 +870,7 @@ config SNI_RM
 	select I8253
 	select I8259
 	select ISA
+	select MIPS_DMA_DEFAULT
 	select SWAP_IO_SPACE if CPU_BIG_ENDIAN
 	select SYS_HAS_CPU_R4X00
 	select SYS_HAS_CPU_R5000

@@ -865,6 +901,7 @@ config MIKROTIK_RB532
 	select DMA_NONCOHERENT
 	select HW_HAS_PCI
 	select IRQ_MIPS_CPU
+	select MIPS_DMA_DEFAULT
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN

@@ -923,6 +960,7 @@ config NLM_XLR_BOARD
 	select SYS_HAS_CPU_XLR
 	select SYS_SUPPORTS_SMP
 	select HW_HAS_PCI
+	select MIPS_DMA_DEFAULT
 	select SWAP_IO_SPACE
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_64BIT_KERNEL

@@ -949,6 +987,7 @@ config NLM_XLP_BOARD
 	select SYS_HAS_CPU_XLP
 	select SYS_SUPPORTS_SMP
 	select HW_HAS_PCI
+	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select PHYS_ADDR_T_64BIT

@@ -974,6 +1013,7 @@ config MIPS_PARAVIRT
 	bool "Para-Virtualized guest system"
 	select CEVT_R4K
 	select CSRC_R4K
+	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN

arch/mips/include/asm/dma-mapping.h +3 -1

index f24b052ec740..eaf3d9054104 100644
@@ -17,8 +17,10 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 {
 #ifdef CONFIG_SWIOTLB
 	return &mips_swiotlb_ops;
-#else
+#elif defined(CONFIG_MIPS_DMA_DEFAULT)
 	return &mips_default_dma_map_ops;
+#else
+	return NULL;
 #endif
 }

arch/mips/jazz/Kconfig +3 -0

index 06838f80a5d7..d3ae3e0356f6 100644
@@ -3,6 +3,7 @@ config ACER_PICA_61
 	bool "Support for Acer PICA 1 chipset"
 	depends on MACH_JAZZ
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	help
 	  This is a machine with a R4400 133/150 MHz CPU. To compile a Linux

@@ -14,6 +15,7 @@ config MIPS_MAGNUM_4000
 	bool "Support for MIPS Magnum 4000"
 	depends on MACH_JAZZ
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	help

@@ -26,6 +28,7 @@ config OLIVETTI_M700
 	bool "Support for Olivetti M700-10"
 	depends on MACH_JAZZ
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	help
 	  This is a machine with a R4000 100 MHz CPU. To compile a Linux

arch/mips/loongson32/Kconfig +2 -0

index 462b126f45aa..7a69a6c0ce22 100644
@@ -10,6 +10,7 @@ config LOONGSON1_LS1B
 	select CSRC_R4K if !MIPS_EXTERNAL_TIMER
 	select SYS_HAS_CPU_LOONGSON1B
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select BOOT_ELF32
 	select IRQ_MIPS_CPU
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -26,6 +27,7 @@ config LOONGSON1_LS1C
 	select CSRC_R4K if !MIPS_EXTERNAL_TIMER
 	select SYS_HAS_CPU_LOONGSON1C
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select BOOT_ELF32
 	select IRQ_MIPS_CPU
 	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/loongson64/Kconfig +2 -0

index c79e6a565572..dbd2a9f9f9a9 100644
@@ -13,6 +13,7 @@ config LEMOTE_FULOONG2E
 	select CSRC_R4K
 	select SYS_HAS_CPU_LOONGSON2E
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select BOOT_ELF32
 	select BOARD_SCACHE
 	select HW_HAS_PCI

@@ -44,6 +45,7 @@ config LEMOTE_MACH2F
 	select CS5536
 	select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select GENERIC_ISA_DMA_SUPPORT_BROKEN
 	select HAVE_CLK
 	select HW_HAS_PCI

arch/mips/mm/Makefile +2 -1

index b87e4258fd78..038bfed34946 100644
@@ -3,7 +3,7 @@
 # Makefile for the Linux/MIPS-specific parts of the memory manager.
 #
 
-obj-y				+= cache.o dma-default.o extable.o fault.o \
+obj-y				+= cache.o extable.o fault.o \
 				   gup.o init.o mmap.o page.o page-funcs.o \
 				   pgtable.o tlbex.o tlbex-fault.o tlb-funcs.o

@@ -17,6 +17,7 @@ obj-$(CONFIG_32BIT)		+= ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)		+= pgtable-64.o
 obj-$(CONFIG_HIGHMEM)		+= highmem.o
 obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
+obj-$(CONFIG_MIPS_DMA_DEFAULT)	+= dma-default.o
 obj-$(CONFIG_SWIOTLB)		+= dma-swiotlb.o
 
 obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o

arch/mips/pic32/Kconfig +1 -0

index e284e89183cc..7feb7359b05b 100644
@@ -11,6 +11,7 @@ config PIC32MZDA
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/txx9/Kconfig +1 -0

index d2509c93f0ee..9dfda3e90348 100644
@@ -16,6 +16,7 @@ config MACH_TX49XX
 config MACH_TXX9
 	bool
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select SWAP_IO_SPACE
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/vr41xx/Kconfig +5 -0

index 992c988b83b0..cc69b2f663fa 100644
@@ -9,6 +9,7 @@ config CASIO_E55
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select ISA
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -19,6 +20,7 @@ config IBM_WORKPAD
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select ISA
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -29,6 +31,7 @@ config TANBAC_TB022X
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select HW_HAS_PCI
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -45,6 +48,7 @@ config VICTOR_MPC30X
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select HW_HAS_PCI
 	select PCI_VR41XX

@@ -56,6 +60,7 @@ config ZAO_CAPCELLA
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
+	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select HW_HAS_PCI
 	select PCI_VR41XX

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #16 lore raw

PATCH 10/25 MIPS: Octeon: remove mips dma-default stubs

In reply to a message not in the archive

Octeon doesn't use the dma-default code, and now doesn't built it either, so these stubs can be removed.

Signed-off-by Christoph Hellwig <[email protected]>

---
 .../asm/mach-cavium-octeon/dma-coherence.h    | 48 -------------------
 1 file changed, 48 deletions(-)

arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +0 ~~-48~~

index c0254c72d97b..66eee98b8b8d 100644
@@ -4,11 +4,6 @@
  * for more details.
  *
  * Copyright (C) 2006  Ralf Baechle <ralf-6z/[email protected]>
- *
- *
- * Similar to mach-generic/dma-coherence.h except
- * plat_device_is_coherent hard coded to return 1.
- *
  */
 #ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
 #define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H

@@ -18,49 +13,6 @@
 struct device;
 
 extern void octeon_pci_dma_init(void);
-
-static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
-	size_t size)
-{
-	BUG();
-	return 0;
-}
-
-static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
-	struct page *page)
-{
-	BUG();
-	return 0;
-}
-
-static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
-	dma_addr_t dma_addr)
-{
-	BUG();
-	return 0;
-}
-
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
-	size_t size, enum dma_data_direction direction)
-{
-	BUG();
-}
-
-static inline int plat_dma_supported(struct device *dev, u64 mask)
-{
-	BUG();
-	return 0;
-}
-
-static inline int plat_device_is_coherent(struct device *dev)
-{
-	return 1;
-}
-
-static inline void plat_post_dma_flush(struct device *dev)
-{
-}
-
 extern char *octeon_swiotlb;
 
 #endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #17 lore raw

PATCH 11/25 MIPS: Octeon: move swiotlb declarations out of dma-coherence.h

In reply to a message not in the archive

No need to pull them into a global header.

Signed-off-by Christoph Hellwig <[email protected]>

---
 .../asm/mach-cavium-octeon/dma-coherence.h     | 18 ------------------
 arch/mips/include/asm/octeon/pci-octeon.h      |  3 +++
 arch/mips/pci/pci-octeon.c                     |  2 --
 arch/mips/pci/pcie-octeon.c                    |  2 --
 4 files changed, 3 insertions(+), 22 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h

arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h deleted +0 ~~-18~~

deleted file mode 100644
index 66eee98b8b8d..000000000000
@@ -1,18 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006  Ralf Baechle <ralf-6z/[email protected]>
- */
-#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
-#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
-
-#include <linux/bug.h>
-
-struct device;
-
-extern void octeon_pci_dma_init(void);
-extern char *octeon_swiotlb;
-
-#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */

arch/mips/include/asm/octeon/pci-octeon.h +3 -0

index 1884609741a8..b12d9a3fbfb6 100644
@@ -63,4 +63,7 @@ enum octeon_dma_bar_type {
  */
 extern enum octeon_dma_bar_type octeon_dma_bar_type;
 
+void octeon_pci_dma_init(void);
+extern char *octeon_swiotlb;
+
 #endif

arch/mips/pci/pci-octeon.c +0 -2

index a20697df3539..5017d5843c5a 100644
@@ -21,8 +21,6 @@
 #include <asm/octeon/cvmx-pci-defs.h>
 #include <asm/octeon/pci-octeon.h>
 
-#include <dma-coherence.h>
-
 #define USE_OCTEON_INTERNAL_ARBITER
 
 /*

arch/mips/pci/pcie-octeon.c +0 -2

index 87ba86bd8696..9cc5905860ef 100644
@@ -94,8 +94,6 @@ union cvmx_pcie_address {
 
 static int cvmx_pcie_rc_initialize(int pcie_port);
 
-#include <dma-coherence.h>
-
 /**
  * Return the Core virtual base address for PCIe IO access. IOs are
  * read/written as an offset from this address.

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:20 UTC #18 lore raw

PATCH 12/25 MIPS: loongson: untangle dma implementations

In reply to a message not in the archive

Only loongson-3 is DMA coherent and uses swiotlb. So move the dma address translations stubs directly to the loongson-3 code, and remove a few Kconfig indirections.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                                |  2 +-
 arch/mips/loongson64/Kconfig                     |  5 -----
 arch/mips/loongson64/common/Makefile             |  5 -----
 arch/mips/loongson64/loongson-3/Makefile         |  2 +-
 .../{common/dma-swiotlb.c => loongson-3/dma.c}   | 16 ++++------------
 5 files changed, 6 insertions(+), 24 deletions(-)
 rename arch/mips/loongson64/{common/dma-swiotlb.c => loongson-3/dma.c} (68%)

arch/mips/Kconfig +1 -1

index 92cc7943d940..24cc20ea60b9 100644
@@ -448,7 +448,6 @@ config MACH_LOONGSON32
 
 config MACH_LOONGSON64
 	bool "Loongson-2/3 family of machines"
-	select ARCH_HAS_PHYS_TO_DMA
 	select SYS_SUPPORTS_ZBOOT
 	help
 	  This enables the support of Loongson-2/3 family of machines.

@@ -1383,6 +1382,7 @@ choice
 config CPU_LOONGSON3
 	bool "Loongson 3 CPU"
 	depends on SYS_HAS_CPU_LOONGSON3
+	select ARCH_HAS_PHYS_TO_DMA
 	select CPU_SUPPORTS_64BIT_KERNEL
 	select CPU_SUPPORTS_HIGHMEM
 	select CPU_SUPPORTS_HUGEPAGES

arch/mips/loongson64/Kconfig +0 -5

index dbd2a9f9f9a9..a785bf8da3f3 100644
@@ -93,7 +93,6 @@ config LOONGSON_MACH3X
 	select LOONGSON_MC146818
 	select ZONE_DMA32
 	select LEFI_FIRMWARE_INTERFACE
-	select PHYS48_TO_HT40
 	help
 		Generic Loongson 3 family machines utilize the 3A/3B revision
 		of Loongson processor and RS780/SBX00 chipset.

@@ -132,10 +131,6 @@ config LOONGSON_UART_BASE
 	default y
 	depends on EARLY_PRINTK || SERIAL_8250
 
-config PHYS48_TO_HT40
-	bool
-	default y if CPU_LOONGSON3
-
 config LOONGSON_MC146818
 	bool
 	default n

arch/mips/loongson64/common/Makefile +0 -5

index 8235ac7eac95..684624f61f5a 100644
@@ -25,8 +25,3 @@ obj-$(CONFIG_CS5536) += cs5536/
 #
 
 obj-$(CONFIG_SUSPEND) += pm.o
-
-#
-# Big Memory (SWIOTLB) Support
-#
-obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o

arch/mips/loongson64/loongson-3/Makefile +1 -1

index 44bc1482158b..b5a0c2fa5446 100644
@@ -1,7 +1,7 @@
 #
 # Makefile for Loongson-3 family machines
 #
-obj-y			+= irq.o cop2-ex.o platform.o acpi_init.o
+obj-y			+= irq.o cop2-ex.o platform.o acpi_init.o dma.o
 
 obj-$(CONFIG_SMP)	+= smp.o

arch/mips/loongson64/loongson-3/dma.c renamed from arch/mips/loongson64/common/dma-swiotlb.c +4 ~~-12~~

similarity index 68%
rename from arch/mips/loongson64/common/dma-swiotlb.c
rename to arch/mips/loongson64/loongson-3/dma.c
index a4f554bf1232..5e86635f71db 100644
@@ -5,26 +5,18 @@
 
 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
-	long nid;
-#ifdef CONFIG_PHYS48_TO_HT40
 	/* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from
 	 * Loongson-3's 48bit address space and embed it into 40bit */
-	nid = (paddr >> 44) & 0x3;
-	paddr = ((nid << 44) ^ paddr) | (nid << 37);
-#endif
-	return paddr;
+	long nid = (paddr >> 44) & 0x3;
+	return ((nid << 44) ^ paddr) | (nid << 37);
 }
 
 phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
 {
-	long nid;
-#ifdef CONFIG_PHYS48_TO_HT40
 	/* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from
 	 * Loongson-3's 48bit address space and embed it into 40bit */
-	nid = (daddr >> 37) & 0x3;
-	daddr = ((nid << 37) ^ daddr) | (nid << 44);
-#endif
-	return daddr;
+	long nid = (daddr >> 37) & 0x3;
+	return ((nid << 37) ^ daddr) | (nid << 44);
 }
 
 void __init plat_swiotlb_setup(void)

Signature · 1 line

2.17.0

A message that is not in the archive (sent off-list or not yet received): [email protected]

Maciej W. Rozycki

2018-07-11 12:46 UTC #20 lore raw

Re: [PATCH 12/25] MIPS: loongson: untangle dma implementations

Quoted 3 lines · Christoph Hellwig

Only loongson-3 is DMA coherent and uses swiotlb. So move the dma address translations stubs directly to the loongson-3 code, and remove a few Kconfig indirections.

SiByte should too though, at least for those boards, such as the SWARM
and the BigSur, that can have DRAM over 4GiB (and 32-bit PCI devices plugged).

I never got to have the wiring of swiotlb completed for these boards as
I got distracted with getting set up to debug a DRAM controller issue observed in the form of memory data corruption with the banks fully populated (which might have to do something with the parameters of bank interleaving enabled in such a configuration, as replacing a single module with a smaller-sized one and therefore disabling interleaving, which can only work with all modules being the same size, makes the problem go away).

FWIW,

Maciej

A message that is not in the archive (sent off-list or not yet received): alpine.DEB.2.00.1807110407510.30992-AURtyoD2VtPP6B53oEZunQ@public.gmane.org

Christoph Hellwig

author

2018-07-11 12:55 UTC #22 lore raw

Re: [PATCH 12/25] MIPS: loongson: untangle dma implementations

Quoted 7 lines · Maciej W. Rozycki

Quoted 3 lines
Only loongson-3 is DMA coherent and uses swiotlb. So move the dma address translations stubs directly to the loongson-3 code, and remove a few Kconfig indirections.
SiByte should too though, at least for those boards, such as the SWARM
and the BigSur, that can have DRAM over 4GiB (and 32-bit PCI devices plugged).

Only in this case refers to loonson boards.

Quoted 8 lines

I never got to have the wiring of swiotlb completed for these boards as
I got distracted with getting set up to debug a DRAM controller issue observed in the form of memory data corruption with the banks fully populated (which might have to do something with the parameters of bank interleaving enabled in such a configuration, as replacing a single module with a smaller-sized one and therefore disabling interleaving, which can only work with all modules being the same size, makes the problem go away).

After this series enabling swiotlb for another board is trivial as all the code has been consolidated. Just select SWIOTLB and add a call to swiotlb_init to the board setup code.

Quoted 4 lines

FWIW,
Maciej

---end quoted text---

A message that is not in the archive (sent off-list or not yet received): [email protected]

Maciej W. Rozycki

2018-07-11 13:21 UTC #24 lore raw

Re: [PATCH 12/25] MIPS: loongson: untangle dma implementations

Quoted 5 lines · Christoph Hellwig

Quoted 3 lines
SiByte should too though, at least for those boards, such as the SWARM
and the BigSur, that can have DRAM over 4GiB (and 32-bit PCI devices plugged).
Only in this case refers to loonson boards.

Right!

Quoted 9 lines

Quoted 8 lines
I never got to have the wiring of swiotlb completed for these boards as
I got distracted with getting set up to debug a DRAM controller issue observed in the form of memory data corruption with the banks fully populated (which might have to do something with the parameters of bank interleaving enabled in such a configuration, as replacing a single module with a smaller-sized one and therefore disabling interleaving, which can only work with all modules being the same size, makes the problem go away).

Quoted 3 lines

After this series enabling swiotlb for another board is trivial as all the code has been consolidated. Just select SWIOTLB and add a call to swiotlb_init to the board setup code.

I had that feeling too, thanks for confirming. And for doing this work
in the first place!

Maciej

Christoph Hellwig

author

2018-05-25 09:20 UTC #25 lore raw

PATCH 13/25 MIPS: loongson: remove loongson-3 handling from dma-coherence.h

In reply to a message not in the archive

Loongson3 is dma coherent and uses swiotlb, so it will never used any of these helpers.

Signed-off-by Christoph Hellwig <[email protected]>

---
 .../include/asm/mach-loongson64/dma-coherence.h  | 16 +---------------
 1 file changed, 1 insertion(+), 15 deletions(-)

arch/mips/include/asm/mach-loongson64/dma-coherence.h +1 ~~-15~~

index b8825a7d1279..651dd2eb3ee5 100644
@@ -20,29 +20,19 @@ struct device;
 static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
 					  size_t size)
 {
-#ifdef CONFIG_CPU_LOONGSON3
-	return __phys_to_dma(dev, virt_to_phys(addr));
-#else
 	return virt_to_phys(addr) | 0x80000000;
-#endif
 }
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
 					       struct page *page)
 {
-#ifdef CONFIG_CPU_LOONGSON3
-	return __phys_to_dma(dev, page_to_phys(page));
-#else
 	return page_to_phys(page) | 0x80000000;
-#endif
 }
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
 	dma_addr_t dma_addr)
 {
-#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT)
-	return __dma_to_phys(dev, dma_addr);
-#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
+#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
 	return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
 #else
 	return dma_addr & 0x7fffffff;

@@ -69,11 +59,7 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
 
 static inline int plat_device_is_coherent(struct device *dev)
 {
-#ifdef CONFIG_DMA_NONCOHERENT
 	return 0;
-#else
-	return 1;
-#endif /* CONFIG_DMA_NONCOHERENT */
 }
 
 static inline void plat_post_dma_flush(struct device *dev)

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #26 lore raw

PATCH 14/25 MIPS: use dma_direct_ops for coherent I/O

In reply to a message not in the archive

Switch the simple cache coherent architectures that don't require any DMA address translation to dma_direct_ops.

We'll soon use at least parts of the direct DMA ops implementation for all platforms, so select the symbol globally.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                   | 15 +--------------
 arch/mips/include/asm/dma-mapping.h |  2 +-
 2 files changed, 2 insertions(+), 15 deletions(-)

arch/mips/Kconfig +1 ~~-14~~

index 24cc20ea60b9..173e5714151c 100644
@@ -16,6 +16,7 @@ config MIPS
 	select BUILDTIME_EXTABLE_SORT
 	select CLONE_BACKWARDS
 	select CPU_PM if CPU_IDLE
+	select DMA_DIRECT_OPS
 	select GENERIC_ATOMIC64 if !64BIT
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_CMOS_UPDATE

@@ -563,7 +564,6 @@ config NEC_MARKEINS
 	bool "NEC EMMA2RH Mark-eins board"
 	select SOC_EMMA2RH
 	select HW_HAS_PCI
-	select MIPS_DMA_DEFAULT
 	help
 	  This enables support for the NEC Electronics Mark-eins boards.

@@ -577,14 +577,12 @@ config MACH_VR41XX
 
 config NXP_STB220
 	bool "NXP STB220 board"
-	select MIPS_DMA_DEFAULT
 	select SOC_PNX833X
 	help
 	 Support for NXP Semiconductors STB220 Development Board.
 
 config NXP_STB225
 	bool "NXP 225 board"
-	select MIPS_DMA_DEFAULT
 	select SOC_PNX833X
 	select SOC_PNX8335
 	help

@@ -762,7 +760,6 @@ config SGI_IP32
 config SIBYTE_CRHINE
 	bool "Sibyte BCM91120C-CRhine"
 	select BOOT_ELF32
-	select MIPS_DMA_DEFAULT
 	select SIBYTE_BCM1120
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -772,7 +769,6 @@ config SIBYTE_CRHINE
 config SIBYTE_CARMEL
 	bool "Sibyte BCM91120x-Carmel"
 	select BOOT_ELF32
-	select MIPS_DMA_DEFAULT
 	select SIBYTE_BCM1120
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -782,7 +778,6 @@ config SIBYTE_CARMEL
 config SIBYTE_CRHONE
 	bool "Sibyte BCM91125C-CRhone"
 	select BOOT_ELF32
-	select MIPS_DMA_DEFAULT
 	select SIBYTE_BCM1125
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -793,7 +788,6 @@ config SIBYTE_CRHONE
 config SIBYTE_RHONE
 	bool "Sibyte BCM91125E-Rhone"
 	select BOOT_ELF32
-	select MIPS_DMA_DEFAULT
 	select SIBYTE_BCM1125H
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -804,7 +798,6 @@ config SIBYTE_SWARM
 	bool "Sibyte BCM91250A-SWARM"
 	select BOOT_ELF32
 	select HAVE_PATA_PLATFORM
-	select MIPS_DMA_DEFAULT
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -817,7 +810,6 @@ config SIBYTE_LITTLESUR
 	bool "Sibyte BCM91250C2-LittleSur"
 	select BOOT_ELF32
 	select HAVE_PATA_PLATFORM
-	select MIPS_DMA_DEFAULT
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -828,7 +820,6 @@ config SIBYTE_LITTLESUR
 config SIBYTE_SENTOSA
 	bool "Sibyte BCM91250E-Sentosa"
 	select BOOT_ELF32
-	select MIPS_DMA_DEFAULT
 	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1

@@ -838,7 +829,6 @@ config SIBYTE_SENTOSA
 config SIBYTE_BIGSUR
 	bool "Sibyte BCM91480B-BigSur"
 	select BOOT_ELF32
-	select MIPS_DMA_DEFAULT
 	select NR_CPUS_DEFAULT_4
 	select SIBYTE_BCM1x80
 	select SWAP_IO_SPACE

@@ -959,7 +949,6 @@ config NLM_XLR_BOARD
 	select SYS_HAS_CPU_XLR
 	select SYS_SUPPORTS_SMP
 	select HW_HAS_PCI
-	select MIPS_DMA_DEFAULT
 	select SWAP_IO_SPACE
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_64BIT_KERNEL

@@ -986,7 +975,6 @@ config NLM_XLP_BOARD
 	select SYS_HAS_CPU_XLP
 	select SYS_SUPPORTS_SMP
 	select HW_HAS_PCI
-	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select PHYS_ADDR_T_64BIT

@@ -1012,7 +1000,6 @@ config MIPS_PARAVIRT
 	bool "Para-Virtualized guest system"
 	select CEVT_R4K
 	select CSRC_R4K
-	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN

arch/mips/include/asm/dma-mapping.h +1 -1

index eaf3d9054104..7c0d4f0ccaa0 100644
@@ -20,7 +20,7 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 #elif defined(CONFIG_MIPS_DMA_DEFAULT)
 	return &mips_default_dma_map_ops;
 #else
-	return NULL;
+	return &dma_direct_ops;
 #endif
 }

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #27 lore raw

PATCH 15/25 MIPS: IP27: use dma_direct_ops

In reply to a message not in the archive

IP27 is coherent and has a reasonably direct mapping, just with a little per-bus offset added into the dma address.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                             |  2 +-
 .../include/asm/mach-ip27/dma-coherence.h     | 70 -------------------
 arch/mips/pci/pci-ip27.c                      | 14 ++++
 3 files changed, 15 insertions(+), 71 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-ip27/dma-coherence.h

arch/mips/Kconfig +1 -1

index 173e5714151c..934696595ad6 100644
@@ -677,11 +677,11 @@ config SGI_IP22
 
 config SGI_IP27
 	bool "SGI IP27 (Origin200/2000)"
+	select ARCH_HAS_PHYS_TO_DMA
 	select FW_ARC
 	select FW_ARC64
 	select BOOT_ELF64
 	select DEFAULT_SGI_PARTITION
-	select MIPS_DMA_DEFAULT
 	select SYS_HAS_EARLY_PRINTK
 	select HW_HAS_PCI
 	select NR_CPUS_DEFAULT_64

arch/mips/include/asm/mach-ip27/dma-coherence.h deleted +0 ~~-70~~

70 lines not on this page · raw message

arch/mips/pci/pci-ip27.c +14 -0

index 0f09eafa5e3a..65b48d41a229 100644
@@ -11,6 +11,7 @@
 #include <linux/export.h>
 #include <linux/pci.h>
 #include <linux/smp.h>
+#include <linux/dma-direct.h>
 #include <asm/sn/arch.h>
 #include <asm/pci/bridge.h>
 #include <asm/paccess.h>

@@ -182,6 +183,19 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 	return 0;
 }
 
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
+
+	return bc->baddr + paddr;
+}
+
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
+	return dma_addr & ~(0xffUL << 56);
+}
+
 /*
  * Device might live on a subordinate PCI bus.	XXX Walk up the chain of buses
  * to find the slot number in sense of the bridge device register.

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #28 lore raw

PATCH 16/25 MIPS: move coherentio setup to setup.c

In reply to a message not in the archive

We want to be able to use it even when not building dma-default.c in the near future.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/kernel/setup.c   | 24 ++++++++++++++++++++++++
 arch/mips/mm/dma-default.c | 23 -----------------------
 2 files changed, 24 insertions(+), 23 deletions(-)

arch/mips/kernel/setup.c +24 -0

index 563188ac6fa2..8dc72797d5cb 100644
@@ -36,6 +36,7 @@
 #include <asm/cdmm.h>
 #include <asm/cpu.h>
 #include <asm/debug.h>
+#include <asm/dma-coherence.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/smp-ops.h>

@@ -1055,3 +1056,26 @@ static int __init debugfs_mips(void)
 }
 arch_initcall(debugfs_mips);
 #endif
+
+#if defined(CONFIG_DMA_MAYBE_COHERENT) && !defined(CONFIG_DMA_PERDEV_COHERENT)
+/* User defined DMA coherency from command line. */
+enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;
+EXPORT_SYMBOL_GPL(coherentio);
+int hw_coherentio = 0;	/* Actual hardware supported DMA coherency setting. */
+
+static int __init setcoherentio(char *str)
+{
+	coherentio = IO_COHERENCE_ENABLED;
+	pr_info("Hardware DMA cache coherency (command line)\n");
+	return 0;
+}
+early_param("coherentio", setcoherentio);
+
+static int __init setnocoherentio(char *str)
+{
+	coherentio = IO_COHERENCE_DISABLED;
+	pr_info("Software DMA cache coherency (command line)\n");
+	return 0;
+}
+early_param("nocoherentio", setnocoherentio);
+#endif

arch/mips/mm/dma-default.c +0 ~~-23~~

index 2db6c2a6f964..10b56e8a2076 100644
@@ -24,29 +24,6 @@
 
 #include <dma-coherence.h>
 
-#if defined(CONFIG_DMA_MAYBE_COHERENT) && !defined(CONFIG_DMA_PERDEV_COHERENT)
-/* User defined DMA coherency from command line. */
-enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;
-EXPORT_SYMBOL_GPL(coherentio);
-int hw_coherentio = 0;	/* Actual hardware supported DMA coherency setting. */
-
-static int __init setcoherentio(char *str)
-{
-	coherentio = IO_COHERENCE_ENABLED;
-	pr_info("Hardware DMA cache coherency (command line)\n");
-	return 0;
-}
-early_param("coherentio", setcoherentio);
-
-static int __init setnocoherentio(char *str)
-{
-	coherentio = IO_COHERENCE_DISABLED;
-	pr_info("Software DMA cache coherency (command line)\n");
-	return 0;
-}
-early_param("nocoherentio", setnocoherentio);
-#endif
-
 static inline struct page *dma_addr_to_page(struct device *dev,
 	dma_addr_t dma_addr)
 {

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #29 lore raw

PATCH 17/25 MIPS: use generic dma noncoherent ops for simple noncoherent platforms

In reply to a message not in the archive

Convert everything not overriding dma-coherence.h to the generic noncoherent ops. The new dma-noncoherent.c file duplicates a lot of the code in dma-default.c, but that file will be gone by the end of this series.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                   |  24 +---
 arch/mips/include/asm/dma-mapping.h |   2 +
 arch/mips/loongson32/Kconfig        |   2 -
 arch/mips/mm/Makefile               |   1 +
 arch/mips/mm/dma-noncoherent.c      | 208 ++++++++++++++++++++++++++++
 arch/mips/pic32/Kconfig             |   1 -
 arch/mips/txx9/Kconfig              |   1 -
 arch/mips/vr41xx/Kconfig            |   5 -
 8 files changed, 216 insertions(+), 28 deletions(-)
 create mode 100644 arch/mips/mm/dma-noncoherent.c

arch/mips/Kconfig +5 ~~-19~~

index 934696595ad6..b39b430c92a3 100644
@@ -96,7 +96,6 @@ config MIPS_GENERIC
 	select IRQ_MIPS_CPU
 	select LIBFDT
 	select MIPS_CPU_SCACHE
-	select MIPS_DMA_DEFAULT
 	select MIPS_GIC
 	select MIPS_L1_CACHE_SHIFT_7
 	select NO_EXCEPT_FILL

@@ -140,7 +139,6 @@ config MIPS_ALCHEMY
 	select CEVT_R4K
 	select CSRC_R4K
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select DMA_MAYBE_COHERENT	# Au1000,1500,1100 aren't, rest is
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -156,7 +154,6 @@ config AR7
 	select CEVT_R4K
 	select CSRC_R4K
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select NO_EXCEPT_FILL
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_MIPS32_R1

@@ -199,7 +196,6 @@ config ATH79
 	select COMMON_CLK
 	select CLKDEV_LOOKUP
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select MIPS_MACHINE
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_HAS_EARLY_PRINTK

@@ -257,7 +253,6 @@ config BCM47XX
 	select HW_HAS_PCI
 	select IRQ_MIPS_CPU
 	select SYS_HAS_CPU_MIPS32_R1
-	select MIPS_DMA_DEFAULT
 	select NO_EXCEPT_FILL
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN

@@ -281,7 +276,6 @@ config BCM63XX
 	select SYNC_R4K
 	select DMA_NONCOHERENT
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_HAS_EARLY_PRINTK

@@ -304,7 +298,6 @@ config MIPS_COBALT
 	select I8259
 	select IRQ_MIPS_CPU
 	select IRQ_GT641XX
-	select MIPS_DMA_DEFAULT
 	select PCI_GT64XXX_PCI0
 	select PCI
 	select SYS_HAS_CPU_NEVADA

@@ -325,7 +318,6 @@ config MACH_DECSTATION
 	select CPU_R4000_WORKAROUNDS if 64BIT
 	select CPU_R4400_WORKAROUNDS if 64BIT
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select NO_IOPORT_MAP
 	select IRQ_MIPS_CPU
 	select SYS_HAS_CPU_R3000

@@ -385,7 +377,6 @@ config MACH_INGENIC
 	select SYS_SUPPORTS_ZBOOT_UART16550
 	select DMA_NONCOHERENT
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select PINCTRL
 	select GPIOLIB
 	select COMMON_CLK

@@ -400,7 +391,6 @@ config LANTIQ
 	select IRQ_MIPS_CPU
 	select CEVT_R4K
 	select CSRC_R4K
-	select MIPS_DMA_DEFAULT
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_BIG_ENDIAN

@@ -428,7 +418,6 @@ config LASAT
 	select SYS_HAS_EARLY_PRINTK
 	select HW_HAS_PCI
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select PCI_GT64XXX_PCI0
 	select MIPS_NILE4
 	select R5000_CPU_SCACHE

@@ -474,7 +463,6 @@ config MACH_PISTACHIO
 	select LIBFDT
 	select MFD_SYSCON
 	select MIPS_CPU_SCACHE
-	select MIPS_DMA_DEFAULT
 	select MIPS_GIC
 	select PINCTRL
 	select REGULATOR

@@ -507,7 +495,6 @@ config MIPS_MALTA
 	select GENERIC_ISA_DMA
 	select HAVE_PCSPKR_PLATFORM
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select MIPS_GIC
 	select HW_HAS_PCI
 	select I8253

@@ -602,7 +589,6 @@ config PMC_MSP
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_MIPS16
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select SERIAL_8250
 	select SERIAL_8250_CONSOLE
 	select USB_EHCI_BIG_ENDIAN_MMIO

@@ -620,7 +606,6 @@ config RALINK
 	select BOOT_RAW
 	select DMA_NONCOHERENT
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select USE_OF
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_HAS_CPU_MIPS32_R2

@@ -647,7 +632,6 @@ config SGI_IP22
 	select I8259
 	select IP22_CPU_SCACHE
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select GENERIC_ISA_DMA_SUPPORT_BROKEN
 	select SGI_HAS_I8042
 	select SGI_HAS_INDYDOG

@@ -708,7 +692,6 @@ config SGI_IP28
 	select DMA_NONCOHERENT
 	select GENERIC_ISA_DMA_SUPPORT_BROKEN
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select HW_HAS_EISA
 	select I8253
 	select I8259

@@ -859,7 +842,6 @@ config SNI_RM
 	select I8253
 	select I8259
 	select ISA
-	select MIPS_DMA_DEFAULT
 	select SWAP_IO_SPACE if CPU_BIG_ENDIAN
 	select SYS_HAS_CPU_R4X00
 	select SYS_HAS_CPU_R5000

@@ -890,7 +872,6 @@ config MIKROTIK_RB532
 	select DMA_NONCOHERENT
 	select HW_HAS_PCI
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN

@@ -1127,7 +1108,12 @@ config DMA_PERDEV_COHERENT
 
 config DMA_NONCOHERENT
 	bool
+	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
+	select ARCH_HAS_SYNC_DMA_FOR_CPU
 	select NEED_DMA_MAP_STATE
+	select DMA_NONCOHERENT_MMAP
+	select DMA_NONCOHERENT_CACHE_SYNC
+	select DMA_NONCOHERENT_OPS if !MIPS_DMA_DEFAULT
 
 config SYS_HAS_EARLY_PRINTK
 	bool

arch/mips/include/asm/dma-mapping.h +2 -0

index 7c0d4f0ccaa0..e32a7b439816 100644
@@ -19,6 +19,8 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 	return &mips_swiotlb_ops;
 #elif defined(CONFIG_MIPS_DMA_DEFAULT)
 	return &mips_default_dma_map_ops;
+#elif defined(CONFIG_DMA_NONCOHERENT_OPS)
+	return &dma_noncoherent_ops;
 #else
 	return &dma_direct_ops;
 #endif

arch/mips/loongson32/Kconfig +0 -2

index 7a69a6c0ce22..462b126f45aa 100644
@@ -10,7 +10,6 @@ config LOONGSON1_LS1B
 	select CSRC_R4K if !MIPS_EXTERNAL_TIMER
 	select SYS_HAS_CPU_LOONGSON1B
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select BOOT_ELF32
 	select IRQ_MIPS_CPU
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -27,7 +26,6 @@ config LOONGSON1_LS1C
 	select CSRC_R4K if !MIPS_EXTERNAL_TIMER
 	select SYS_HAS_CPU_LOONGSON1C
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select BOOT_ELF32
 	select IRQ_MIPS_CPU
 	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/mm/Makefile +1 -0

index 038bfed34946..c6146c3805dc 100644
@@ -18,6 +18,7 @@ obj-$(CONFIG_64BIT)		+= pgtable-64.o
 obj-$(CONFIG_HIGHMEM)		+= highmem.o
 obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
 obj-$(CONFIG_MIPS_DMA_DEFAULT)	+= dma-default.o
+obj-$(CONFIG_DMA_NONCOHERENT)	+= dma-noncoherent.o
 obj-$(CONFIG_SWIOTLB)		+= dma-swiotlb.o
 
 obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o

arch/mips/mm/dma-noncoherent.c new file +208 -0

208 lines not on this page · raw message

arch/mips/pic32/Kconfig +0 -1

index 7feb7359b05b..e284e89183cc 100644
@@ -11,7 +11,6 @@ config PIC32MZDA
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/txx9/Kconfig +0 -1

index 9dfda3e90348..d2509c93f0ee 100644
@@ -16,7 +16,6 @@ config MACH_TX49XX
 config MACH_TXX9
 	bool
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select SWAP_IO_SPACE
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/vr41xx/Kconfig +0 -5

index cc69b2f663fa..992c988b83b0 100644
@@ -9,7 +9,6 @@ config CASIO_E55
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select ISA
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -20,7 +19,6 @@ config IBM_WORKPAD
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select ISA
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -31,7 +29,6 @@ config TANBAC_TB022X
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select HW_HAS_PCI
 	select SYS_SUPPORTS_32BIT_KERNEL

@@ -48,7 +45,6 @@ config VICTOR_MPC30X
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select HW_HAS_PCI
 	select PCI_VR41XX

@@ -60,7 +56,6 @@ config ZAO_CAPCELLA
 	select CEVT_R4K
 	select CSRC_R4K
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select IRQ_MIPS_CPU
 	select HW_HAS_PCI
 	select PCI_VR41XX

Signature · 6 lines

2.17.0

_______________________________________________
iommu mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/iommu

Christoph Hellwig

author

2018-05-25 09:21 UTC #30 lore raw

PATCH 18/25 MIPS: loongson64: use generic dma noncoherent ops

In reply to a message not in the archive

Provide phys_to_dma/dma_to_phys helpers, everything else is generic.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                             |  1 +
 .../asm/mach-loongson64/dma-coherence.h       | 69 -------------------
 arch/mips/loongson64/Kconfig                  |  2 -
 arch/mips/loongson64/common/Makefile          |  1 +
 arch/mips/loongson64/common/dma.c             | 16 +++++
 5 files changed, 18 insertions(+), 71 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-loongson64/dma-coherence.h
 create mode 100644 arch/mips/loongson64/common/dma.c

arch/mips/Kconfig +1 -0

index b39b430c92a3..3140955bc77c 100644
@@ -1822,6 +1822,7 @@ config CPU_LOONGSON2
 	select CPU_SUPPORTS_64BIT_KERNEL
 	select CPU_SUPPORTS_HIGHMEM
 	select CPU_SUPPORTS_HUGEPAGES
+	select ARCH_HAS_PHYS_TO_DMA
 
 config CPU_LOONGSON1
 	bool

arch/mips/include/asm/mach-loongson64/dma-coherence.h deleted +0 ~~-69~~

69 lines not on this page · raw message

arch/mips/loongson64/Kconfig +0 -2

index a785bf8da3f3..c865b4b9b775 100644
@@ -13,7 +13,6 @@ config LEMOTE_FULOONG2E
 	select CSRC_R4K
 	select SYS_HAS_CPU_LOONGSON2E
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select BOOT_ELF32
 	select BOARD_SCACHE
 	select HW_HAS_PCI

@@ -45,7 +44,6 @@ config LEMOTE_MACH2F
 	select CS5536
 	select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select GENERIC_ISA_DMA_SUPPORT_BROKEN
 	select HAVE_CLK
 	select HW_HAS_PCI

arch/mips/loongson64/common/Makefile +1 -0

index 684624f61f5a..57ee03022941 100644
@@ -6,6 +6,7 @@
 obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
     bonito-irq.o mem.o machtype.o platform.o serial.o
 obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_CPU_LOONGSON2) += dma.o
 
 #
 # Serial port support

arch/mips/loongson64/common/dma.c new file +16 -0

new file mode 100644
index 000000000000..95ede4b0fbbb
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/dma-direct.h>
+
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+	return paddr | 0x80000000;
+}
+
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
+#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
+	if (dma_addr > 0x8fffffff)
+		return dma_addr;
+#endif
+	return dma_addr & 0x0fffffff;
+}

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #31 lore raw

PATCH 19/25 MIPS: IP32: use generic dma noncoherent ops

In reply to a message not in the archive

Provide phys_to_dma/dma_to_phys helpers, everything else is generic.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                             |  2 +-
 .../include/asm/mach-ip32/dma-coherence.h     | 92 -------------------
 arch/mips/sgi-ip32/Makefile                   |  2 +-
 arch/mips/sgi-ip32/ip32-dma.c                 | 37 ++++++++
 4 files changed, 39 insertions(+), 94 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-ip32/dma-coherence.h
 create mode 100644 arch/mips/sgi-ip32/ip32-dma.c

arch/mips/Kconfig +1 -1

index 3140955bc77c..bde16399a8fe 100644
@@ -720,6 +720,7 @@ config SGI_IP28
 
 config SGI_IP32
 	bool "SGI IP32 (O2)"
+	select ARCH_HAS_PHYS_TO_DMA
 	select FW_ARC
 	select FW_ARC32
 	select BOOT_ELF32

@@ -728,7 +729,6 @@ config SGI_IP32
 	select DMA_NONCOHERENT
 	select HW_HAS_PCI
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select R5000_CPU_SCACHE
 	select RM7000_CPU_SCACHE
 	select SYS_HAS_CPU_R5000

arch/mips/include/asm/mach-ip32/dma-coherence.h deleted +0 ~~-92~~

92 lines not on this page · raw message

arch/mips/sgi-ip32/Makefile +1 -1

index 60f0227425e7..4745cd94df11 100644
@@ -4,4 +4,4 @@
 #
 
 obj-y	+= ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \
-	   crime.o ip32-memory.o
+	   crime.o ip32-memory.o ip32-dma.o

arch/mips/sgi-ip32/ip32-dma.c new file +37 -0

new file mode 100644
index 000000000000..fa7b17cb5385
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2006  Ralf Baechle <ralf-6z/[email protected]>
+ */
+#include <linux/dma-direct.h>
+#include <asm/ip32/crime.h>
+
+/*
+ * Few notes.
+ * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
+ * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
+ *    native-endian)
+ * 3. All other devices see memory as one big chunk at 0x40000000
+ * 4. Non-PCI devices will pass NULL as struct device*
+ *
+ * Thus we translate differently, depending on device.
+ */
+
+#define RAM_OFFSET_MASK 0x3fffffffUL
+
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+	dma_addr_t dma_addr = paddr & RAM_OFFSET_MASK;
+
+	if (!dev)
+		dma_addr += CRIME_HI_MEM_BASE;
+	return dma_addr;
+}
+
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
+	phys_addr_t paddr = dma_addr & RAM_OFFSET_MASK;
+
+	if (dma_addr >= 256*1024*1024)
+		paddr += CRIME_HI_MEM_BASE;
+	return paddr;
+}

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #32 lore raw

PATCH 20/25 MIPS: ath25: use generic dma noncoherent ops

In reply to a message not in the archive

Provide phys_to_dma/dma_to_phys helpers only if PCI support is enabled, everything else is generic.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                             |  1 -
 arch/mips/ath25/Kconfig                       |  1 +
 .../include/asm/mach-ath25/dma-coherence.h    | 71 -------------------
 arch/mips/pci/pci-ar2315.c                    | 24 +++++++
 4 files changed, 25 insertions(+), 72 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-ath25/dma-coherence.h

arch/mips/Kconfig +0 -1

index bde16399a8fe..25a3c3262554 100644
@@ -176,7 +176,6 @@ config ATH25
 	select DMA_NONCOHERENT
 	select IRQ_MIPS_CPU
 	select IRQ_DOMAIN
-	select MIPS_DMA_DEFAULT
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_32BIT_KERNEL

arch/mips/ath25/Kconfig +1 -0

index 7070b4bcd01d..2c1dfd06c366 100644
@@ -12,6 +12,7 @@ config SOC_AR2315
 config PCI_AR2315
 	bool "Atheros AR2315 PCI controller support"
 	depends on SOC_AR2315
+	select ARCH_HAS_PHYS_TO_DMA
 	select HW_HAS_PCI
 	select PCI
 	default y

arch/mips/include/asm/mach-ath25/dma-coherence.h deleted +0 ~~-71~~

71 lines not on this page · raw message

arch/mips/pci/pci-ar2315.c +24 -0

index b4fa6413c4e5..c539d0d2b0cf 100644
@@ -149,6 +149,13 @@
 #define AR2315_PCI_HOST_SLOT	3
 #define AR2315_PCI_HOST_DEVID	((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
 
+/*
+ * We need some arbitrary non-zero value to be programmed to the BAR1 register
+ * of PCI host controller to enable DMA. The same value should be used as the
+ * offset to calculate the physical address of DMA buffer for PCI devices.
+ */
+#define AR2315_PCI_HOST_SDRAM_BASEADDR	0x20000000
+
 /* ??? access BAR */
 #define AR2315_PCI_HOST_MBAR0		0x10000000
 /* RAM access BAR */

@@ -167,6 +174,23 @@ struct ar2315_pci_ctrl {
 	struct resource io_res;
 };
 
+static inline dma_addr_t ar2315_dev_offset(struct device *dev)
+{
+	if (dev && dev_is_pci(dev))
+		return AR2315_PCI_HOST_SDRAM_BASEADDR;
+	return 0;
+}
+
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+	return paddr + ar2315_dev_offset(dev);
+}
+
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
+	return dma_addr - ar2315_dev_offset(dev);
+}
+
 static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
 {
 	struct pci_controller *hose = bus->sysdata;

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #33 lore raw

PATCH 21/25 MIPS: jazz: split dma mapping operations from dma-default

In reply to a message not in the archive

Jazz actually has a very basic IOMMU, so split the ops into a separate implementation from the generic default support (which is about to go away anyway).

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/include/asm/dma-mapping.h           |   5 +-
 .../include/asm/mach-jazz/dma-coherence.h     |  60 --------
 arch/mips/jazz/Kconfig                        |   3 -
 arch/mips/jazz/jazzdma.c                      | 141 +++++++++++++++++-
 4 files changed, 144 insertions(+), 65 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-jazz/dma-coherence.h

arch/mips/include/asm/dma-mapping.h +4 -1

index e32a7b439816..caf97f739897 100644
@@ -10,12 +10,15 @@
 #include <dma-coherence.h>
 #endif
 
+extern const struct dma_map_ops jazz_dma_ops;
 extern const struct dma_map_ops mips_default_dma_map_ops;
 extern const struct dma_map_ops mips_swiotlb_ops;
 
 static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 {
-#ifdef CONFIG_SWIOTLB
+#if defined(CONFIG_MACH_JAZZ)
+	return &jazz_dma_ops;
+#elif defined(CONFIG_SWIOTLB)
 	return &mips_swiotlb_ops;
 #elif defined(CONFIG_MIPS_DMA_DEFAULT)
 	return &mips_default_dma_map_ops;

arch/mips/include/asm/mach-jazz/dma-coherence.h deleted +0 ~~-60~~

60 lines not on this page · raw message

arch/mips/jazz/Kconfig +0 -3

index d3ae3e0356f6..06838f80a5d7 100644
@@ -3,7 +3,6 @@ config ACER_PICA_61
 	bool "Support for Acer PICA 1 chipset"
 	depends on MACH_JAZZ
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	help
 	  This is a machine with a R4400 133/150 MHz CPU. To compile a Linux

@@ -15,7 +14,6 @@ config MIPS_MAGNUM_4000
 	bool "Support for MIPS Magnum 4000"
 	depends on MACH_JAZZ
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	help

@@ -28,7 +26,6 @@ config OLIVETTI_M700
 	bool "Support for Olivetti M700-10"
 	depends on MACH_JAZZ
 	select DMA_NONCOHERENT
-	select MIPS_DMA_DEFAULT
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	help
 	  This is a machine with a R4000 100 MHz CPU. To compile a Linux

arch/mips/jazz/jazzdma.c +140 -1

156 lines not on this page · raw message

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #34 lore raw

PATCH 22/25 dma-noncoherent: add a arch_sync_dma_for_cpu_all hook

In reply to a message not in the archive

The MIPS bmips platform needs a global flush when transferring ownership back to the CPU. Add a hook for that to the dma-noncoherent implementation.

Signed-off-by Christoph Hellwig <[email protected]>

---
 include/linux/dma-noncoherent.h | 8 ++++++++
 lib/dma-noncoherent.c           | 8 ++++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

include/linux/dma-noncoherent.h +8 -0

index 10b2654d549b..a0aa00cc909d 100644
@@ -44,4 +44,12 @@ static inline void arch_sync_dma_for_cpu(struct device *dev,
 }
 #endif /* ARCH_HAS_SYNC_DMA_FOR_CPU */
 
+#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
+void arch_sync_dma_for_cpu_all(struct device *dev);
+#else
+static inline void arch_sync_dma_for_cpu_all(struct device *dev)
+{
+}
+#endif /* CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL */
+
 #endif /* _LINUX_DMA_NONCOHERENT_H */

lib/dma-noncoherent.c +6 -2

index 79e9a757387f..031fe235d958 100644
@@ -49,11 +49,13 @@ static int dma_noncoherent_map_sg(struct device *dev, struct scatterlist *sgl,
 	return nents;
 }
 
-#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
+    defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
 static void dma_noncoherent_sync_single_for_cpu(struct device *dev,
 		dma_addr_t addr, size_t size, enum dma_data_direction dir)
 {
 	arch_sync_dma_for_cpu(dev, dma_to_phys(dev, addr), size, dir);
+	arch_sync_dma_for_cpu_all(dev);
 }
 
 static void dma_noncoherent_sync_sg_for_cpu(struct device *dev,

@@ -64,6 +66,7 @@ static void dma_noncoherent_sync_sg_for_cpu(struct device *dev,
 
 	for_each_sg(sgl, sg, nents, i)
 		arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir);
+	arch_sync_dma_for_cpu_all(dev);
 }
 
 static void dma_noncoherent_unmap_page(struct device *dev, dma_addr_t addr,

@@ -89,7 +92,8 @@ const struct dma_map_ops dma_noncoherent_ops = {
 	.sync_sg_for_device	= dma_noncoherent_sync_sg_for_device,
 	.map_page		= dma_noncoherent_map_page,
 	.map_sg			= dma_noncoherent_map_sg,
-#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
+    defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
 	.sync_single_for_cpu	= dma_noncoherent_sync_single_for_cpu,
 	.sync_sg_for_cpu	= dma_noncoherent_sync_sg_for_cpu,
 	.unmap_page		= dma_noncoherent_unmap_page,

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #35 lore raw

PATCH 23/25 MIPS: bmips: use generic dma noncoherent ops

In reply to a message not in the archive

Provide phys_to_dma/dma_to_phys helpers, and the special arch_sync_dma_for_cpu_all hook, everything else is generic

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                             |  3 +-
 arch/mips/bmips/dma.c                         | 32 ++++++-----
 arch/mips/include/asm/bmips.h                 | 16 ------
 .../include/asm/mach-bmips/dma-coherence.h    | 54 -------------------
 4 files changed, 21 insertions(+), 84 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-bmips/dma-coherence.h

arch/mips/Kconfig +2 -1

index 25a3c3262554..9ac3c6260b68 100644
@@ -209,6 +209,8 @@ config ATH79
 
 config BMIPS_GENERIC
 	bool "Broadcom Generic BMIPS kernel"
+	select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
+	select ARCH_HAS_PHYS_TO_DMA
 	select BOOT_RAW
 	select NO_EXCEPT_FILL
 	select USE_OF

@@ -221,7 +223,6 @@ config BMIPS_GENERIC
 	select BCM7120_L2_IRQ
 	select BRCMSTB_L2_IRQ
 	select IRQ_MIPS_CPU
-	select MIPS_DMA_DEFAULT
 	select DMA_NONCOHERENT
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_LITTLE_ENDIAN

arch/mips/bmips/dma.c +19 ~~-13~~

index 04790f4e1805..02ba0e38748d 100644
@@ -17,7 +17,7 @@
 #include <linux/printk.h>
 #include <linux/slab.h>
 #include <linux/types.h>
-#include <dma-coherence.h>
+#include <asm/bmips.h>
 
 /*
  * BCM338x has configurable address translation windows which allow the

@@ -40,7 +40,7 @@ static struct bmips_dma_range *bmips_dma_ranges;
 
 #define FLUSH_RAC		0x100
 
-static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa)
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t pa)
 {
 	struct bmips_dma_range *r;

@@ -52,17 +52,7 @@ static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa)
 	return pa;
 }
 
-dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
-{
-	return bmips_phys_to_dma(dev, virt_to_phys(addr));
-}
-
-dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
-{
-	return bmips_phys_to_dma(dev, page_to_phys(page));
-}
-
-unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
 {
 	struct bmips_dma_range *r;

@@ -74,6 +64,22 @@ unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
 	return dma_addr;
 }
 
+void arch_sync_dma_for_cpu_all(struct device *dev)
+{
+	void __iomem *cbr = BMIPS_GET_CBR();
+	u32 cfg;
+
+	if (boot_cpu_type() != CPU_BMIPS3300 &&
+	    boot_cpu_type() != CPU_BMIPS4350 &&
+	    boot_cpu_type() != CPU_BMIPS4380)
+		return;
+
+	/* Flush stale data out of the readahead cache */
+	cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+	__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
+	__raw_readl(cbr + BMIPS_RAC_CONFIG);
+}
+
 static int __init bmips_init_dma_ranges(void)
 {
 	struct device_node *np =

arch/mips/include/asm/bmips.h +0 ~~-16~~

index b3e2975f83d3..bf6a8afd7ad2 100644
@@ -123,22 +123,6 @@ static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
 	barrier();
 }
 
-static inline void bmips_post_dma_flush(struct device *dev)
-{
-	void __iomem *cbr = BMIPS_GET_CBR();
-	u32 cfg;
-
-	if (boot_cpu_type() != CPU_BMIPS3300 &&
-	    boot_cpu_type() != CPU_BMIPS4350 &&
-	    boot_cpu_type() != CPU_BMIPS4380)
-		return;
-
-	/* Flush stale data out of the readahead cache */
-	cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
-	__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
-	__raw_readl(cbr + BMIPS_RAC_CONFIG);
-}
-
 #endif /* !defined(__ASSEMBLY__) */
 
 #endif /* _ASM_BMIPS_H */

arch/mips/include/asm/mach-bmips/dma-coherence.h deleted +0 ~~-54~~

54 lines not on this page · raw message

Signature · 1 line

2.17.0

Christoph Hellwig

author

2018-05-25 09:21 UTC #36 lore raw

PATCH 24/25 MIPS: remove the old dma-default implementation

In reply to a message not in the archive

Now unused.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/Kconfig                             |   5 +-
 arch/mips/include/asm/dma-mapping.h           |   3 -
 .../include/asm/mach-generic/dma-coherence.h  |  73 ----
 arch/mips/mm/Makefile                         |   1 -
 arch/mips/mm/dma-default.c                    | 379 ------------------
 5 files changed, 1 insertion(+), 460 deletions(-)
 delete mode 100644 arch/mips/include/asm/mach-generic/dma-coherence.h
 delete mode 100644 arch/mips/mm/dma-default.c

arch/mips/Kconfig +1 -4

index 9ac3c6260b68..ad5a542bf094 100644
@@ -72,9 +72,6 @@ config MIPS
 	select SYSCTL_EXCEPTION_TRACE
 	select VIRT_TO_BUS
 
-config MIPS_DMA_DEFAULT
-	bool
-
 menu "Machine selection"
 
 choice

@@ -1113,7 +1110,7 @@ config DMA_NONCOHERENT
 	select NEED_DMA_MAP_STATE
 	select DMA_NONCOHERENT_MMAP
 	select DMA_NONCOHERENT_CACHE_SYNC
-	select DMA_NONCOHERENT_OPS if !MIPS_DMA_DEFAULT
+	select DMA_NONCOHERENT_OPS
 
 config SYS_HAS_EARLY_PRINTK
 	bool

arch/mips/include/asm/dma-mapping.h +0 -3

index caf97f739897..143250986e17 100644
@@ -11,7 +11,6 @@
 #endif
 
 extern const struct dma_map_ops jazz_dma_ops;
-extern const struct dma_map_ops mips_default_dma_map_ops;
 extern const struct dma_map_ops mips_swiotlb_ops;
 
 static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)

@@ -20,8 +19,6 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
 	return &jazz_dma_ops;
 #elif defined(CONFIG_SWIOTLB)
 	return &mips_swiotlb_ops;
-#elif defined(CONFIG_MIPS_DMA_DEFAULT)
-	return &mips_default_dma_map_ops;
 #elif defined(CONFIG_DMA_NONCOHERENT_OPS)
 	return &dma_noncoherent_ops;
 #else

arch/mips/include/asm/mach-generic/dma-coherence.h deleted +0 ~~-73~~

73 lines not on this page · raw message

arch/mips/mm/Makefile +0 -1

index c6146c3805dc..6922f393af19 100644
@@ -17,7 +17,6 @@ obj-$(CONFIG_32BIT)		+= ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)		+= pgtable-64.o
 obj-$(CONFIG_HIGHMEM)		+= highmem.o
 obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
-obj-$(CONFIG_MIPS_DMA_DEFAULT)	+= dma-default.o
 obj-$(CONFIG_DMA_NONCOHERENT)	+= dma-noncoherent.o
 obj-$(CONFIG_SWIOTLB)		+= dma-swiotlb.o

arch/mips/mm/dma-default.c deleted +0 ~~-379~~

379 lines not on this page · raw message

Signature · 6 lines

2.17.0

_______________________________________________
iommu mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/iommu

Christoph Hellwig

author

2018-05-25 09:21 UTC #37 lore raw

PATCH 25/25 MIPS: remove unneeded includes from dma-mapping.h

In reply to a message not in the archive

Keep this file as light as possible as it gets pulled into every driver using dma mapping APIs.

Signed-off-by Christoph Hellwig <[email protected]>

---
 arch/mips/include/asm/dma-mapping.h | 8 --------
 arch/mips/mti-malta/malta-setup.c   | 1 +
 2 files changed, 1 insertion(+), 8 deletions(-)

arch/mips/include/asm/dma-mapping.h +0 -8

index 143250986e17..1c6e0c8ef483 100644
@@ -2,14 +2,6 @@
 #ifndef _ASM_DMA_MAPPING_H
 #define _ASM_DMA_MAPPING_H
 
-#include <linux/scatterlist.h>
-#include <asm/dma-coherence.h>
-#include <asm/cache.h>
-
-#ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */
-#include <dma-coherence.h>
-#endif
-
 extern const struct dma_map_ops jazz_dma_ops;
 extern const struct dma_map_ops mips_swiotlb_ops;

arch/mips/mti-malta/malta-setup.c +1 -0

index 4d5cdfeee3db..7cb7d5a42087 100644
@@ -26,6 +26,7 @@
 #include <linux/screen_info.h>
 #include <linux/time.h>
 
+#include <asm/dma-coherence.h>
 #include <asm/fw/fw.h>
 #include <asm/mach-malta/malta-dtshim.h>
 #include <asm/mips-cps.h>

Signature · 1 line

2.17.0