clean up DPU custom properties

Cleanup residual connector property enumerations.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/msm_drv.h | 27 ---------------------------
 1 file changed, 27 deletions(-)

drivers/gpu/drm/msm/msm_drv.h +0 -27

index 90a2521..954ac12 100644
@@ -140,32 +140,6 @@ enum msm_mdp_crtc_property {
 	CRTC_PROP_COUNT
 };
 
-enum msm_mdp_conn_property {
-	/* blob properties, always put these first */
-	CONNECTOR_PROP_DPU_INFO,
-	CONNECTOR_PROP_HDR_INFO,
-	CONNECTOR_PROP_PP_DITHER,
-
-	/* # of blob properties */
-	CONNECTOR_PROP_BLOBCOUNT,
-
-	/* range properties */
-	CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
-	CONNECTOR_PROP_DST_X,
-	CONNECTOR_PROP_DST_Y,
-	CONNECTOR_PROP_DST_W,
-	CONNECTOR_PROP_DST_H,
-	CONNECTOR_PROP_BL_SCALE,
-	CONNECTOR_PROP_AD_BL_SCALE,
-
-	/* enum/bitmask properties */
-	CONNECTOR_PROP_AUTOREFRESH,
-	CONNECTOR_PROP_LP,
-
-	/* total # of properties */
-	CONNECTOR_PROP_COUNT
-};
-
 struct msm_vblank_ctrl {
 	struct kthread_work work;
 	struct list_head event_list;

@@ -434,7 +408,6 @@ struct msm_drm_private {
 	/* Properties */
 	struct drm_property *plane_property[PLANE_PROP_COUNT];
 	struct drm_property *crtc_property[CRTC_PROP_COUNT];
-	struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
 
 	/* Color processing properties for the crtc */
 	struct drm_property **cp_property;

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

This change removes all the dpu plane custom properties and its handlers.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 Makefile                                           |    2 +-
 drivers/gpu/drm/msm/Makefile                       |    8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h            |   99 --
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c   | 1521 --------------------
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.h   |  120 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           |  148 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           |    3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |    2 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c    |    1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c         | 1443 -------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   72 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   89 --
 .../msm/disp/dpu1/dpu_hw_color_proc_common_v4.h    |   69 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c   |  242 ----
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h   |   40 -
 .../drm/msm/disp/dpu1/dpu_hw_color_processing.h    |   20 -
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.c   |  565 --------
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.h   |   92 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         |   44 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h         |   15 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c        |  209 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h        |  220 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c          |    1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   44 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c    |   68 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h    |    6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c  |  757 ----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h  |   27 -
 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c   |  943 ------------
 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h   |   75 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c        |  219 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h        |   73 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c        |    1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h        |  156 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |    3 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c          | 1267 +---------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h          |   31 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c        |  139 --

 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h        |  310 ----
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             |  102 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             |    2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c             |    2 -
 drivers/gpu/drm/msm/msm_drv.h                      |   28 -
 include/uapi/drm/dpu_drm.h                         |  187 ---
 include/uapi/drm/msm_drm.h                         |    1 -
 45 files changed, 277 insertions(+), 9189 deletions(-)

 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h

Makefile +0 -0

index 3c00040..1f23c66 100644

index 48920b05..d439a9e 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +6 -3

@@ -20,7 +20,6 @@
 #include <linux/sort.h>
 #include <linux/debugfs.h>
 #include <linux/ktime.h>
-#include <uapi/drm/dpu_drm.h>
 #include <drm/drm_mode.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>

@@ -31,13 +30,18 @@
 #include "dpu_hw_ctl.h"
 #include "dpu_crtc.h"
 #include "dpu_plane.h"
-#include "dpu_color_processing.h"
 #include "dpu_encoder.h"
 #include "dpu_vbif.h"
 #include "dpu_power_handle.h"
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
+#define DPU_DRM_BLEND_OP_NOT_DEFINED    0
+#define DPU_DRM_BLEND_OP_OPAQUE         1
+#define DPU_DRM_BLEND_OP_PREMULTIPLIED  2
+#define DPU_DRM_BLEND_OP_COVERAGE       3
+#define DPU_DRM_BLEND_OP_MAX            4
+
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1

@@ -590,7 +594,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
 	if (dpu_crtc->blob_info)
 		drm_property_blob_put(dpu_crtc->blob_info);
 	msm_property_destroy(&dpu_crtc->property_info);
-	dpu_cp_crtc_destroy_properties(crtc);
 	_dpu_crtc_destroy_dest_scaler(dpu_crtc);
 
 	_dpu_crtc_deinit_events(dpu_crtc);

Quoted 9 lines · Jeykumar Sankaran

This change removes all the dpu plane custom properties and its handlers.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 Makefile                                           |    2 +-
 drivers/gpu/drm/msm/Makefile                       |    8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h            |   99 --
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c   | 1521

--------------------

Quoted 6 lines

 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.h   |  120 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           |  148 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           |    3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |    2 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c    |    1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c         | 1443

-------------------

Quoted 19 lines

 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   72 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   89 --
 .../msm/disp/dpu1/dpu_hw_color_proc_common_v4.h    |   69 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c   |  242 ----
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h   |   40 -
 .../drm/msm/disp/dpu1/dpu_hw_color_processing.h    |   20 -
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.c   |  565 --------
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.h   |   92 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         |   44 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h         |   15 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c        |  209 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h        |  220 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c          |    1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   44 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c    |   68 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h    |    6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c  |  757 ----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h  |   27 -
 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c   |  943 

Quoted 8 lines

------------

 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h   |   75 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c        |  219 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h        |   73 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c        |    1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h        |  156 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |    3 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c          | 1267

+---------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h          |   31 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c        |  139 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h        |  310 ----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             |  102 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             |    2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c             |    2 -
>  drivers/gpu/drm/msm/msm_drv.h                      |   28 -
>  include/uapi/drm/dpu_drm.h                         |  187 ---
>  include/uapi/drm/msm_drm.h                         |    1 -
>  45 files changed, 277 insertions(+), 9189 deletions(-)

Doing all of this at once is really hard to review. I would have preferred to
review each feature removal in a separate patch. However, since this is just
going to be squashed into the DPU megapatch anyways, I guess it's fine.

I only paid close attention to the additions, there are some unrelated whitespace changes, but also meh on account of the squash (and non seem objectionable).

Quoted 7 lines

 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
 delete mode 100644 
drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
 delete mode 100644 
drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h

Quoted 5 lines

 delete mode 100644 
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
 delete mode 100644 
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h

Quoted 1 line

 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c

Quoted 1 line

 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h

Quoted 5 lines

 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h
 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c

Quoted 1 line

 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h

Makefile HOST_LFS_LIBS := $(shell getconf LFS_LIBS) · line 367

Quoted 13 lines

 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h

Makefile +1 -1

index 3c00040..1f23c66 100644
@@ -364,7 +364,7 @@ HOST_LFS_LIBS := $(shell getconf LFS_LIBS)
 HOSTCC       = gcc
 HOSTCXX      = g++
 HOSTCFLAGS   := -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 \
-		-fomit-frame-pointer -std=gnu89 $(HOST_LFS_CFLAGS)
+		-fomit-frame-pointer -std=gnu89 -Wmaybe-uninitialized

$(HOST_LFS_CFLAGS)

What's up with the compiler flag warnings? Seems unrelated (and we should probably remove all of them in a separate patch anyways).

Makefile HOST_LFS_LIBS := $(shell getconf LFS_LIBS) · line 370

Quoted 3 lines

Makefile +0 -0

 HOSTCXXFLAGS := -O2 $(HOST_LFS_CFLAGS)
 HOSTLDFLAGS  := $(HOST_LFS_LDFLAGS)
 HOST_LOADLIBES := $(HOST_LFS_LIBS)

/snip

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c static void _dpu_crtc_setup_blend_cfg(struct

Quoted 41 lines

index 48920b05..d439a9e 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +6 -3

@@ -20,7 +20,6 @@
 #include <linux/sort.h>
 #include <linux/debugfs.h>
 #include <linux/ktime.h>
-#include <uapi/drm/dpu_drm.h>
 #include <drm/drm_mode.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>

@@ -31,13 +30,18 @@
 #include "dpu_hw_ctl.h"
 #include "dpu_crtc.h"
 #include "dpu_plane.h"
-#include "dpu_color_processing.h"
 #include "dpu_encoder.h"
 #include "dpu_vbif.h"
 #include "dpu_power_handle.h"
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
+#define DPU_DRM_BLEND_OP_NOT_DEFINED    0
+#define DPU_DRM_BLEND_OP_OPAQUE         1
+#define DPU_DRM_BLEND_OP_PREMULTIPLIED  2
+#define DPU_DRM_BLEND_OP_COVERAGE       3
+#define DPU_DRM_BLEND_OP_MAX            4
+
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1

@@ -590,7 +594,6 @@ static void dpu_crtc_destroy(struct drm_crtc 
 *crtc)
 	if (dpu_crtc->blob_info)
 		drm_property_blob_put(dpu_crtc->blob_info);
 	msm_property_destroy(&dpu_crtc->property_info);
-	dpu_cp_crtc_destroy_properties(crtc);
 	_dpu_crtc_destroy_dest_scaler(dpu_crtc);
 

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +0 -0

 	_dpu_crtc_deinit_events(dpu_crtc);

@@ -624,15 +627,11 @@ static void _dpu_crtc_setup_blend_cfg(struct

dpu_crtc_mixer *mixer,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, · line 631

Quoted 6 lines

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +1 -1

 	struct dpu_hw_mixer *lm = mixer->hw_lm;
 
 	/* default to opaque blending */
-	fg_alpha = dpu_plane_get_property(pstate, PLANE_PROP_ALPHA);
+	fg_alpha = 0XFF;
 	bg_alpha = 0xFF - fg_alpha;

This goes to 0 and the fg_alpha != 0xff checks are always false. So let's clean
the rest of the function to remove the dead code and variables.

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c static void _dpu_crtc_setup_blend_cfg(struct · line 629

Quoted 1 line

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +0 -1

-	blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |

DPU_BLEND_BG_ALPHA_BG_CONST;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,

Quoted 3 lines

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +0 -3

-	blend_type = dpu_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
-
-	DPU_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type,

fg_alpha);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, · line 637

Quoted 8 lines

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +1 -1

+	blend_type = DPU_DRM_BLEND_OP_OPAQUE;
 
 	switch (blend_type) {
-
 	case DPU_DRM_BLEND_OP_OPAQUE:
 		blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
 			DPU_BLEND_BG_ALPHA_BG_CONST;

/snip

Enable drm core zpos normalization for planes.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/msm_drv.c | 3 +++
 1 file changed, 3 insertions(+)

drivers/gpu/drm/msm/msm_drv.c +3 -0

index ebc40a9..549359e 100644
@@ -592,6 +592,9 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
 	ddev->mode_config.funcs = &mode_config_funcs;
 	ddev->mode_config.helper_private = &mode_config_helper_funcs;
 
+	/* Enable normalization of plane zpos */
+	ddev->mode_config.normalize_zpos = true;
+
 	if (kms) {
 		ret = kms->funcs->hw_init(kms);
 		if (ret) {

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Replace custom plane zpos property with drm core zpos property. CRTC relies on the normalized zpos values to configure blend stages of each plane.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 36 +------------------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++++++---
 2 files changed, 16 insertions(+), 38 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +1 -35

index d439a9e..a0b702f 100644
@@ -2631,24 +2631,6 @@ struct plane_state {
 	u32 pipe_id;
 };
 
-static int pstate_cmp(const void *a, const void *b)
-{
-	struct plane_state *pa = (struct plane_state *)a;
-	struct plane_state *pb = (struct plane_state *)b;
-	int rc = 0;
-	int pa_zpos, pb_zpos;
-
-	pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS);
-	pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS);
-
-	if (pa_zpos != pb_zpos)
-		rc = pa_zpos - pb_zpos;
-	else
-		rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
-
-	return rc;
-}
-
 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		struct drm_crtc_state *state)
 {

@@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 		pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
 		pstates[cnt].drm_pstate = pstate;
-		pstates[cnt].stage = dpu_plane_get_property(
-				pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS);
+		pstates[cnt].stage = pstate->normalized_zpos;
 		pstates[cnt].pipe_id = dpu_plane_pipe(plane);
 
 		/* check dim layer stage with every plane */

@@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		}
 	}
 
-	/* assign mixer stages based on sorted zpos property */
-	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
-
-	if (!dpu_is_custom_client()) {
-		int stage_old = pstates[0].stage;
-
-		z_pos = 0;
-		for (i = 0; i < cnt; i++) {
-			if (stage_old != pstates[i].stage)
-				++z_pos;
-			stage_old = pstates[i].stage;
-			pstates[i].stage = z_pos;
-		}
-	}
-
 	z_pos = -1;
 	for (i = 0; i < cnt; i++) {
 		/* reset counts at every new blend stage */

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +5 -3

index b033653..28735c8 100644
@@ -59,6 +59,7 @@
 #define DPU_NAME_SIZE  12
 
 #define DPU_PLANE_COLOR_FILL_FLAG	BIT(31)
+#define DPU_ZPOS_MAX 255
 
 /* multirect rect index */
 enum {

@@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane,
 		/* reserve zpos == 0 for primary planes */
 		zpos_def = drm_plane_index(plane) + 1;
 	}
-
-	msm_property_install_range(&pdpu->property_info, "zpos",
-		0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
 }
 
 static int dpu_plane_atomic_set_property(struct drm_plane *plane,

@@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	struct msm_drm_private *priv;
 	struct dpu_kms *kms;
 	enum drm_plane_type type;
+	int zpos_max = DPU_ZPOS_MAX;
 	int ret = -EINVAL;
 
 	if (!dev) {

@@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	if (ret)
 		goto clean_sspp;
 
+	pdpu->catalog = kms->catalog;
+
+	if (kms->catalog->mixer_count &&

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +0 -0

 	/* success! finalize initialization */
 	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
 

Signature · 7 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

Quoted 105 lines · Jeykumar Sankaran

Replace custom plane zpos property with drm core zpos property. CRTC relies on the normalized zpos values to configure blend stages of each plane.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 36 +------------------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++++++---
 2 files changed, 16 insertions(+), 38 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +1 -35

index d439a9e..a0b702f 100644
@@ -2631,24 +2631,6 @@ struct plane_state {
 	u32 pipe_id;
 };
 
-static int pstate_cmp(const void *a, const void *b)
-{
-	struct plane_state *pa = (struct plane_state *)a;
-	struct plane_state *pb = (struct plane_state *)b;
-	int rc = 0;
-	int pa_zpos, pb_zpos;
-
-	pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS);
-	pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS);
-
-	if (pa_zpos != pb_zpos)
-		rc = pa_zpos - pb_zpos;
-	else
-		rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
-
-	return rc;
-}
-
 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		struct drm_crtc_state *state)
 {

@@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 		pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
 		pstates[cnt].drm_pstate = pstate;
-		pstates[cnt].stage = dpu_plane_get_property(
-				pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS);
+		pstates[cnt].stage = pstate->normalized_zpos;
 		pstates[cnt].pipe_id = dpu_plane_pipe(plane);
 
 		/* check dim layer stage with every plane */

@@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		}
 	}
 
-	/* assign mixer stages based on sorted zpos property */
-	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
-
-	if (!dpu_is_custom_client()) {
-		int stage_old = pstates[0].stage;
-
-		z_pos = 0;
-		for (i = 0; i < cnt; i++) {
-			if (stage_old != pstates[i].stage)
-				++z_pos;
-			stage_old = pstates[i].stage;
-			pstates[i].stage = z_pos;
-		}
-	}
-
 	z_pos = -1;
 	for (i = 0; i < cnt; i++) {
 		/* reset counts at every new blend stage */

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +2 -3

index b033653..28735c8 100644
@@ -59,6 +59,7 @@
 #define DPU_NAME_SIZE  12
 
 #define DPU_PLANE_COLOR_FILL_FLAG	BIT(31)
+#define DPU_ZPOS_MAX 255
 
 /* multirect rect index */
 enum {

@@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane,
 		/* reserve zpos == 0 for primary planes */
 		zpos_def = drm_plane_index(plane) + 1;
 	}
-
-	msm_property_install_range(&pdpu->property_info, "zpos",
-		0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
 }
 
 static int dpu_plane_atomic_set_property(struct drm_plane *plane,

@@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	struct msm_drm_private *priv;
 	struct dpu_kms *kms;
 	enum drm_plane_type type;
+	int zpos_max = DPU_ZPOS_MAX;
 	int ret = -EINVAL;
 
 	if (!dev) {

@@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	if (ret)
 		goto clean_sspp;
 

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c struct drm_plane *dpu_plane_init(struct drm_device *dev, · line 2063

Quoted 13 lines

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +13 -0

+	pdpu->catalog = kms->catalog;
+
+	if (kms->catalog->mixer_count &&
+		kms->catalog->mixer[0].sblk->maxblendstages) {
+		zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
+		if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
+			zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
+	}
+
+	ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
+	if (ret)
+		DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
+

drm_plane_create_zpos_property() can either return 0 or -ENOMEM

so
printing the return value isn't interesting.

Quoted 12 lines

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +0 -0

 	/* success! finalize initialization */
 	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
 

Signature · 7 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Replace custom plane zpos property with drm core zpos property. CRTC relies on the normalized zpos values to configure blend stages of each plane.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 36 +------------------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++++++---
 2 files changed, 16 insertions(+), 38 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +1 -35

index d439a9e..a0b702f 100644
@@ -2631,24 +2631,6 @@ struct plane_state {
 	u32 pipe_id;
 };
 
-static int pstate_cmp(const void *a, const void *b)
-{
-	struct plane_state *pa = (struct plane_state *)a;
-	struct plane_state *pb = (struct plane_state *)b;
-	int rc = 0;
-	int pa_zpos, pb_zpos;
-
-	pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS);
-	pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS);
-
-	if (pa_zpos != pb_zpos)
-		rc = pa_zpos - pb_zpos;
-	else
-		rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
-
-	return rc;
-}
-
 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		struct drm_crtc_state *state)
 {

@@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 		pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
 		pstates[cnt].drm_pstate = pstate;
-		pstates[cnt].stage = dpu_plane_get_property(
-				pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS);
+		pstates[cnt].stage = pstate->normalized_zpos;
 		pstates[cnt].pipe_id = dpu_plane_pipe(plane);
 
 		/* check dim layer stage with every plane */

@@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		}
 	}
 
-	/* assign mixer stages based on sorted zpos property */
-	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
-
-	if (!dpu_is_custom_client()) {
-		int stage_old = pstates[0].stage;
-
-		z_pos = 0;
-		for (i = 0; i < cnt; i++) {
-			if (stage_old != pstates[i].stage)
-				++z_pos;
-			stage_old = pstates[i].stage;
-			pstates[i].stage = z_pos;
-		}
-	}
-
 	z_pos = -1;
 	for (i = 0; i < cnt; i++) {
 		/* reset counts at every new blend stage */

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +2 -3

index b033653..28735c8 100644
@@ -59,6 +59,7 @@
 #define DPU_NAME_SIZE  12
 
 #define DPU_PLANE_COLOR_FILL_FLAG	BIT(31)
+#define DPU_ZPOS_MAX 255
 
 /* multirect rect index */
 enum {

@@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane,
 		/* reserve zpos == 0 for primary planes */
 		zpos_def = drm_plane_index(plane) + 1;
 	}
-
-	msm_property_install_range(&pdpu->property_info, "zpos",
-		0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
 }
 
 static int dpu_plane_atomic_set_property(struct drm_plane *plane,

@@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	struct msm_drm_private *priv;
 	struct dpu_kms *kms;
 	enum drm_plane_type type;
+	int zpos_max = DPU_ZPOS_MAX;
 	int ret = -EINVAL;
 
 	if (!dev) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +11 -0

+	if (kms->catalog->mixer_count &&
+		kms->catalog->mixer[0].sblk->maxblendstages) {
+		zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
+		if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
+			zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
+	}
+
+	ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
+	if (ret)
+		DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
+
 	/* success! finalize initialization */
 	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
 

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Remove dpu crtc custom properties and its handlers.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/Makefile                  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  28 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c      | 856 +-------------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h      |  27 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  12 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c     | 149 -----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h     | 111 ----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c     |  67 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h     |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h   |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c        |  71 +--
 drivers/gpu/drm/msm/msm_drv.h                 |  15 -
 12 files changed, 11 insertions(+), 1356 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h

drivers/gpu/drm/msm/Makefile +0 -1

index 7bc3921..d289503 100644
@@ -57,7 +57,6 @@ msm-y := \
 	disp/dpu1/dpu_hw_catalog.o \
 	disp/dpu1/dpu_hw_cdm.o \
 	disp/dpu1/dpu_hw_ctl.o \
-	disp/dpu1/dpu_hw_ds.o \
 	disp/dpu1/dpu_hw_interrupts.o \
 	disp/dpu1/dpu_hw_intf.o \
 	disp/dpu1/dpu_hw_lm.o \

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +0 -28

index 981f77f..c4820de 100644
@@ -102,34 +102,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
 	dpu_cstate = to_dpu_crtc_state(state);
 	memset(perf, 0, sizeof(struct dpu_core_perf_params));
 
-	perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-		dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-	perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-		dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-
-	if (dpu_cstate->bw_split_vote) {
-		perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_AB);
-		perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_IB);
-		perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_AB);
-		perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_IB);
-	} else {
-		perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-		perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-		perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-		perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-	}
-
-	perf->core_clk_rate =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_CLK);
-
 	if (!dpu_cstate->bw_control) {
 		for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
 			perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +3 -853

index a0b702f..b0a3a30 100644
@@ -570,18 +570,6 @@ static void _dpu_crtc_deinit_events(struct dpu_crtc *dpu_crtc)
 		return;
 }
 
-/**
- * dpu_crtc_destroy_dest_scaler - free memory allocated for scaler lut
- * @dpu_crtc: Pointer to dpu crtc
- */
-static void _dpu_crtc_destroy_dest_scaler(struct dpu_crtc *dpu_crtc)
-{
-	if (!dpu_crtc)
-		return;
-
-	kfree(dpu_crtc->scl3_lut_cfg);
-}
-
 static void dpu_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);

@@ -594,7 +582,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
 	if (dpu_crtc->blob_info)
 		drm_property_blob_put(dpu_crtc->blob_info);
 	msm_property_destroy(&dpu_crtc->property_info);
-	_dpu_crtc_destroy_dest_scaler(dpu_crtc);
 
 	_dpu_crtc_deinit_events(dpu_crtc);
 

@@ -679,71 +666,6 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
 		format->alpha_enable, fg_alpha, bg_alpha, blend_op);
 }
 
-static void _dpu_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
-		struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
-		struct dpu_hw_dim_layer *dim_layer)
-{
-	struct dpu_crtc_state *cstate;
-	struct dpu_hw_mixer *lm;
-	struct dpu_hw_dim_layer split_dim_layer;
-	int i;
-
-	if (!dim_layer->rect.w || !dim_layer->rect.h) {
-		DPU_DEBUG("empty dim_layer\n");
-		return;
-	}
-
-	cstate = to_dpu_crtc_state(crtc->state);
-
-	DPU_DEBUG("dim_layer - flags:%d, stage:%d\n",
-			dim_layer->flags, dim_layer->stage);
-
-	split_dim_layer.stage = dim_layer->stage;
-	split_dim_layer.color_fill = dim_layer->color_fill;
-
-	/*
-	 * traverse through the layer mixers attached to crtc and find the
-	 * intersecting dim layer rect in each LM and program accordingly.
-	 */
-	for (i = 0; i < dpu_crtc->num_mixers; i++) {
-		split_dim_layer.flags = dim_layer->flags;
-
-		dpu_kms_rect_intersect(&cstate->lm_bounds[i], &dim_layer->rect,
-					&split_dim_layer.rect);
-		if (dpu_kms_rect_is_null(&split_dim_layer.rect)) {
-			/*
-			 * no extra programming required for non-intersecting
-			 * layer mixers with INCLUSIVE dim layer
-			 */
-			if (split_dim_layer.flags & DPU_DRM_DIM_LAYER_INCLUSIVE)
-				continue;
-
-			/*
-			 * program the other non-intersecting layer mixers with
-			 * INCLUSIVE dim layer of full size for uniformity
-			 * with EXCLUSIVE dim layer config.
-			 */
-			split_dim_layer.flags &= ~DPU_DRM_DIM_LAYER_EXCLUSIVE;
-			split_dim_layer.flags |= DPU_DRM_DIM_LAYER_INCLUSIVE;
-			memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
-					sizeof(split_dim_layer.rect));
-
-		} else {
-			split_dim_layer.rect.x =
-					split_dim_layer.rect.x -
-						cstate->lm_bounds[i].x;
-		}
-
-		DPU_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
-			i, split_dim_layer.rect.x, split_dim_layer.rect.y,
-			split_dim_layer.rect.w, split_dim_layer.rect.h);
-
-		lm = mixer[i].hw_lm;
-		mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
-		lm->ops.setup_dim_layer(lm, &split_dim_layer);
-	}
-}
-
 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
 {
 	struct dpu_crtc *dpu_crtc;

@@ -787,7 +709,6 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
 	u32 flush_mask;
 	uint32_t stage_idx, lm_idx;
 	int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
-	int i;
 	bool bg_alpha_enable = false;
 
 	if (!dpu_crtc || !mixer) {

@@ -863,13 +784,6 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
 		}
 	}
 
-	if (lm && lm->ops.setup_dim_layer) {
-		cstate = to_dpu_crtc_state(crtc->state);
-		for (i = 0; i < cstate->num_dim_layers; i++)
-			_dpu_crtc_setup_dim_layer_cfg(crtc, dpu_crtc,
-					mixer, &cstate->dim_layer[i]);
-	}
-
 	 _dpu_crtc_program_lm_output_roi(crtc);
 }
 

@@ -911,11 +825,6 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 		if (mixer[i].hw_ctl->ops.clear_all_blendstages)
 			mixer[i].hw_ctl->ops.clear_all_blendstages(
 					mixer[i].hw_ctl);
-
-		/* clear dim_layer settings */
-		lm = mixer[i].hw_lm;
-		if (lm->ops.clear_dim_layer)
-			lm->ops.clear_dim_layer(lm);
 	}
 
 	/* initialize stage cfg */

@@ -947,163 +856,6 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 }
 
 /**
- * _dpu_crtc_setup_scaler3_lut - Set up scaler lut
- * LUTs are configured only once during boot
- * @dpu_crtc: Pointer to dpu crtc
- * @cstate: Pointer to dpu crtc state
- */
-static int _dpu_crtc_set_dest_scaler_lut(struct dpu_crtc *dpu_crtc,
-		struct dpu_crtc_state *cstate, uint32_t lut_idx)
-{
-	struct dpu_hw_scaler3_lut_cfg *cfg;
-	u32 *lut_data = NULL;
-	size_t len = 0;
-	int ret = 0;
-
-	if (!dpu_crtc || !cstate || !dpu_crtc->scl3_lut_cfg) {
-		DPU_ERROR("invalid args\n");
-		return -EINVAL;
-	}
-
-	if (dpu_crtc->scl3_lut_cfg->is_configured) {
-		DPU_DEBUG("lut already configured\n");
-		return 0;
-	}
-
-	lut_data = msm_property_get_blob(&dpu_crtc->property_info,
-			&cstate->property_state, &len, lut_idx);
-	if (!lut_data || !len) {
-		DPU_ERROR("lut(%d): no data, len(%zu)\n", lut_idx, len);
-		return -ENODATA;
-	}
-
-	cfg = dpu_crtc->scl3_lut_cfg;
-
-	switch (lut_idx) {
-	case CRTC_PROP_DEST_SCALER_LUT_ED:
-		cfg->dir_lut = lut_data;
-		cfg->dir_len = len;
-		break;
-	case CRTC_PROP_DEST_SCALER_LUT_CIR:
-		cfg->cir_lut = lut_data;
-		cfg->cir_len = len;
-		break;
-	case CRTC_PROP_DEST_SCALER_LUT_SEP:
-		cfg->sep_lut = lut_data;
-		cfg->sep_len = len;
-		break;
-	default:
-		ret = -EINVAL;
-		DPU_ERROR("invalid LUT index = %d", lut_idx);
-		break;
-	}
-
-	if (cfg->dir_lut && cfg->cir_lut && cfg->sep_lut)
-		cfg->is_configured = true;
-
-	return ret;
-}
-
-/**
- * _dpu_crtc_dest_scaler_setup - Set up dest scaler block
- * @crtc: Pointer to drm crtc
- */
-static void _dpu_crtc_dest_scaler_setup(struct drm_crtc *crtc)
-{
-	struct dpu_crtc *dpu_crtc;
-	struct dpu_crtc_state *cstate;
-	struct dpu_hw_mixer *hw_lm;
-	struct dpu_hw_ctl *hw_ctl;
-	struct dpu_hw_ds *hw_ds;
-	struct dpu_hw_ds_cfg *cfg;
-	struct dpu_kms *kms;
-	u32 flush_mask = 0, op_mode = 0;
-	u32 lm_idx = 0, num_mixers = 0;
-	int i, count = 0;
-
-	if (!crtc)
-		return;
-
-	dpu_crtc   = to_dpu_crtc(crtc);
-	cstate = to_dpu_crtc_state(crtc->state);
-	kms    = _dpu_crtc_get_kms(crtc);
-	num_mixers = dpu_crtc->num_mixers;
-
-	DPU_DEBUG("crtc%d\n", crtc->base.id);
-
-	if (!cstate->ds_dirty) {
-		DPU_DEBUG("no change in settings, skip commit\n");
-	} else if (!kms || !kms->catalog) {
-		DPU_ERROR("invalid parameters\n");
-	} else if (!kms->catalog->mdp[0].has_dest_scaler) {
-		DPU_DEBUG("dest scaler feature not supported\n");
-	} else if (num_mixers > CRTC_DUAL_MIXERS) {
-		DPU_ERROR("invalid number mixers: %d\n", num_mixers);
-	} else if (!dpu_crtc->scl3_lut_cfg->is_configured) {
-		DPU_DEBUG("no LUT data available\n");
-	} else {
-		count = cstate->num_ds_enabled ? cstate->num_ds : num_mixers;
-
-		for (i = 0; i < count; i++) {
-			cfg = &cstate->ds_cfg[i];
-
-			if (!cfg->flags)
-				continue;
-
-			lm_idx = cfg->ndx;
-			hw_lm  = dpu_crtc->mixers[lm_idx].hw_lm;
-			hw_ctl = dpu_crtc->mixers[lm_idx].hw_ctl;
-			hw_ds  = dpu_crtc->mixers[lm_idx].hw_ds;
-
-			/* Setup op mode - Dual/single */
-			if (cfg->flags & DPU_DRM_DESTSCALER_ENABLE)
-				op_mode |= BIT(hw_ds->idx - DS_0);
-
-			if ((i == count-1) && hw_ds->ops.setup_opmode) {
-				op_mode |= (cstate->num_ds_enabled ==
-					CRTC_DUAL_MIXERS) ?
-					DPU_DS_OP_MODE_DUAL : 0;
-				hw_ds->ops.setup_opmode(hw_ds, op_mode);
-				DPU_EVT32(DRMID(crtc), op_mode);
-			}
-
-			/* Setup scaler */
-			if ((cfg->flags & DPU_DRM_DESTSCALER_SCALE_UPDATE) ||
-				(cfg->flags &
-					DPU_DRM_DESTSCALER_ENHANCER_UPDATE)) {
-				if (hw_ds->ops.setup_scaler)
-					hw_ds->ops.setup_scaler(hw_ds,
-							cfg->scl3_cfg,
-							dpu_crtc->scl3_lut_cfg);
-
-				/**
-				 * Clear the flags as the block doesn't have to
-				 * be programmed in each commit if no updates
-				 */
-				cfg->flags &= ~DPU_DRM_DESTSCALER_SCALE_UPDATE;
-				cfg->flags &=
-					~DPU_DRM_DESTSCALER_ENHANCER_UPDATE;
-			}
-
-			/*
-			 * Dest scaler shares the flush bit of the LM in control
-			 */
-			if (cfg->set_lm_flush && hw_lm && hw_ctl &&
-				hw_ctl->ops.get_bitmask_mixer) {
-				flush_mask = hw_ctl->ops.get_bitmask_mixer(
-						hw_ctl, hw_lm->idx);
-				DPU_DEBUG("Set lm[%d] flush = %d",
-					hw_lm->idx, flush_mask);
-				hw_ctl->ops.update_pending_flush(hw_ctl,
-								flush_mask);
-			}
-			cfg->set_lm_flush = false;
-		}
-		cstate->ds_dirty = false;
-	}
-}
-
-/**
  *  _dpu_crtc_complete_flip - signal pending page_flip events
  * Any pending vblank events are added to the vblank_event_list
  * so that the next vblank interrupt shall signal them.

@@ -1361,448 +1113,6 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
 	DPU_EVT32_VERBOSE(DRMID(crtc));
 }
 
-/* _dpu_crtc_set_idle_timeout - update idle timeout wait duration */
-static void _dpu_crtc_set_idle_timeout(struct drm_crtc *crtc, u64 val)
-{
-	struct drm_encoder *encoder;
-
-	if (!crtc) {
-		DPU_ERROR("invalid crtc\n");
-		return;
-	}
-
-	drm_for_each_encoder(encoder, crtc->dev) {
-		if (encoder->crtc != crtc)
-			continue;
-
-		dpu_encoder_set_idle_timeout(encoder, (u32) val);
-	}
-}
-
-/**
- * _dpu_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
- * @cstate:      Pointer to dpu crtc state
- * @user_ptr:    User ptr for dpu_drm_dim_layer_v1 struct
- */
-static void _dpu_crtc_set_dim_layer_v1(struct dpu_crtc_state *cstate,
-		void __user *usr_ptr)
-{
-	struct dpu_drm_dim_layer_v1 dim_layer_v1;
-	struct dpu_drm_dim_layer_cfg *user_cfg;
-	struct dpu_hw_dim_layer *dim_layer;
-	u32 count, i;
-
-	if (!cstate) {
-		DPU_ERROR("invalid cstate\n");
-		return;
-	}
-	dim_layer = cstate->dim_layer;
-
-	if (!usr_ptr) {
-		DPU_DEBUG("dim_layer data removed\n");
-		return;
-	}
-
-	if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
-		DPU_ERROR("failed to copy dim_layer data\n");
-		return;
-	}
-
-	count = dim_layer_v1.num_layers;
-	if (count > DPU_MAX_DIM_LAYERS) {
-		DPU_ERROR("invalid number of dim_layers:%d", count);
-		return;
-	}
-
-	/* populate from user space */
-	cstate->num_dim_layers = count;
-	for (i = 0; i < count; i++) {
-		user_cfg = &dim_layer_v1.layer_cfg[i];
-
-		dim_layer[i].flags = user_cfg->flags;
-		dim_layer[i].stage = user_cfg->stage + DPU_STAGE_0;
-
-		dim_layer[i].rect.x = user_cfg->rect.x1;
-		dim_layer[i].rect.y = user_cfg->rect.y1;
-		dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
-		dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
-
-		dim_layer[i].color_fill = (struct dpu_mdss_color) {
-				user_cfg->color_fill.color_0,
-				user_cfg->color_fill.color_1,
-				user_cfg->color_fill.color_2,
-				user_cfg->color_fill.color_3,
-		};
-
-		DPU_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
-				i, dim_layer[i].flags, dim_layer[i].stage);
-		DPU_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
-				dim_layer[i].rect.x, dim_layer[i].rect.y,
-				dim_layer[i].rect.w, dim_layer[i].rect.h,
-				dim_layer[i].color_fill.color_0,
-				dim_layer[i].color_fill.color_1,
-				dim_layer[i].color_fill.color_2,
-				dim_layer[i].color_fill.color_3);
-	}
-}
-
-/**
- * _dpu_crtc_dest_scaler_init - allocate memory for scaler lut
- * @dpu_crtc    :  Pointer to dpu crtc
- * @catalog :  Pointer to mdss catalog info
- */
-static void _dpu_crtc_dest_scaler_init(struct dpu_crtc *dpu_crtc,
-				struct dpu_mdss_cfg *catalog)
-{
-	if (!dpu_crtc || !catalog)
-		return;
-
-	if (!catalog->mdp[0].has_dest_scaler) {
-		DPU_DEBUG("dest scaler feature not supported\n");
-		return;
-	}
-
-	dpu_crtc->scl3_lut_cfg = kzalloc(sizeof(struct dpu_hw_scaler3_lut_cfg),
-				GFP_KERNEL);
-	if (!dpu_crtc->scl3_lut_cfg)
-		DPU_ERROR("failed to create scale LUT for dest scaler");
-}
-
-/**
- * _dpu_crtc_set_dest_scaler - copy dest scaler settings from userspace
- * @dpu_crtc   :  Pointer to dpu crtc
- * @cstate :  Pointer to dpu crtc state
- * @usr_ptr:  User ptr for dpu_drm_dest_scaler_data struct
- */
-static int _dpu_crtc_set_dest_scaler(struct dpu_crtc *dpu_crtc,
-				struct dpu_crtc_state *cstate,
-				void __user *usr_ptr)
-{
-	struct dpu_drm_dest_scaler_data ds_data;
-	struct dpu_drm_dest_scaler_cfg *ds_cfg_usr;
-	struct dpu_drm_scaler_v2 scaler_v2;
-	void __user *scaler_v2_usr;
-	int i, count, ret = 0;
-
-	if (!dpu_crtc || !cstate) {
-		DPU_ERROR("invalid dpu_crtc/state\n");
-		return -EINVAL;
-	}
-
-	DPU_DEBUG("crtc %s\n", dpu_crtc->name);
-
-	cstate->num_ds = 0;
-	cstate->ds_dirty = false;
-	if (!usr_ptr) {
-		DPU_DEBUG("ds data removed\n");
-		return 0;
-	}
-
-	if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
-		DPU_ERROR("failed to copy dest scaler data from user\n");
-		return -EINVAL;
-	}
-
-	count = ds_data.num_dest_scaler;
-	if (!dpu_crtc->num_mixers || count > dpu_crtc->num_mixers ||
-		(count && (count != dpu_crtc->num_mixers) &&
-		!(ds_data.ds_cfg[0].flags & DPU_DRM_DESTSCALER_PU_ENABLE))) {
-		DPU_ERROR("invalid config:num ds(%d), mixers(%d),flags(%d)\n",
-			count, dpu_crtc->num_mixers, ds_data.ds_cfg[0].flags);
-		return -EINVAL;
-	}
-
-	/* Populate from user space */
-	for (i = 0; i < count; i++) {
-		ds_cfg_usr = &ds_data.ds_cfg[i];
-
-		cstate->ds_cfg[i].ndx = ds_cfg_usr->index;
-		cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
-		cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
-		cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
-		cstate->ds_cfg[i].scl3_cfg = NULL;
-
-		if (ds_cfg_usr->scaler_cfg) {
-			scaler_v2_usr =
-			(void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
-
-			memset(&scaler_v2, 0, sizeof(scaler_v2));
-
-			cstate->ds_cfg[i].scl3_cfg =
-				kzalloc(sizeof(struct dpu_hw_scaler3_cfg),
-					GFP_KERNEL);
-
-			if (!cstate->ds_cfg[i].scl3_cfg) {
-				ret = -ENOMEM;
-				goto err;
-			}
-
-			if (copy_from_user(&scaler_v2, scaler_v2_usr,
-					sizeof(scaler_v2))) {
-				DPU_ERROR("scale data:copy from user failed\n");
-				ret = -EINVAL;
-				goto err;
-			}
-
-			dpu_set_scaler_v2(cstate->ds_cfg[i].scl3_cfg,
-					&scaler_v2);
-
-			DPU_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
-				scaler_v2.enable, scaler_v2.dir_en,
-				scaler_v2.de.enable, scaler_v2.src_width[0],
-				scaler_v2.src_height[0], scaler_v2.dst_width,
-				scaler_v2.dst_height);
-			DPU_EVT32_VERBOSE(DRMID(&dpu_crtc->base),
-				scaler_v2.enable, scaler_v2.dir_en,
-				scaler_v2.de.enable, scaler_v2.src_width[0],
-				scaler_v2.src_height[0], scaler_v2.dst_width,
-				scaler_v2.dst_height);
-		}
-
-		DPU_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
-			i, ds_cfg_usr->index, ds_cfg_usr->flags,
-			ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
-		DPU_EVT32_VERBOSE(DRMID(&dpu_crtc->base), i, ds_cfg_usr->index,
-			ds_cfg_usr->flags, ds_cfg_usr->lm_width,
-			ds_cfg_usr->lm_height);
-	}
-
-	cstate->num_ds = count;
-	cstate->ds_dirty = true;
-	return 0;
-
-err:
-	for (; i >= 0; i--)
-		kfree(cstate->ds_cfg[i].scl3_cfg);
-
-	return ret;
-}
-
-/**
- * _dpu_crtc_check_dest_scaler_data - validate the dest scaler data
- * @crtc  :  Pointer to drm crtc
- * @state :  Pointer to drm crtc state
- */
-static int _dpu_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
-				struct drm_crtc_state *state)
-{
-	struct dpu_crtc *dpu_crtc;
-	struct dpu_crtc_state *cstate;
-	struct drm_display_mode *mode;
-	struct dpu_kms *kms;
-	struct dpu_hw_ds *hw_ds;
-	struct dpu_hw_ds_cfg *cfg;
-	u32 i, ret = 0, lm_idx;
-	u32 num_ds_enable = 0;
-	u32 max_in_width = 0, max_out_width = 0;
-	u32 prev_lm_width = 0, prev_lm_height = 0;
-
-	if (!crtc || !state)
-		return -EINVAL;
-
-	dpu_crtc = to_dpu_crtc(crtc);
-	cstate = to_dpu_crtc_state(state);
-	kms = _dpu_crtc_get_kms(crtc);
-	mode = &state->adjusted_mode;
-
-	DPU_DEBUG("crtc%d\n", crtc->base.id);
-
-	if (!cstate->ds_dirty && !cstate->num_ds_enabled) {
-		DPU_DEBUG("dest scaler property not set, skip validation\n");
-		return 0;
-	}
-
-	if (!kms || !kms->catalog) {
-		DPU_ERROR("invalid parameters\n");
-		return -EINVAL;
-	}
-
-	if (!kms->catalog->mdp[0].has_dest_scaler) {
-		DPU_DEBUG("dest scaler feature not supported\n");
-		return 0;
-	}
-
-	if (!dpu_crtc->num_mixers) {
-		DPU_ERROR("mixers not allocated\n");
-		return -EINVAL;
-	}
-
-	/**
-	 * Check if sufficient hw resources are
-	 * available as per target caps & topology
-	 */
-	if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
-		DPU_ERROR("invalid config: mixers(%d) max(%d)\n",
-			dpu_crtc->num_mixers, CRTC_DUAL_MIXERS);
-		ret = -EINVAL;
-		goto err;
-	}
-
-	for (i = 0; i < dpu_crtc->num_mixers; i++) {
-		if (!dpu_crtc->mixers[i].hw_lm || !dpu_crtc->mixers[i].hw_ds) {
-			DPU_ERROR("insufficient HW resources allocated\n");
-			ret = -EINVAL;
-			goto err;
-		}
-	}
-
-	/**
-	 * Check if DS needs to be enabled or disabled
-	 * In case of enable, validate the data
-	 */
-	if (!cstate->ds_dirty || !cstate->num_ds ||
-		!(cstate->ds_cfg[0].flags & DPU_DRM_DESTSCALER_ENABLE)) {
-		DPU_DEBUG("disable dest scaler,dirty(%d)num(%d)flags(%d)\n",
-			cstate->ds_dirty, cstate->num_ds,
-			cstate->ds_cfg[0].flags);
-		goto disable;
-	}
-
-	/**
-	 * No of dest scalers shouldn't exceed hw ds block count and
-	 * also, match the num of mixers unless it is partial update
-	 * left only/right only use case - currently PU + DS is not supported
-	 */
-	if (cstate->num_ds > kms->catalog->ds_count ||
-		((cstate->num_ds != dpu_crtc->num_mixers) &&
-		!(cstate->ds_cfg[0].flags & DPU_DRM_DESTSCALER_PU_ENABLE))) {
-		DPU_ERROR("invalid cfg: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
-			cstate->num_ds, kms->catalog->ds_count,
-			cstate->ds_cfg[0].flags);
-		ret = -EINVAL;
-		goto err;
-	}
-
-	/* Validate the DS data */
-	for (i = 0; i < cstate->num_ds; i++) {
-		cfg = &cstate->ds_cfg[i];
-		lm_idx = cfg->ndx;
-
-		/**
-		 * Validate against topology
-		 * No of dest scalers should match the num of mixers
-		 * unless it is partial update left only/right only use case
-		 */
-		if (lm_idx >= dpu_crtc->num_mixers || (i != lm_idx &&
-			!(cfg->flags & DPU_DRM_DESTSCALER_PU_ENABLE))) {
-			DPU_ERROR("invalid user data(%d):idx(%d), flags(%d)\n",
-				i, lm_idx, cfg->flags);
-			ret = -EINVAL;
-			goto err;
-		}
-
-		hw_ds = dpu_crtc->mixers[lm_idx].hw_ds;
-
-		if (!max_in_width && !max_out_width) {
-			max_in_width = hw_ds->scl->top->maxinputwidth;
-			max_out_width = hw_ds->scl->top->maxoutputwidth;
-
-			if (cstate->num_ds == CRTC_DUAL_MIXERS)
-				max_in_width -= DPU_DS_OVERFETCH_SIZE;
-
-			DPU_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
-				max_in_width, max_out_width, cstate->num_ds);
-		}
-
-		/* Check LM width and height */
-		if (cfg->lm_width > (mode->hdisplay/dpu_crtc->num_mixers) ||
-			cfg->lm_height > mode->vdisplay ||
-			!cfg->lm_width || !cfg->lm_height) {
-			DPU_ERROR("invalid lm size[%d,%d] display [%d,%d]\n",
-				cfg->lm_width,
-				cfg->lm_height,
-				mode->hdisplay/dpu_crtc->num_mixers,
-				mode->vdisplay);
-			ret = -E2BIG;
-			goto err;
-		}
-
-		if (!prev_lm_width && !prev_lm_height) {
-			prev_lm_width = cfg->lm_width;
-			prev_lm_height = cfg->lm_height;
-		} else {
-			if (cfg->lm_width != prev_lm_width ||
-				cfg->lm_height != prev_lm_height) {
-				DPU_ERROR("lm size:left[%d,%d], right[%d %d]\n",
-					cfg->lm_width, cfg->lm_height,
-					prev_lm_width, prev_lm_height);
-				ret = -EINVAL;
-				goto err;
-			}
-		}
-
-		/* Check scaler data */
-		if (cfg->flags & DPU_DRM_DESTSCALER_SCALE_UPDATE ||
-			cfg->flags & DPU_DRM_DESTSCALER_ENHANCER_UPDATE) {
-			if (!cfg->scl3_cfg) {
-				ret = -EINVAL;
-				DPU_ERROR("null scale data\n");
-				goto err;
-			}
-			if (cfg->scl3_cfg->src_width[0] > max_in_width ||
-				cfg->scl3_cfg->dst_width > max_out_width ||
-				!cfg->scl3_cfg->src_width[0] ||
-				!cfg->scl3_cfg->dst_width) {
-				DPU_ERROR("scale width(%d %d) for ds-%d:\n",
-					cfg->scl3_cfg->src_width[0],
-					cfg->scl3_cfg->dst_width,
-					hw_ds->idx - DS_0);
-				DPU_ERROR("scale_en = %d, DE_en =%d\n",
-					cfg->scl3_cfg->enable,
-					cfg->scl3_cfg->de.enable);
-
-				cfg->flags &=
-					~DPU_DRM_DESTSCALER_SCALE_UPDATE;
-				cfg->flags &=
-					~DPU_DRM_DESTSCALER_ENHANCER_UPDATE;
-
-				ret = -EINVAL;
-				goto err;
-			}
-		}
-
-		if (cfg->flags & DPU_DRM_DESTSCALER_ENABLE)
-			num_ds_enable++;
-
-		/**
-		 * Validation successful, indicator for flush to be issued
-		 */
-		cfg->set_lm_flush = true;
-
-		DPU_DEBUG("ds[%d]: flags = 0x%X\n",
-			hw_ds->idx - DS_0, cfg->flags);
-	}
-
-disable:
-	DPU_DEBUG("dest scaler enable status, old = %d, new = %d",
-		cstate->num_ds_enabled, num_ds_enable);
-	DPU_EVT32(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
-		cstate->ds_dirty);
-
-	if (cstate->num_ds_enabled != num_ds_enable) {
-		/* Disabling destination scaler */
-		if (!num_ds_enable) {
-			for (i = 0; i < dpu_crtc->num_mixers; i++) {
-				cfg = &cstate->ds_cfg[i];
-				cfg->ndx = i;
-				/* Update scaler settings in disable case */
-				cfg->flags = DPU_DRM_DESTSCALER_SCALE_UPDATE;
-				cfg->scl3_cfg->enable = 0;
-				cfg->scl3_cfg->de.enable = 0;
-				cfg->set_lm_flush = true;
-			}
-		}
-		cstate->num_ds_enabled = num_ds_enable;
-		cstate->ds_dirty = true;
-	}
-
-	return 0;
-
-err:
-	cstate->ds_dirty = false;
-	return ret;
-}
-
 static void _dpu_crtc_setup_mixer_for_encoder(
 		struct drm_crtc *crtc,
 		struct drm_encoder *enc)

@@ -1813,11 +1123,10 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 	struct dpu_crtc_mixer *mixer;
 	struct dpu_hw_ctl *last_valid_ctl = NULL;
 	int i;
-	struct dpu_rm_hw_iter lm_iter, ctl_iter, ds_iter;
+	struct dpu_rm_hw_iter lm_iter, ctl_iter;
 
 	dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM);
 	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
-	dpu_rm_init_hw_iter(&ds_iter, enc->base.id, DPU_HW_BLK_DS);
 
 	/* Set up all the mixers and ctls reserved by this encoder */
 	for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers); i++) {

@@ -1844,10 +1153,6 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 			return;
 		}
 
-		/* DS may be null */
-		(void) dpu_rm_get_hw(rm, &ds_iter);
-		mixer->hw_ds = (struct dpu_hw_ds *)ds_iter.hw;
-
 		mixer->encoder = enc;
 
 		dpu_crtc->num_mixers++;

@@ -1855,9 +1160,6 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 				i, mixer->hw_lm->idx - LM_0);
 		DPU_DEBUG("setup mixer %d: ctl %d\n",
 				i, mixer->hw_ctl->idx - CTL_0);
-		if (mixer->hw_ds)
-			DPU_DEBUG("setup mixer %d: ds %d\n",
-				i, mixer->hw_ds->idx - DS_0);
 	}
 }
 

@@ -1973,7 +1275,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 		return;
 
 	_dpu_crtc_blend_setup(crtc);
-	_dpu_crtc_dest_scaler_setup(crtc);
 
 	/*
 	 * PP_DONE irq is only used by command mode for now.

@@ -2672,13 +1973,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 	memset(pipe_staged, 0, sizeof(pipe_staged));
 
-	rc = _dpu_crtc_check_dest_scaler_data(crtc, state);
-	if (rc) {
-		DPU_ERROR("crtc%d failed dest scaler check %d\n",
-			crtc->base.id, rc);
-		goto end;
-	}
-
 	mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
 	_dpu_crtc_setup_lm_bounds(crtc, state);

@@ -2699,19 +1993,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		pstates[cnt].stage = pstate->normalized_zpos;
 		pstates[cnt].pipe_id = dpu_plane_pipe(plane);
 
-		/* check dim layer stage with every plane */
-		for (i = 0; i < cstate->num_dim_layers; i++) {
-			if (cstate->dim_layer[i].stage
-					== (pstates[cnt].stage + DPU_STAGE_0)) {
-				DPU_ERROR(
-					"plane:%d/dim_layer:%i-same stage:%d\n",
-					plane->base.id, i,
-					cstate->dim_layer[i].stage);
-				rc = -EINVAL;
-				goto end;
-			}
-		}
-
 		if (pipe_staged[pstates[cnt].pipe_id]) {
 			multirect_plane[multirect_count].r0 =
 				pipe_staged[pstates[cnt].pipe_id];

@@ -2947,52 +2228,11 @@ static void dpu_crtc_install_properties(struct drm_crtc *crtc,
 		return;
 	}
 
-	/* range properties */
-	msm_property_install_range(&dpu_crtc->property_info,
-			"core_clk", 0x0, 0, U64_MAX,
-			dpu_kms->perf.max_core_clk_rate,
-			CRTC_PROP_CORE_CLK);
-	msm_property_install_range(&dpu_crtc->property_info,
-			"core_ab", 0x0, 0, U64_MAX,
-			catalog->perf.max_bw_high * 1000ULL,
-			CRTC_PROP_CORE_AB);
-	msm_property_install_range(&dpu_crtc->property_info,
-			"core_ib", 0x0, 0, U64_MAX,
-			catalog->perf.max_bw_high * 1000ULL,
-			CRTC_PROP_CORE_IB);
-	msm_property_install_range(&dpu_crtc->property_info,
-			"llcc_ab", 0x0, 0, U64_MAX,
-			catalog->perf.max_bw_high * 1000ULL,
-			CRTC_PROP_LLCC_AB);
-	msm_property_install_range(&dpu_crtc->property_info,
-			"llcc_ib", 0x0, 0, U64_MAX,
-			catalog->perf.max_bw_high * 1000ULL,
-			CRTC_PROP_LLCC_IB);
-	msm_property_install_range(&dpu_crtc->property_info,
-			"dram_ab", 0x0, 0, U64_MAX,
-			catalog->perf.max_bw_high * 1000ULL,
-			CRTC_PROP_DRAM_AB);
-	msm_property_install_range(&dpu_crtc->property_info,
-			"dram_ib", 0x0, 0, U64_MAX,
-			catalog->perf.max_bw_high * 1000ULL,
-			CRTC_PROP_DRAM_IB);
-
-	msm_property_install_range(&dpu_crtc->property_info,
-		"idle_timeout", IDLE_TIMEOUT, 0, U64_MAX, 0,
-		CRTC_PROP_IDLE_TIMEOUT);
-
 	msm_property_install_blob(&dpu_crtc->property_info, "capabilities",
 		DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
 
 	dpu_kms_info_reset(info);
 
-	if (catalog->caps->has_dim_layer) {
-		msm_property_install_volatile_range(&dpu_crtc->property_info,
-			"dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
-		dpu_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
-				DPU_MAX_DIM_LAYERS);
-	}
-
 	dpu_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
 	dpu_kms_info_add_keyint(info, "max_linewidth",
 			catalog->caps->max_mixer_width);

@@ -3012,39 +2252,6 @@ static void dpu_crtc_install_properties(struct drm_crtc *crtc,
 					"smart_dma_rev", "smart_dma_v2");
 	}
 
-	if (catalog->mdp[0].has_dest_scaler) {
-		dpu_kms_info_add_keyint(info, "has_dest_scaler",
-				catalog->mdp[0].has_dest_scaler);
-		dpu_kms_info_add_keyint(info, "dest_scaler_count",
-					catalog->ds_count);
-
-		if (catalog->ds[0].top) {
-			dpu_kms_info_add_keyint(info,
-					"max_dest_scaler_input_width",
-					catalog->ds[0].top->maxinputwidth);
-			dpu_kms_info_add_keyint(info,
-					"max_dest_scaler_output_width",
-					catalog->ds[0].top->maxinputwidth);
-			dpu_kms_info_add_keyint(info, "max_dest_scale_up",
-					catalog->ds[0].top->maxupscale);
-		}
-
-		if (catalog->ds[0].features & BIT(DPU_SSPP_SCALER_QSEED3)) {
-			msm_property_install_volatile_range(
-					&dpu_crtc->property_info, "dest_scaler",
-					0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
-			msm_property_install_blob(&dpu_crtc->property_info,
-					"ds_lut_ed", 0,
-					CRTC_PROP_DEST_SCALER_LUT_ED);
-			msm_property_install_blob(&dpu_crtc->property_info,
-					"ds_lut_cir", 0,
-					CRTC_PROP_DEST_SCALER_LUT_CIR);
-			msm_property_install_blob(&dpu_crtc->property_info,
-					"ds_lut_sep", 0,
-					CRTC_PROP_DEST_SCALER_LUT_SEP);
-		}
-	}
-
 	dpu_kms_info_add_keyint(info, "has_src_split",
 				catalog->caps->has_src_split);
 	if (catalog->perf.max_bw_low)

@@ -3113,7 +2320,7 @@ static int dpu_crtc_atomic_set_property(struct drm_crtc *crtc,
 {
 	struct dpu_crtc *dpu_crtc;
 	struct dpu_crtc_state *cstate;
-	int idx, ret = -EINVAL;
+	int ret = -EINVAL;
 
 	if (!crtc || !state || !property) {
 		DPU_ERROR("invalid argument(s)\n");

@@ -3122,45 +2329,8 @@ static int dpu_crtc_atomic_set_property(struct drm_crtc *crtc,
 		cstate = to_dpu_crtc_state(state);
 		ret = msm_property_atomic_set(&dpu_crtc->property_info,
 				&cstate->property_state, property, val);
-		if (!ret) {
-			idx = msm_property_index(&dpu_crtc->property_info,
-					property);
-			switch (idx) {
-			case CRTC_PROP_DIM_LAYER_V1:
-				_dpu_crtc_set_dim_layer_v1(cstate,
-							u64_to_user_ptr(val));
-				break;
-			case CRTC_PROP_DEST_SCALER:
-				ret = _dpu_crtc_set_dest_scaler(dpu_crtc,
-						cstate, u64_to_user_ptr(val));
-				break;
-			case CRTC_PROP_DEST_SCALER_LUT_ED:
-			case CRTC_PROP_DEST_SCALER_LUT_CIR:
-			case CRTC_PROP_DEST_SCALER_LUT_SEP:
-				ret = _dpu_crtc_set_dest_scaler_lut(dpu_crtc,
-								cstate, idx);
-				break;
-			case CRTC_PROP_CORE_CLK:
-			case CRTC_PROP_CORE_AB:
-			case CRTC_PROP_CORE_IB:
-				cstate->bw_control = true;
-				break;
-			case CRTC_PROP_LLCC_AB:
-			case CRTC_PROP_LLCC_IB:
-			case CRTC_PROP_DRAM_AB:
-			case CRTC_PROP_DRAM_IB:
-				cstate->bw_control = true;
-				cstate->bw_split_vote = true;
-				break;
-			case CRTC_PROP_IDLE_TIMEOUT:
-				_dpu_crtc_set_idle_timeout(crtc, val);
-			default:
-				/* nothing to do */
-				break;
-			}
-		} else {
+		if (ret)
 			DRM_ERROR("failed to set the property\n");
-		}
 
 		DPU_DEBUG("crtc%d %s[%d] <= 0x%llx ret=%d\n", crtc->base.id,
 				property->name, property->base.id, val, ret);

@@ -3276,23 +2446,6 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
 
 	seq_puts(s, "\n");
 
-	for (i = 0; i < cstate->num_dim_layers; i++) {
-		struct dpu_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
-
-		seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
-				i, dim_layer->stage, dim_layer->flags);
-		seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
-				dim_layer->rect.x, dim_layer->rect.y,
-				dim_layer->rect.w, dim_layer->rect.h);
-		seq_printf(s,
-			"\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
-				dim_layer->color_fill.color_0,
-				dim_layer->color_fill.color_1,
-				dim_layer->color_fill.color_2,
-				dim_layer->color_fill.color_3);
-		seq_puts(s, "\n");
-	}
-
 	drm_atomic_crtc_for_each_plane(plane, crtc) {
 		pstate = to_dpu_plane_state(plane->state);
 		state = plane->state;

@@ -3779,9 +2932,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
 
 	dpu_crtc_install_properties(crtc, kms->catalog);
 
-	/* Init dest scaler */
-	_dpu_crtc_dest_scaler_init(dpu_crtc, kms->catalog);
-
 	DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);
 	return crtc;
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +3 -24

index 5f380b8..6628eb3 100644
@@ -26,7 +26,6 @@
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"
 #include "dpu_hw_blk.h"
-#include "dpu_hw_ds.h"
 
 #define DPU_CRTC_NAME_SIZE	12
 

@@ -87,7 +86,6 @@ struct dpu_crtc_smmu_state_data {
  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
  * @hw_lm:	LM HW Driver context
  * @hw_ctl:	CTL Path HW driver context
- * @hw_ds:	DS HW driver context
  * @encoder:	Encoder attached to this lm & ctl
  * @mixer_op_mode:	mixer blending operation mode
  * @flush_mask:	mixer flush mask for ctl, mixer and pipe

@@ -95,7 +93,6 @@ struct dpu_crtc_smmu_state_data {
 struct dpu_crtc_mixer {
 	struct dpu_hw_mixer *hw_lm;
 	struct dpu_hw_ctl *hw_ctl;
-	struct dpu_hw_ds *hw_ds;
 	struct drm_encoder *encoder;
 	u32 mixer_op_mode;
 	u32 flush_mask;

@@ -314,12 +311,6 @@ struct dpu_crtc_respool {
  * @property_state: Local storage for msm_prop properties
  * @property_values: Current crtc property values
  * @input_fence_timeout_ns : Cached input fence timeout, in ns
- * @num_dim_layers: Number of dim layers
- * @dim_layer: Dim layer configs
- * @num_ds: Number of destination scalers to be configured
- * @num_ds_enabled: Number of destination scalers enabled
- * @ds_dirty: Boolean to indicate if dirty or not
- * @ds_cfg: Destination scaler config
  * @new_perf: new performance state being requested
  */
 struct dpu_crtc_state {

@@ -336,12 +327,6 @@ struct dpu_crtc_state {
 	struct msm_property_state property_state;
 	struct msm_property_value property_values[CRTC_PROP_COUNT];
 	uint64_t input_fence_timeout_ns;
-	uint32_t num_dim_layers;
-	struct dpu_hw_dim_layer dim_layer[DPU_MAX_DIM_LAYERS];
-	uint32_t num_ds;
-	uint32_t num_ds_enabled;
-	bool ds_dirty;
-	struct dpu_hw_ds_cfg ds_cfg[DPU_MAX_DS_COUNT];
 
 	struct dpu_core_perf_params new_perf;
 	struct dpu_crtc_respool rp;

@@ -362,7 +347,6 @@ struct dpu_crtc_state {
 /**
  * dpu_crtc_get_mixer_width - get the mixer width
  * Mixer width will be same as panel width(/2 for split)
- * unless destination scaler feature is enabled
  */
 static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
 	struct dpu_crtc_state *cstate, struct drm_display_mode *mode)

@@ -372,10 +356,7 @@ static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
 	if (!dpu_crtc || !cstate || !mode)
 		return 0;
 
-	if (cstate->num_ds_enabled)
-		mixer_width = cstate->ds_cfg[0].lm_width;
-	else
-		mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
+	mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
 			mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
 
 	return mixer_width;

@@ -383,8 +364,7 @@ static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
 
 /**
  * dpu_crtc_get_mixer_height - get the mixer height
- * Mixer height will be same as panel height unless
- * destination scaler feature is enabled
+ * Mixer height will be same as panel height
  */
 static inline int dpu_crtc_get_mixer_height(struct dpu_crtc *dpu_crtc,
 		struct dpu_crtc_state *cstate, struct drm_display_mode *mode)

@@ -392,8 +372,7 @@ static inline int dpu_crtc_get_mixer_height(struct dpu_crtc *dpu_crtc,
 	if (!dpu_crtc || !cstate || !mode)
 		return 0;
 
-	return (cstate->num_ds_enabled ?
-			cstate->ds_cfg[0].lm_height : mode->vdisplay);
+	return mode->vdisplay;
 }
 
 /**

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +0 -12

index 77d3571..62660e0 100644
@@ -230,18 +230,6 @@ struct dpu_encoder_virt {
 };
 
 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
-
-void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, u32 idle_timeout)
-{
-	struct dpu_encoder_virt *dpu_enc;
-
-	if (!drm_enc)
-		return;
-
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
-	dpu_enc->idle_timeout = idle_timeout;
-}
-
 static inline int _dpu_encoder_power_enable(struct dpu_encoder_virt *dpu_enc,
 								bool enable)
 {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c deleted +0 -149

deleted file mode 100644
index fad19fb..0000000
@@ -1,149 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "dpu_hw_ds.h"
-#include "dpu_formats.h"
-#include "dpu_dbg.h"
-#include "dpu_kms.h"
-
-/* Destination scaler TOP registers */
-#define DEST_SCALER_OP_MODE     0x00
-#define DEST_SCALER_HW_VERSION  0x10
-
-static void dpu_hw_ds_setup_opmode(struct dpu_hw_ds *hw_ds,
-				u32 op_mode)
-{
-	struct dpu_hw_blk_reg_map *hw = &hw_ds->hw;
-
-	DPU_REG_WRITE(hw, DEST_SCALER_OP_MODE, op_mode);
-}
-
-static void dpu_hw_ds_setup_scaler3(struct dpu_hw_ds *hw_ds,
-			void *scaler_cfg, void *scaler_lut_cfg)
-{
-	struct dpu_hw_scaler3_cfg *scl3_cfg = scaler_cfg;
-	struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg = scaler_lut_cfg;
-
-	if (!hw_ds || !hw_ds->scl || !scl3_cfg || !scl3_lut_cfg)
-		return;
-
-	/*
-	 * copy LUT values to scaler structure
-	 */
-	if (scl3_lut_cfg->is_configured) {
-		scl3_cfg->dir_lut = scl3_lut_cfg->dir_lut;
-		scl3_cfg->dir_len = scl3_lut_cfg->dir_len;
-		scl3_cfg->cir_lut = scl3_lut_cfg->cir_lut;
-		scl3_cfg->cir_len = scl3_lut_cfg->cir_len;
-		scl3_cfg->sep_lut = scl3_lut_cfg->sep_lut;
-		scl3_cfg->sep_len = scl3_lut_cfg->sep_len;
-	}
-
-	dpu_hw_setup_scaler3(&hw_ds->hw, scl3_cfg,
-			 hw_ds->scl->base,
-			 hw_ds->scl->version,
-			 dpu_get_dpu_format(DRM_FORMAT_XBGR2101010));
-}
-
-static void _setup_ds_ops(struct dpu_hw_ds_ops *ops, unsigned long features)
-{
-	ops->setup_opmode = dpu_hw_ds_setup_opmode;
-
-	if (test_bit(DPU_SSPP_SCALER_QSEED3, &features))
-		ops->setup_scaler = dpu_hw_ds_setup_scaler3;
-}
-
-static struct dpu_ds_cfg *_ds_offset(enum dpu_ds ds,
-		struct dpu_mdss_cfg *m,
-		void __iomem *addr,
-		struct dpu_hw_blk_reg_map *b)
-{
-	int i;
-
-	if (!m || !addr || !b)
-		return ERR_PTR(-EINVAL);
-
-	for (i = 0; i < m->ds_count; i++) {
-		if ((ds == m->ds[i].id) &&
-			 (m->ds[i].top)) {
-			b->base_off = addr;
-			b->blk_off = m->ds[i].top->base;
-			b->length = m->ds[i].top->len;
-			b->hwversion = m->hwversion;
-			b->log_mask = DPU_DBG_MASK_DS;
-			return &m->ds[i];
-		}
-	}
-
-	return ERR_PTR(-EINVAL);
-}
-
-static struct dpu_hw_blk_ops dpu_hw_ops = {
-	.start = NULL,
-	.stop = NULL,
-};
-
-struct dpu_hw_ds *dpu_hw_ds_init(enum dpu_ds idx,
-			void __iomem *addr,
-			struct dpu_mdss_cfg *m)
-{
-	struct dpu_hw_ds *hw_ds;
-	struct dpu_ds_cfg *cfg;
-	int rc;
-
-	if (!addr || !m)
-		return ERR_PTR(-EINVAL);
-
-	hw_ds = kzalloc(sizeof(*hw_ds), GFP_KERNEL);
-	if (!hw_ds)
-		return ERR_PTR(-ENOMEM);
-
-	cfg = _ds_offset(idx, m, addr, &hw_ds->hw);
-	if (IS_ERR_OR_NULL(cfg)) {
-		DPU_ERROR("failed to get ds cfg\n");
-		kfree(hw_ds);
-		return ERR_PTR(-EINVAL);
-	}
-
-	/* Assign ops */
-	hw_ds->idx = idx;
-	hw_ds->scl = cfg;
-	_setup_ds_ops(&hw_ds->ops, hw_ds->scl->features);
-
-	rc = dpu_hw_blk_init(&hw_ds->base, DPU_HW_BLK_DS, idx, &dpu_hw_ops);
-	if (rc) {
-		DPU_ERROR("failed to init hw blk %d\n", rc);
-		goto blk_init_error;
-	}
-
-	if (cfg->len) {
-		dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name,
-				hw_ds->hw.blk_off + cfg->base,
-				hw_ds->hw.blk_off + cfg->base + cfg->len,
-				hw_ds->hw.xin_id);
-	}
-
-	return hw_ds;
-
-blk_init_error:
-	kzfree(hw_ds);
-
-	return ERR_PTR(rc);
-
-}
-
-void dpu_hw_ds_destroy(struct dpu_hw_ds *hw_ds)
-{
-	if (hw_ds)
-		dpu_hw_blk_destroy(&hw_ds->base);
-	kfree(hw_ds);
-}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h deleted +0 -111

deleted file mode 100644
index 2455920..0000000
@@ -1,111 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DPU_HW_DS_H
-#define _DPU_HW_DS_H
-
-#include "dpu_hw_mdss.h"
-#include "dpu_hw_util.h"
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_blk.h"
-
-struct dpu_hw_ds;
-
-/* Destination Scaler DUAL mode overfetch pixel count */
-#define DPU_DS_OVERFETCH_SIZE 5
-
-/* Destination scaler DUAL mode operation bit */
-#define DPU_DS_OP_MODE_DUAL BIT(16)
-
-/* struct dpu_hw_ds_cfg - destination scaler config
- * @ndx          : DS selection index
- * @flags        : Flag to switch between mode for DS
- * @lm_width     : Layer mixer width configuration
- * @lm_heigh     : Layer mixer height configuration
- * @set_lm_flush : LM flush bit
- * @scl3_cfg     : Pointer to dpu_hw_scaler3_cfg.
- */
-struct dpu_hw_ds_cfg {
-	u32 ndx;
-	int flags;
-	u32 lm_width;
-	u32 lm_height;
-	bool set_lm_flush;
-	struct dpu_hw_scaler3_cfg *scl3_cfg;
-};
-
-/**
- * struct dpu_hw_ds_ops - interface to the destination scaler
- * hardware driver functions
- * Caller must call the init function to get the ds context for each ds
- * Assumption is these functions will be called after clocks are enabled
- */
-struct dpu_hw_ds_ops {
-	/**
-	 * setup_opmode - destination scaler op mode setup
-	 * @hw_ds   : Pointer to ds context
-	 * @op_mode : Op mode configuration
-	 */
-	void (*setup_opmode)(struct dpu_hw_ds *hw_ds,
-				u32 op_mode);
-
-	/**
-	 * setup_scaler - destination scaler block setup
-	 * @hw_ds          : Pointer to ds context
-	 * @scaler_cfg     : Pointer to scaler data
-	 * @scaler_lut_cfg : Pointer to scaler lut
-	 */
-	void (*setup_scaler)(struct dpu_hw_ds *hw_ds,
-				void *scaler_cfg,
-				void *scaler_lut_cfg);
-
-};
-
-/**
- * struct dpu_hw_ds - destination scaler description
- * @base : Hardware block base structure
- * @hw   : Block hardware details
- * @idx  : Destination scaler index
- * @scl  : Pointer to
- *          - scaler offset relative to top offset
- *          - capabilities
- * @ops  : Pointer to operations for this DS
- */
-struct dpu_hw_ds {
-	struct dpu_hw_blk base;
-	struct dpu_hw_blk_reg_map hw;
-	enum dpu_ds idx;
-	const struct dpu_ds_cfg *scl;
-	struct dpu_hw_ds_ops ops;
-};
-
-/**
- * dpu_hw_ds_init - initializes the destination scaler
- * hw driver object and should be called once before
- * accessing every destination scaler
- * @idx : DS index for which driver object is required
- * @addr: Mapped register io address of MDP
- * @m   : MDSS catalog information
- * @Return: pointer to structure or ERR_PTR
- */
-struct dpu_hw_ds *dpu_hw_ds_init(enum dpu_ds idx,
-			void __iomem *addr,
-			struct dpu_mdss_cfg *m);
-
-/**
- * dpu_hw_ds_destroy - destroys destination scaler
- * driver context
- * @hw_ds:   Pointer to DS context
- */
-void dpu_hw_ds_destroy(struct dpu_hw_ds *hw_ds);
-
-#endif /*_DPU_HW_DS_H */

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +0 -67

index 75a30db..830b69e 100644
@@ -172,68 +172,6 @@ static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer,
 {
 }
 
-static void dpu_hw_lm_clear_dim_layer(struct dpu_hw_mixer *ctx)
-{
-	struct dpu_hw_blk_reg_map *c = &ctx->hw;
-	const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk;
-	int stage_off, i;
-	u32 reset = BIT(16), val;
-
-	reset = ~reset;
-	for (i = DPU_STAGE_0; i < sblk->maxblendstages; i++) {
-		stage_off = _stage_offset(ctx, i);
-		if (WARN_ON(stage_off < 0))
-			return;
-
-		/*
-		 * read the existing blendn_op register and clear only DIM layer
-		 * bit (color_fill bit)
-		 */
-		val = DPU_REG_READ(c, LM_BLEND0_OP + stage_off);
-		val &= reset;
-		DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, val);
-	}
-}
-
-static void dpu_hw_lm_setup_dim_layer(struct dpu_hw_mixer *ctx,
-		struct dpu_hw_dim_layer *dim_layer)
-{
-	struct dpu_hw_blk_reg_map *c = &ctx->hw;
-	int stage_off;
-	u32 val = 0, alpha = 0;
-
-	stage_off = _stage_offset(ctx, dim_layer->stage);
-	if (stage_off < 0) {
-		DPU_ERROR("invalid stage_off:%d for dim layer\n", stage_off);
-		return;
-	}
-
-	alpha = dim_layer->color_fill.color_3 & 0xFF;
-	val = ((dim_layer->color_fill.color_1 << 2) & 0xFFF) << 16 |
-			((dim_layer->color_fill.color_0 << 2) & 0xFFF);
-	DPU_REG_WRITE(c, LM_FG_COLOR_FILL_COLOR_0 + stage_off, val);
-
-	val = (alpha << 4) << 16 |
-			((dim_layer->color_fill.color_2 << 2) & 0xFFF);
-	DPU_REG_WRITE(c, LM_FG_COLOR_FILL_COLOR_1 + stage_off, val);
-
-	val = dim_layer->rect.h << 16 | dim_layer->rect.w;
-	DPU_REG_WRITE(c, LM_FG_COLOR_FILL_SIZE + stage_off, val);
-
-	val = dim_layer->rect.y << 16 | dim_layer->rect.x;
-	DPU_REG_WRITE(c, LM_FG_COLOR_FILL_XY + stage_off, val);
-
-	val = BIT(16); /* enable dim layer */
-	val |= DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_BG_CONST;
-	if (dim_layer->flags & DPU_DRM_DIM_LAYER_EXCLUSIVE)
-		val |= BIT(17);
-	else
-		val &= ~BIT(17);
-	DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, val);
-	val = (alpha << 16) | (0xff - alpha);
-	DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, val);
-}
-
 static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx,
 				bool enable, u32 frame_count)
 {

@@ -272,11 +210,6 @@ static void _setup_mixer_ops(struct dpu_mdss_cfg *m,
 	ops->setup_gc = dpu_hw_lm_gc;
 	ops->setup_misr = dpu_hw_lm_setup_misr;
 	ops->collect_misr = dpu_hw_lm_collect_misr;
-
-	if (test_bit(DPU_DIM_LAYER, &features)) {
-		ops->setup_dim_layer = dpu_hw_lm_setup_dim_layer;
-		ops->clear_dim_layer = dpu_hw_lm_clear_dim_layer;
-	}
 };
 
 static struct dpu_hw_blk_ops dpu_hw_ops = {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +0 -14

index ef22c86..e29e5da 100644
@@ -67,20 +67,6 @@ struct dpu_hw_lm_ops {
 	void (*setup_gc)(struct dpu_hw_mixer *mixer,
 			void *cfg);
 
-	/**
-	 * setup_dim_layer: configure dim layer settings
-	 * @ctx: Pointer to layer mixer context
-	 * @dim_layer: dim layer configs
-	 */
-	void (*setup_dim_layer)(struct dpu_hw_mixer *ctx,
-			struct dpu_hw_dim_layer *dim_layer);
-
-	/**
-	 * clear_dim_layer: clear dim layer settings
-	 * @ctx: Pointer to layer mixer context
-	 */
-	void (*clear_dim_layer)(struct dpu_hw_mixer *ctx);
-
 	/* setup_misr: enables/disables MISR in HW register */
 	void (*setup_misr)(struct dpu_hw_mixer *ctx,
 			bool enable, u32 frame_count);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +0 -16

index fcd164f..836ff9e 100644
@@ -99,7 +99,6 @@ enum dpu_hw_blk_type {
 	DPU_HW_BLK_TOP = 0,
 	DPU_HW_BLK_SSPP,
 	DPU_HW_BLK_LM,
-	DPU_HW_BLK_DS,
 	DPU_HW_BLK_CTL,
 	DPU_HW_BLK_CDM,
 	DPU_HW_BLK_PINGPONG,

@@ -469,20 +468,5 @@ struct dpu_mdss_color {
 #define DPU_DBG_MASK_TOP      (1 << 8)
 #define DPU_DBG_MASK_VBIF     (1 << 9)
 #define DPU_DBG_MASK_ROT      (1 << 10)
-#define DPU_DBG_MASK_DS       (1 << 11)
-
-/**
- * struct dpu_hw_dim_layer: dim layer configs
- * @flags: Flag to represent INCLUSIVE/EXCLUSIVE
- * @stage: Blending stage of dim layer
- * @color_fill: Color fill to be used for the layer
- * @rect: Dim layer coordinates
- */
-struct dpu_hw_dim_layer {
-	uint32_t flags;
-	uint32_t stage;
-	struct dpu_mdss_color color_fill;
-	struct dpu_rect rect;
-};
 
 #endif  /* _DPU_HW_MDSS_H */

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +5 -66

index f467bf1..0af2996 100644
@@ -17,7 +17,6 @@
 #include "dpu_hw_lm.h"
 #include "dpu_hw_ctl.h"
 #include "dpu_hw_cdm.h"
-#include "dpu_hw_ds.h"
 #include "dpu_hw_pingpong.h"
 #include "dpu_hw_intf.h"
 #include "dpu_hw_wb.h"

@@ -235,9 +234,6 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
 	case DPU_HW_BLK_LM:
 		dpu_hw_lm_destroy(hw);
 		break;
-	case DPU_HW_BLK_DS:
-		dpu_hw_ds_destroy(hw);
-		break;
 	case DPU_HW_BLK_CTL:
 		dpu_hw_ctl_destroy(hw);
 		break;

@@ -317,9 +313,6 @@ static int _dpu_rm_hw_blk_create(
 	case DPU_HW_BLK_LM:
 		hw = dpu_hw_lm_init(id, mmio, cat);
 		break;
-	case DPU_HW_BLK_DS:
-		hw = dpu_hw_ds_init(id, mmio, cat);
-		break;
 	case DPU_HW_BLK_CTL:
 		hw = dpu_hw_ctl_init(id, mmio, cat);
 		break;

@@ -427,17 +420,6 @@ int dpu_rm_init(struct dpu_rm *rm,
 		}
 	}
 
-	if (cat->mdp[0].has_dest_scaler) {
-		for (i = 0; i < cat->ds_count; i++) {
-			rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_DS,
-					cat->ds[i].id, &cat->ds[i]);
-			if (rc) {
-				DPU_ERROR("failed: ds hw not available\n");
-				goto fail;
-			}
-		}
-	}
-
 	for (i = 0; i < cat->pingpong_count; i++) {
 		rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_PINGPONG,
 				cat->pingpong[i].id, &cat->pingpong[i]);

@@ -516,20 +498,16 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm_rsvp *rsvp,
 		struct dpu_rm_requirements *reqs,
 		struct dpu_rm_hw_blk *lm,
-		struct dpu_rm_hw_blk **ds,
 		struct dpu_rm_hw_blk **pp,
 		struct dpu_rm_hw_blk *primary_lm)
 {
 	const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
 	struct dpu_rm_hw_iter iter;
-	bool is_valid_ds;
 
-	*ds = NULL;
 	*pp = NULL;
 
-	DPU_DEBUG("check lm %d ds %d pp %d\n",
-			   lm_cfg->id,
-			   lm_cfg->ds, lm_cfg->pingpong);
+	DPU_DEBUG("check lm %d pp %d\n",
+			   lm_cfg->id, lm_cfg->pingpong);
 
 	/* Check if this layer mixer is a peer of the proposed primary LM */
 	if (primary_lm) {

@@ -543,43 +521,12 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		}
 	}
 
-	is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
-
-	if (RM_RQ_DS(reqs) && !is_valid_ds) {
-		DPU_DEBUG("fail:lm(%d)req_ds(%d)ds(%d)\n",
-			lm_cfg->id, (bool)(RM_RQ_DS(reqs)), lm_cfg->ds);
-
-		return false;
-	}
-
 	/* Already reserved? */
 	if (RESERVED_BY_OTHER(lm, rsvp)) {
 		DPU_DEBUG("lm %d already reserved\n", lm_cfg->id);
 		return false;
 	}
 
-	if (lm_cfg->ds != DS_MAX) {
-		dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_DS);
-		while (_dpu_rm_get_hw_locked(rm, &iter)) {
-			if (iter.blk->id == lm_cfg->ds) {
-				*ds = iter.blk;
-				break;
-			}
-		}
-
-		if (!*ds) {
-			DPU_DEBUG("lm %d failed to retrieve ds %d\n", lm->id,
-					lm_cfg->ds);
-			return false;
-		}
-
-		if (RESERVED_BY_OTHER(*ds, rsvp)) {
-			DPU_DEBUG("lm %d ds %d already reserved\n",
-					lm->id, (*ds)->id);
-			return false;
-		}
-	}
-
 	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		if (iter.blk->id == lm_cfg->pingpong) {

@@ -596,7 +543,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 	if (RESERVED_BY_OTHER(*pp, rsvp)) {
 		DPU_DEBUG("lm %d pp %d already reserved\n", lm->id,
 				(*pp)->id);
-		*ds = NULL;
 		return false;
 	}
 

@@ -610,7 +556,6 @@ static int _dpu_rm_reserve_lms(
 
 {
 	struct dpu_rm_hw_blk *lm[MAX_BLOCKS];
-	struct dpu_rm_hw_blk *ds[MAX_BLOCKS];
 	struct dpu_rm_hw_blk *pp[MAX_BLOCKS];
 	struct dpu_rm_hw_iter iter_i, iter_j;
 	int lm_count = 0;

@@ -626,14 +571,13 @@ static int _dpu_rm_reserve_lms(
 	while (lm_count != reqs->topology->num_lm &&
 			_dpu_rm_get_hw_locked(rm, &iter_i)) {
 		memset(&lm, 0, sizeof(lm));
-		memset(&ds, 0, sizeof(ds));
 		memset(&pp, 0, sizeof(pp));
 
 		lm_count = 0;
 		lm[lm_count] = iter_i.blk;
 
 		if (!_dpu_rm_check_lm_and_get_connected_blks(
-				rm, rsvp, reqs, lm[lm_count], &ds[lm_count],
+				rm, rsvp, reqs, lm[lm_count],
 				&pp[lm_count], NULL))
 			continue;
 

@@ -649,8 +593,7 @@ static int _dpu_rm_reserve_lms(
 
 			if (!_dpu_rm_check_lm_and_get_connected_blks(
 					rm, rsvp, reqs, iter_j.blk,
-					&ds[lm_count], &pp[lm_count],
-					iter_i.blk))
+					&pp[lm_count], iter_i.blk))
 				continue;
 
 			lm[lm_count] = iter_j.blk;

@@ -670,11 +613,7 @@ static int _dpu_rm_reserve_lms(
 		lm[i]->rsvp_nxt = rsvp;
 		pp[i]->rsvp_nxt = rsvp;
 
-		if (ds[i])
-			ds[i]->rsvp_nxt = rsvp;
-
-		DPU_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
-				ds[i] ? ds[i]->id : 0);
+		DPU_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id);
 	}
 
 	return rc;

drivers/gpu/drm/msm/msm_drv.h +0 -15

index 5baff27..8e80b4b 100644
@@ -89,25 +89,10 @@ enum msm_mdp_plane_property {
 
 enum msm_mdp_crtc_property {
 	CRTC_PROP_INFO,
-	CRTC_PROP_DEST_SCALER_LUT_ED,
-	CRTC_PROP_DEST_SCALER_LUT_CIR,
-	CRTC_PROP_DEST_SCALER_LUT_SEP,
 
 	/* # of blob properties */
 	CRTC_PROP_BLOBCOUNT,
 
-	/* range properties */
-	CRTC_PROP_DIM_LAYER_V1 = CRTC_PROP_BLOBCOUNT,
-	CRTC_PROP_CORE_CLK,
-	CRTC_PROP_CORE_AB,
-	CRTC_PROP_CORE_IB,
-	CRTC_PROP_LLCC_AB,
-	CRTC_PROP_LLCC_IB,
-	CRTC_PROP_DRAM_AB,
-	CRTC_PROP_DRAM_IB,
-	CRTC_PROP_IDLE_TIMEOUT,
-	CRTC_PROP_DEST_SCALER,
-
 	/* total # of properties */
 	CRTC_PROP_COUNT
 };

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Remove hand rolled msm property caching to handle DPU custom properties. This change also cleans up all its dependencies to cache and restore respective drm states.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/Makefile                  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c      | 239 +--------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h      |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c     | 123 +----
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h     |  12 -
 drivers/gpu/drm/msm/msm_drv.h                 |  16 +-
 drivers/gpu/drm/msm/msm_prop.c                | 688 --------------------------
 drivers/gpu/drm/msm/msm_prop.h                | 438 ----------------
 10 files changed, 8 insertions(+), 1529 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/msm_prop.c
 delete mode 100644 drivers/gpu/drm/msm/msm_prop.h

drivers/gpu/drm/msm/Makefile +0 -1

index d289503..5331188 100644
@@ -76,7 +76,6 @@ msm-y := \
 	dpu_io_util.o \
 	dpu_dbg_evtlog.o \
 	dpu_power_handle.o \
-	msm_prop.o \
 	msm_atomic.o \
 	msm_debugfs.o \
 	msm_drv.o \

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +0 -2

index c4820de..e4b82d5 100644
@@ -19,8 +19,6 @@
 #include <linux/clk.h>
 #include <linux/bitmap.h>
 
-#include "msm_prop.h"
-
 #include "dpu_kms.h"
 #include "dpu_trace.h"
 #include "dpu_crtc.h"

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +3 -236

index b0a3a30..43d9985 100644
@@ -579,10 +579,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
 	if (!crtc)
 		return;
 
-	if (dpu_crtc->blob_info)
-		drm_property_blob_put(dpu_crtc->blob_info);
-	msm_property_destroy(&dpu_crtc->property_info);
-
 	_dpu_crtc_deinit_events(dpu_crtc);
 
 	drm_crtc_cleanup(crtc);

@@ -1390,9 +1386,7 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
 
 	__drm_atomic_helper_crtc_destroy_state(state);
 
-	/* destroy value helper */
-	msm_property_destroy_state(&dpu_crtc->property_info, cstate,
-			&cstate->property_state);
+	kfree(cstate);
 }
 
 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)

@@ -1641,17 +1635,12 @@ static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
 
 	dpu_crtc = to_dpu_crtc(crtc);
 	old_cstate = to_dpu_crtc_state(crtc->state);
-	cstate = msm_property_alloc_state(&dpu_crtc->property_info);
+	cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
 	if (!cstate) {
 		DPU_ERROR("failed to allocate state\n");
 		return NULL;
 	}
 
-	/* duplicate value helper */
-	msm_property_duplicate_state(&dpu_crtc->property_info,
-			old_cstate, cstate,
-			&cstate->property_state, cstate->property_values);
-
 	/* duplicate base helper */
 	__drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
 

@@ -1687,17 +1676,12 @@ static void dpu_crtc_reset(struct drm_crtc *crtc)
 	}
 
 	dpu_crtc = to_dpu_crtc(crtc);
-	cstate = msm_property_alloc_state(&dpu_crtc->property_info);
+	cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
 	if (!cstate) {
 		DPU_ERROR("failed to allocate state\n");
 		return;
 	}
 
-	/* reset value helper */
-	msm_property_reset_state(&dpu_crtc->property_info, cstate,
-			&cstate->property_state,
-			cstate->property_values);
-
 	_dpu_crtc_rp_reset(&cstate->rp, &dpu_crtc->rp_lock,
 			&dpu_crtc->rp_head);
 

@@ -2194,212 +2178,6 @@ void dpu_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
 	_dpu_crtc_complete_flip(crtc, file);
 }
 
-/**
- * dpu_crtc_install_properties - install all drm properties for crtc
- * @crtc: Pointer to drm crtc structure
- */
-static void dpu_crtc_install_properties(struct drm_crtc *crtc,
-				struct dpu_mdss_cfg *catalog)
-{
-	struct dpu_crtc *dpu_crtc;
-	struct drm_device *dev;
-	struct dpu_kms_info *info;
-	struct dpu_kms *dpu_kms;
-
-	DPU_DEBUG("\n");
-
-	if (!crtc || !catalog) {
-		DPU_ERROR("invalid crtc or catalog\n");
-		return;
-	}
-
-	dpu_crtc = to_dpu_crtc(crtc);
-	dev = crtc->dev;
-	dpu_kms = _dpu_crtc_get_kms(crtc);
-
-	if (!dpu_kms) {
-		DPU_ERROR("invalid argument\n");
-		return;
-	}
-
-	info = kzalloc(sizeof(struct dpu_kms_info), GFP_KERNEL);
-	if (!info) {
-		DPU_ERROR("failed to allocate info memory\n");
-		return;
-	}
-
-	msm_property_install_blob(&dpu_crtc->property_info, "capabilities",
-		DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
-
-	dpu_kms_info_reset(info);
-
-	dpu_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
-	dpu_kms_info_add_keyint(info, "max_linewidth",
-			catalog->caps->max_mixer_width);
-	dpu_kms_info_add_keyint(info, "max_blendstages",
-			catalog->caps->max_mixer_blendstages);
-	if (catalog->caps->qseed_type == DPU_SSPP_SCALER_QSEED2)
-		dpu_kms_info_add_keystr(info, "qseed_type", "qseed2");
-	if (catalog->caps->qseed_type == DPU_SSPP_SCALER_QSEED3)
-		dpu_kms_info_add_keystr(info, "qseed_type", "qseed3");
-
-	if (dpu_is_custom_client()) {
-		if (catalog->caps->smart_dma_rev == DPU_SSPP_SMART_DMA_V1)
-			dpu_kms_info_add_keystr(info,
-					"smart_dma_rev", "smart_dma_v1");
-		if (catalog->caps->smart_dma_rev == DPU_SSPP_SMART_DMA_V2)
-			dpu_kms_info_add_keystr(info,
-					"smart_dma_rev", "smart_dma_v2");
-	}
-
-	dpu_kms_info_add_keyint(info, "has_src_split",
-				catalog->caps->has_src_split);
-	if (catalog->perf.max_bw_low)
-		dpu_kms_info_add_keyint(info, "max_bandwidth_low",
-				catalog->perf.max_bw_low * 1000LL);
-	if (catalog->perf.max_bw_high)
-		dpu_kms_info_add_keyint(info, "max_bandwidth_high",
-				catalog->perf.max_bw_high * 1000LL);
-	if (catalog->perf.min_core_ib)
-		dpu_kms_info_add_keyint(info, "min_core_ib",
-				catalog->perf.min_core_ib * 1000LL);
-	if (catalog->perf.min_llcc_ib)
-		dpu_kms_info_add_keyint(info, "min_llcc_ib",
-				catalog->perf.min_llcc_ib * 1000LL);
-	if (catalog->perf.min_dram_ib)
-		dpu_kms_info_add_keyint(info, "min_dram_ib",
-				catalog->perf.min_dram_ib * 1000LL);
-	if (dpu_kms->perf.max_core_clk_rate)
-		dpu_kms_info_add_keyint(info, "max_mdp_clk",
-				dpu_kms->perf.max_core_clk_rate);
-	dpu_kms_info_add_keystr(info, "core_ib_ff",
-			catalog->perf.core_ib_ff);
-	dpu_kms_info_add_keystr(info, "core_clk_ff",
-			catalog->perf.core_clk_ff);
-	dpu_kms_info_add_keystr(info, "comp_ratio_rt",
-			catalog->perf.comp_ratio_rt);
-	dpu_kms_info_add_keystr(info, "comp_ratio_nrt",
-			catalog->perf.comp_ratio_nrt);
-	dpu_kms_info_add_keyint(info, "dest_scale_prefill_lines",
-			catalog->perf.dest_scale_prefill_lines);
-	dpu_kms_info_add_keyint(info, "undersized_prefill_lines",
-			catalog->perf.undersized_prefill_lines);
-	dpu_kms_info_add_keyint(info, "macrotile_prefill_lines",
-			catalog->perf.macrotile_prefill_lines);
-	dpu_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
-			catalog->perf.yuv_nv12_prefill_lines);
-	dpu_kms_info_add_keyint(info, "linear_prefill_lines",
-			catalog->perf.linear_prefill_lines);
-	dpu_kms_info_add_keyint(info, "downscaling_prefill_lines",
-			catalog->perf.downscaling_prefill_lines);
-	dpu_kms_info_add_keyint(info, "xtra_prefill_lines",
-			catalog->perf.xtra_prefill_lines);
-	dpu_kms_info_add_keyint(info, "amortizable_threshold",
-			catalog->perf.amortizable_threshold);
-	dpu_kms_info_add_keyint(info, "min_prefill_lines",
-			catalog->perf.min_prefill_lines);
-
-	msm_property_set_blob(&dpu_crtc->property_info, &dpu_crtc->blob_info,
-			info->data, DPU_KMS_INFO_DATALEN(info), CRTC_PROP_INFO);
-
-	kfree(info);
-}
-
-/**
- * dpu_crtc_atomic_set_property - atomically set a crtc drm property
- * @crtc: Pointer to drm crtc structure
- * @state: Pointer to drm crtc state structure
- * @property: Pointer to targeted drm property
- * @val: Updated property value
- * @Returns: Zero on success
- */
-static int dpu_crtc_atomic_set_property(struct drm_crtc *crtc,
-		struct drm_crtc_state *state,
-		struct drm_property *property,
-		uint64_t val)
-{
-	struct dpu_crtc *dpu_crtc;
-	struct dpu_crtc_state *cstate;
-	int ret = -EINVAL;
-
-	if (!crtc || !state || !property) {
-		DPU_ERROR("invalid argument(s)\n");
-	} else {
-		dpu_crtc = to_dpu_crtc(crtc);
-		cstate = to_dpu_crtc_state(state);
-		ret = msm_property_atomic_set(&dpu_crtc->property_info,
-				&cstate->property_state, property, val);
-		if (ret)
-			DRM_ERROR("failed to set the property\n");
-
-		DPU_DEBUG("crtc%d %s[%d] <= 0x%llx ret=%d\n", crtc->base.id,
-				property->name, property->base.id, val, ret);
-	}
-
-	return ret;
-}
-
-/**
- * dpu_crtc_set_property - set a crtc drm property
- * @crtc: Pointer to drm crtc structure
- * @property: Pointer to targeted drm property
- * @val: Updated property value
- * @Returns: Zero on success
- */
-static int dpu_crtc_set_property(struct drm_crtc *crtc,
-		struct drm_property *property, uint64_t val)
-{
-	DPU_DEBUG("\n");
-
-	return dpu_crtc_atomic_set_property(crtc, crtc->state, property, val);
-}
-
-/**
- * dpu_crtc_atomic_get_property - retrieve a crtc drm property
- * @crtc: Pointer to drm crtc structure
- * @state: Pointer to drm crtc state structure
- * @property: Pointer to targeted drm property
- * @val: Pointer to variable for receiving property value
- * @Returns: Zero on success
- */
-static int dpu_crtc_atomic_get_property(struct drm_crtc *crtc,
-		const struct drm_crtc_state *state,
-		struct drm_property *property,
-		uint64_t *val)
-{
-	struct dpu_crtc *dpu_crtc;
-	struct dpu_crtc_state *cstate;
-	struct drm_encoder *encoder;
-	int i, ret = -EINVAL;
-	bool is_cmd = true;
-
-	if (!crtc || !state) {
-		DPU_ERROR("invalid argument(s)\n");
-	} else {
-		dpu_crtc = to_dpu_crtc(crtc);
-		cstate = to_dpu_crtc_state(state);
-
-		/**
-		 * set the cmd flag only when all the encoders attached
-		 * to the crtc are in cmd mode. Consider all other cases
-		 * as video mode.
-		 */
-		drm_for_each_encoder(encoder, crtc->dev) {
-			if (encoder->crtc == crtc)
-				is_cmd = dpu_encoder_check_mode(encoder,
-						MSM_DISPLAY_CAP_CMD_MODE);
-		}
-
-		i = msm_property_index(&dpu_crtc->property_info, property);
-		ret = msm_property_atomic_get(&dpu_crtc->property_info,
-				&cstate->property_state,
-				property, val);
-		if (ret)
-			DRM_ERROR("get property failed\n");
-	}
-	return ret;
-}
-
 #ifdef CONFIG_DEBUG_FS
 static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
 {

@@ -2759,9 +2537,6 @@ static void dpu_crtc_early_unregister(struct drm_crtc *crtc)
 	.set_config = drm_atomic_helper_set_config,
 	.destroy = dpu_crtc_destroy,
 	.page_flip = drm_atomic_helper_page_flip,
-	.set_property = dpu_crtc_set_property,
-	.atomic_set_property = dpu_crtc_atomic_set_property,
-	.atomic_get_property = dpu_crtc_atomic_get_property,
 	.reset = dpu_crtc_reset,
 	.atomic_duplicate_state = dpu_crtc_duplicate_state,
 	.atomic_destroy_state = dpu_crtc_destroy_state,

@@ -2924,14 +2699,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
 		return ERR_PTR(rc);
 	}
 
-	/* create CRTC properties */
-	msm_property_init(&dpu_crtc->property_info, &crtc->base, dev,
-			priv->crtc_property, dpu_crtc->property_data,
-			CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
-			sizeof(struct dpu_crtc_state));
-
-	dpu_crtc_install_properties(crtc, kms->catalog);
-
 	DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);
 	return crtc;
 }

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +0 -16

index 6628eb3..f752101 100644
@@ -22,7 +22,6 @@
 #include <linux/kthread.h>
 #include <uapi/drm/dpu_drm.h>
 #include <drm/drm_crtc.h>
-#include "msm_prop.h"
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"
 #include "dpu_hw_blk.h"

@@ -200,10 +199,6 @@ struct dpu_crtc {
 	struct drm_pending_vblank_event *event;
 	u32 vsync_count;
 
-	struct msm_property_info property_info;
-	struct msm_property_data property_data[CRTC_PROP_COUNT];
-	struct drm_property_blob *blob_info;
-
 	struct dpu_hw_stage_cfg stage_cfg;
 	struct dentry *debugfs_root;
 

@@ -324,8 +319,6 @@ struct dpu_crtc_state {
 	bool is_ppsplit;
 	struct dpu_rect lm_bounds[CRTC_DUAL_MIXERS];
 
-	struct msm_property_state property_state;
-	struct msm_property_value property_values[CRTC_PROP_COUNT];
 	uint64_t input_fence_timeout_ns;
 
 	struct dpu_core_perf_params new_perf;

@@ -336,15 +329,6 @@ struct dpu_crtc_state {
 	container_of(x, struct dpu_crtc_state, base)
 
 /**
- * dpu_crtc_get_property - query integer value of crtc property
- * @S: Pointer to crtc state
- * @X: Property index, from enum msm_mdp_crtc_property
- * Returns: Integer value of requested property
- */
-#define dpu_crtc_get_property(S, X) \
-	((S) && ((X) < CRTC_PROP_COUNT) ? ((S)->property_values[(X)].value) : 0)
-
-/**
  * dpu_crtc_get_mixer_width - get the mixer width
  * Mixer width will be same as panel width(/2 for split)
  */

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +0 -2

index d853ad9..0339dfd 100644
@@ -20,8 +20,6 @@
 #define __DPU_ENCODER_H__
 
 #include <drm/drm_crtc.h>
-
-#include "msm_prop.h"
 #include "dpu_hw_mdss.h"
 
 #define DPU_ENCODER_FRAME_EVENT_DONE			BIT(0)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +4 -119

index 28735c8..faf5903 100644
@@ -20,9 +20,8 @@
 
 #include <linux/debugfs.h>
 #include <linux/dma-buf.h>
-#include "msm_prop.h"
-#include "msm_drv.h"
 
+#include "msm_drv.h"
 #include "dpu_kms.h"
 #include "dpu_formats.h"
 #include "dpu_hw_sspp.h"

@@ -119,9 +118,6 @@ struct dpu_plane {
 
 	const struct dpu_sspp_sub_blks *pipe_sblk;
 	char pipe_name[DPU_NAME_SIZE];
-	struct msm_property_info property_info;
-	struct msm_property_data property_data[PLANE_PROP_COUNT];
-	struct drm_property_blob *blob_info;
 
 	/* debugfs related stuff */
 	struct dentry *debugfs_root;

@@ -1401,7 +1397,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
 	}
 
 	_dpu_plane_set_qos_remap(plane);
-
 	return 0;
 }
 

@@ -1486,89 +1481,6 @@ void dpu_plane_restore(struct drm_plane *plane)
 	dpu_plane_atomic_update(plane, plane->state);
 }
 
-/* helper to install properties which are common to planes and crtcs */
-static void _dpu_plane_install_properties(struct drm_plane *plane,
-	struct dpu_mdss_cfg *catalog, u32 master_plane_id)
-{
-	struct dpu_plane *pdpu = to_dpu_plane(plane);
-	int zpos_max = 255;
-	int zpos_def = 0;
-
-	if (!plane || !pdpu) {
-		DPU_ERROR("invalid plane\n");
-		return;
-	} else if (!pdpu->pipe_hw || !pdpu->pipe_sblk) {
-		DPU_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
-				pdpu->pipe_hw != 0, pdpu->pipe_sblk != 0);
-		return;
-	} else if (!catalog) {
-		DPU_ERROR("invalid catalog\n");
-		return;
-	}
-
-	pdpu->catalog = catalog;
-
-	if (dpu_is_custom_client()) {
-		if (catalog->mixer_count &&
-				catalog->mixer[0].sblk->maxblendstages) {
-			zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
-			if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
-				zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
-		}
-	} else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
-		/* reserve zpos == 0 for primary planes */
-		zpos_def = drm_plane_index(plane) + 1;
-	}
-}
-
-static int dpu_plane_atomic_set_property(struct drm_plane *plane,
-		struct drm_plane_state *state, struct drm_property *property,
-		uint64_t val)
-{
-	struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
-	struct dpu_plane_state *pstate;
-	int ret = -EINVAL;
-
-	DPU_DEBUG_PLANE(pdpu, "\n");
-
-	if (!plane) {
-		DPU_ERROR("invalid plane\n");
-	} else if (!state) {
-		DPU_ERROR_PLANE(pdpu, "invalid state\n");
-	} else {
-		pstate = to_dpu_plane_state(state);
-		ret = msm_property_atomic_set(&pdpu->property_info,
-				&pstate->property_state, property, val);
-	}
-
-	DPU_DEBUG_PLANE(pdpu, "%s[%d] <= 0x%llx ret=%d\n",
-			property->name, property->base.id, val, ret);
-
-	return ret;
-}
-
-static int dpu_plane_atomic_get_property(struct drm_plane *plane,
-		const struct drm_plane_state *state,
-		struct drm_property *property, uint64_t *val)
-{
-	struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
-	struct dpu_plane_state *pstate;
-	int ret = -EINVAL;
-
-	if (!plane) {
-		DPU_ERROR("invalid plane\n");
-	} else if (!state) {
-		DPU_ERROR("invalid state\n");
-	} else {
-		DPU_DEBUG_PLANE(pdpu, "\n");
-		pstate = to_dpu_plane_state(state);
-		ret = msm_property_atomic_get(&pdpu->property_info,
-				&pstate->property_state, property, val);
-	}
-
-	return ret;
-}
-
 static void dpu_plane_destroy(struct drm_plane *plane)
 {
 	struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;

@@ -1578,9 +1490,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
 	if (pdpu) {
 		_dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
 
-		if (pdpu->blob_info)
-			drm_property_blob_put(pdpu->blob_info);
-		msm_property_destroy(&pdpu->property_info);
 		mutex_destroy(&pdpu->lock);
 
 		drm_plane_helper_disable(plane);

@@ -1598,7 +1507,6 @@ static void dpu_plane_destroy(struct drm_plane *plane)
 static void dpu_plane_destroy_state(struct drm_plane *plane,
 		struct drm_plane_state *state)
 {
-	struct dpu_plane *pdpu;
 	struct dpu_plane_state *pstate;
 
 	if (!plane || !state) {

@@ -1607,18 +1515,13 @@ static void dpu_plane_destroy_state(struct drm_plane *plane,
 		return;
 	}
 
-	pdpu = to_dpu_plane(plane);
 	pstate = to_dpu_plane_state(state);
 
-	DPU_DEBUG_PLANE(pdpu, "\n");
-
 	/* remove ref count for frame buffers */
 	if (state->fb)
 		drm_framebuffer_put(state->fb);
 
-	/* destroy value helper */
-	msm_property_destroy_state(&pdpu->property_info, pstate,
-			&pstate->property_state);
+	kfree(pstate);
 }
 
 static struct drm_plane_state *

@@ -1638,7 +1541,7 @@ static void dpu_plane_destroy_state(struct drm_plane *plane,
 
 	old_state = to_dpu_plane_state(plane->state);
 	pdpu = to_dpu_plane(plane);
-	pstate = msm_property_alloc_state(&pdpu->property_info);
+	pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
 	if (!pstate) {
 		DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
 		return NULL;

@@ -1646,10 +1549,6 @@ static void dpu_plane_destroy_state(struct drm_plane *plane,
 
 	DPU_DEBUG_PLANE(pdpu, "\n");
 
-	/* duplicate value helper */
-	msm_property_duplicate_state(&pdpu->property_info, old_state, pstate,
-			&pstate->property_state, pstate->property_values);
-
 	pstate->pending = false;
 
 	__drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);

@@ -1676,17 +1575,12 @@ static void dpu_plane_reset(struct drm_plane *plane)
 		plane->state = 0;
 	}
 
-	pstate = msm_property_alloc_state(&pdpu->property_info);
+	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
 	if (!pstate) {
 		DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
 		return;
 	}
 
-	/* reset value helper */
-	msm_property_reset_state(&pdpu->property_info, pstate,
-			&pstate->property_state,
-			pstate->property_values);
-
 	pstate->base.plane = plane;
 
 	plane->state = &pstate->base;

@@ -1919,8 +1813,6 @@ static void dpu_plane_early_unregister(struct drm_plane *plane)
 		.update_plane = drm_atomic_helper_update_plane,
 		.disable_plane = drm_atomic_helper_disable_plane,
 		.destroy = dpu_plane_destroy,
-		.atomic_set_property = dpu_plane_atomic_set_property,
-		.atomic_get_property = dpu_plane_atomic_get_property,
 		.reset = dpu_plane_reset,
 		.atomic_duplicate_state = dpu_plane_duplicate_state,
 		.atomic_destroy_state = dpu_plane_destroy_state,

@@ -2064,13 +1956,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	/* success! finalize initialization */
 	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
 
-	msm_property_init(&pdpu->property_info, &plane->base, dev,
-			priv->plane_property, pdpu->property_data,
-			PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
-			sizeof(struct dpu_plane_state));
-
-	_dpu_plane_install_properties(plane, kms->catalog, master_plane_id);
-
 	/* save user friendly pipe name for later */
 	snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
 

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +0 -12

index a06c8b4..f6fe6dd 100644
@@ -21,7 +21,6 @@
 
 #include <drm/drm_crtc.h>
 
-#include "msm_prop.h"
 #include "dpu_kms.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_sspp.h"

@@ -44,8 +43,6 @@
  */
 struct dpu_plane_state {
 	struct drm_plane_state base;
-	struct msm_property_state property_state;
-	struct msm_property_value property_values[PLANE_PROP_COUNT];
 	struct msm_gem_address_space *aspace;
 	void *input_fence;
 	enum dpu_stage stage;

@@ -74,15 +71,6 @@ struct dpu_multirect_plane_states {
 	container_of(x, struct dpu_plane_state, base)
 
 /**
- * dpu_plane_get_property - Query integer value of plane property
- * @S: Pointer to plane state
- * @X: Property index, from enum msm_mdp_plane_property
- * Returns: Integer value of requested property
- */
-#define dpu_plane_get_property(S, X) ((S) && ((X) < PLANE_PROP_COUNT) ? \
-	((S)->property_values[(X)].value) : 0)
-
-/**
  * dpu_plane_pipe - return sspp identifier for the given plane
  * @plane:   Pointer to DRM plane object
  * Returns: sspp identifier of the given plane

drivers/gpu/drm/msm/msm_drv.h +1 -15

index 8e80b4b..edb395d 100644
@@ -77,26 +77,13 @@ struct msm_file_private {
 };
 
 enum msm_mdp_plane_property {
-	/* # of blob properties */
-	PLANE_PROP_BLOBCOUNT,
-
 	/* range properties */
-	PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
+	PLANE_PROP_ZPOS,
 
 	/* total # of properties */
 	PLANE_PROP_COUNT
 };
 
-enum msm_mdp_crtc_property {
-	CRTC_PROP_INFO,
-
-	/* # of blob properties */
-	CRTC_PROP_BLOBCOUNT,
-
-	/* total # of properties */
-	CRTC_PROP_COUNT
-};
-
 struct msm_vblank_ctrl {
 	struct kthread_work work;
 	struct list_head event_list;

@@ -364,7 +351,6 @@ struct msm_drm_private {
 
 	/* Properties */
 	struct drm_property *plane_property[PLANE_PROP_COUNT];
-	struct drm_property *crtc_property[CRTC_PROP_COUNT];
 
 	/* Color processing properties for the crtc */
 	struct drm_property **cp_property;

drivers/gpu/drm/msm/msm_prop.c deleted +0 -688

deleted file mode 100644
index 8f27cde..0000000
@@ -1,688 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "msm_prop.h"
-
-void msm_property_init(struct msm_property_info *info,
-		struct drm_mode_object *base,
-		struct drm_device *dev,
-		struct drm_property **property_array,
-		struct msm_property_data *property_data,
-		uint32_t property_count,
-		uint32_t blob_count,
-		uint32_t state_size)
-{
-	/* prevent access if any of these are NULL */
-	if (!base || !dev || !property_array || !property_data) {
-		property_count = 0;
-		blob_count = 0;
-
-		DRM_ERROR("invalid arguments, forcing zero properties\n");
-		return;
-	}
-
-	/* can't have more blob properties than total properties */
-	if (blob_count > property_count) {
-		blob_count = property_count;
-
-		DBG("Capping number of blob properties to %d", blob_count);
-	}
-
-	if (!info) {
-		DRM_ERROR("info pointer is NULL\n");
-	} else {
-		info->base = base;
-		info->dev = dev;
-		info->property_array = property_array;
-		info->property_data = property_data;
-		info->property_count = property_count;
-		info->blob_count = blob_count;
-		info->install_request = 0;
-		info->install_count = 0;
-		info->recent_idx = 0;
-		info->is_active = false;
-		info->state_size = state_size;
-		info->state_cache_size = 0;
-		mutex_init(&info->property_lock);
-
-		memset(property_data,
-				0,
-				sizeof(struct msm_property_data) *
-				property_count);
-	}
-}
-
-void msm_property_destroy(struct msm_property_info *info)
-{
-	if (!info)
-		return;
-
-	/* free state cache */
-	while (info->state_cache_size > 0)
-		kfree(info->state_cache[--(info->state_cache_size)]);
-
-	mutex_destroy(&info->property_lock);
-}
-
-int msm_property_pop_dirty(struct msm_property_info *info,
-		struct msm_property_state *property_state)
-{
-	struct list_head *item;
-	int rc = 0;
-
-	if (!info || !property_state || !property_state->values) {
-		DRM_ERROR("invalid argument(s)\n");
-		return -EINVAL;
-	}
-
-	mutex_lock(&info->property_lock);
-	if (list_empty(&property_state->dirty_list)) {
-		rc = -EAGAIN;
-	} else {
-		item = property_state->dirty_list.next;
-		list_del_init(item);
-		rc = container_of(item, struct msm_property_value, dirty_node)
-			- property_state->values;
-		DRM_DEBUG_KMS("property %d dirty\n", rc);
-	}
-	mutex_unlock(&info->property_lock);
-
-	return rc;
-}
-
-/**
- * _msm_property_set_dirty_no_lock - flag given property as being dirty
- *                                   This function doesn't mutex protect the
- *                                   dirty linked list.
- * @info: Pointer to property info container struct
- * @property_state: Pointer to property state container struct
- * @property_idx: Property index
- */
-static void _msm_property_set_dirty_no_lock(
-		struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		uint32_t property_idx)
-{
-	if (!info || !property_state || !property_state->values ||
-			property_idx >= info->property_count) {
-		DRM_ERROR("invalid argument(s), idx %u\n", property_idx);
-		return;
-	}
-
-	/* avoid re-inserting if already dirty */
-	if (!list_empty(&property_state->values[property_idx].dirty_node)) {
-		DRM_DEBUG_KMS("property %u already dirty\n", property_idx);
-		return;
-	}
-
-	list_add_tail(&property_state->values[property_idx].dirty_node,
-			&property_state->dirty_list);
-}
-
-/**
- * _msm_property_install_integer - install standard drm range property
- * @info: Pointer to property info container struct
- * @name: Property name
- * @flags: Other property type flags, e.g. DRM_MODE_PROP_IMMUTABLE
- * @min: Min property value
- * @max: Max property value
- * @init: Default Property value
- * @property_idx: Property index
- * @force_dirty: Whether or not to filter 'dirty' status on unchanged values
- */
-static void _msm_property_install_integer(struct msm_property_info *info,
-		const char *name, int flags, uint64_t min, uint64_t max,
-		uint64_t init, uint32_t property_idx, bool force_dirty)
-{
-	struct drm_property **prop;
-
-	if (!info)
-		return;
-
-	++info->install_request;
-
-	if (!name || (property_idx >= info->property_count)) {
-		DRM_ERROR("invalid argument(s), %s\n", name ? name : "null");
-	} else {
-		prop = &info->property_array[property_idx];
-		/*
-		 * Properties need to be attached to each drm object that
-		 * uses them, but only need to be created once
-		 */
-		if (*prop == 0) {
-			*prop = drm_property_create_range(info->dev,
-					flags, name, min, max);
-			if (*prop == 0)
-				DRM_ERROR("create %s property failed\n", name);
-		}
-
-		/* save init value for later */
-		info->property_data[property_idx].default_value = init;
-		info->property_data[property_idx].force_dirty = force_dirty;
-
-		/* always attach property, if created */
-		if (*prop) {
-			drm_object_attach_property(info->base, *prop, init);
-			++info->install_count;
-		}
-	}
-}
-
-void msm_property_install_range(struct msm_property_info *info,
-		const char *name, int flags, uint64_t min, uint64_t max,
-		uint64_t init, uint32_t property_idx)
-{
-	_msm_property_install_integer(info, name, flags,
-			min, max, init, property_idx, false);
-}
-
-void msm_property_install_volatile_range(struct msm_property_info *info,
-		const char *name, int flags, uint64_t min, uint64_t max,
-		uint64_t init, uint32_t property_idx)
-{
-	_msm_property_install_integer(info, name, flags,
-			min, max, init, property_idx, true);
-}
-
-void msm_property_install_rotation(struct msm_property_info *info,
-		struct drm_plane *plane, unsigned int rotation,
-		unsigned int supported_rotations, uint32_t property_idx)
-{
-	if (!info || !plane)
-		return;
-
-	++info->install_request;
-
-	if (property_idx >= info->property_count) {
-		DRM_ERROR("invalid property index %d\n", property_idx);
-		return;
-	}
-
-	if (drm_plane_create_rotation_property(plane,
-			rotation, supported_rotations)) {
-		DRM_ERROR("create rotation property failed\n");
-		return;
-	}
-
-	if (plane->rotation_property) {
-		info->property_array[property_idx] = plane->rotation_property;
-
-		/* save init value for later */
-		info->property_data[property_idx].default_value = rotation;
-		info->property_data[property_idx].force_dirty = false;
-
-		++info->install_count;
-	}
-}
-
-void msm_property_install_enum(struct msm_property_info *info,
-		const char *name, int flags, int is_bitmask,
-		const struct drm_prop_enum_list *values, int num_values,
-		uint32_t property_idx)
-{
-	struct drm_property **prop;
-
-	if (!info)
-		return;
-
-	++info->install_request;
-
-	if (!name || !values || !num_values ||
-			(property_idx >= info->property_count)) {
-		DRM_ERROR("invalid argument(s), %s\n", name ? name : "null");
-	} else {
-		prop = &info->property_array[property_idx];
-		/*
-		 * Properties need to be attached to each drm object that
-		 * uses them, but only need to be created once
-		 */
-		if (*prop == 0) {
-			/* 'bitmask' is a special type of 'enum' */
-			if (is_bitmask)
-				*prop = drm_property_create_bitmask(info->dev,
-						DRM_MODE_PROP_BITMASK | flags,
-						name, values, num_values, -1);
-			else
-				*prop = drm_property_create_enum(info->dev,
-						DRM_MODE_PROP_ENUM | flags,
-						name, values, num_values);
-			if (*prop == 0)
-				DRM_ERROR("create %s property failed\n", name);
-		}
-
-		/* save init value for later */
-		info->property_data[property_idx].default_value = 0;
-		info->property_data[property_idx].force_dirty = false;
-
-		/* select first defined value for enums */
-		if (!is_bitmask)
-			info->property_data[property_idx].default_value =
-				values->type;
-
-		/* always attach property, if created */
-		if (*prop) {
-			drm_object_attach_property(info->base, *prop,
-					info->property_data
-					[property_idx].default_value);
-			++info->install_count;
-		}
-	}
-}
-
-void msm_property_install_blob(struct msm_property_info *info,
-		const char *name, int flags, uint32_t property_idx)
-{
-	struct drm_property **prop;
-
-	if (!info)
-		return;
-
-	++info->install_request;
-
-	if (!name || (property_idx >= info->blob_count)) {
-		DRM_ERROR("invalid argument(s), %s\n", name ? name : "null");
-	} else {
-		prop = &info->property_array[property_idx];
-		/*
-		 * Properties need to be attached to each drm object that
-		 * uses them, but only need to be created once
-		 */
-		if (*prop == 0) {
-			/* use 'create' for blob property place holder */
-			*prop = drm_property_create(info->dev,
-					DRM_MODE_PROP_BLOB | flags, name, 0);
-			if (*prop == 0)
-				DRM_ERROR("create %s property failed\n", name);
-		}
-
-		/* save init value for later */
-		info->property_data[property_idx].default_value = 0;
-		info->property_data[property_idx].force_dirty = true;
-
-		/* always attach property, if created */
-		if (*prop) {
-			drm_object_attach_property(info->base, *prop, -1);
-			++info->install_count;
-		}
-	}
-}
-
-int msm_property_install_get_status(struct msm_property_info *info)
-{
-	int rc = -ENOMEM;
-
-	if (info && (info->install_request == info->install_count))
-		rc = 0;
-
-	return rc;
-}
-
-int msm_property_index(struct msm_property_info *info,
-		struct drm_property *property)
-{
-	uint32_t count;
-	int32_t idx;
-	int rc = -EINVAL;
-
-	if (!info || !property) {
-		DRM_ERROR("invalid argument(s)\n");
-	} else {
-		/*
-		 * Linear search, but start from last found index. This will
-		 * help if any single property is accessed multiple times in a
-		 * row. Ideally, we could keep a list of properties sorted in
-		 * the order of most recent access, but that may be overkill
-		 * for now.
-		 */
-		mutex_lock(&info->property_lock);
-		idx = info->recent_idx;
-		count = info->property_count;
-		while (count) {
-			--count;
-
-			/* stop searching on match */
-			if (info->property_array[idx] == property) {
-				info->recent_idx = idx;
-				rc = idx;
-				break;
-			}
-
-			/* move to next valid index */
-			if (--idx < 0)
-				idx = info->property_count - 1;
-		}
-		mutex_unlock(&info->property_lock);
-	}
-
-	return rc;
-}
-
-int msm_property_set_dirty(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		int property_idx)
-{
-	if (!info || !property_state || !property_state->values) {
-		DRM_ERROR("invalid argument(s)\n");
-		return -EINVAL;
-	}
-	mutex_lock(&info->property_lock);
-	_msm_property_set_dirty_no_lock(info, property_state, property_idx);
-	mutex_unlock(&info->property_lock);
-	return 0;
-}
-
-int msm_property_atomic_set(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		struct drm_property *property, uint64_t val)
-{
-	struct drm_property_blob *blob;
-	int property_idx, rc = -EINVAL;
-
-	property_idx = msm_property_index(info, property);
-	if (!info || !property_state ||
-			(property_idx == -EINVAL) || !property_state->values) {
-		DRM_DEBUG("invalid argument(s)\n");
-	} else {
-		/* extra handling for incoming properties */
-		mutex_lock(&info->property_lock);
-		if ((property->flags & DRM_MODE_PROP_BLOB) &&
-			(property_idx < info->blob_count)) {
-			/* DRM lookup also takes a reference */
-			blob = drm_property_lookup_blob(info->dev,
-				(uint32_t)val);
-			if (!blob) {
-				DRM_ERROR("blob not found\n");
-				val = 0;
-			} else {
-				DBG("Blob %u saved", blob->base.id);
-				val = blob->base.id;
-
-				/* save blob - need to clear previous ref */
-				if (property_state->values[property_idx].blob)
-					drm_property_blob_put(
-						property_state->values[
-						property_idx].blob);
-				property_state->values[property_idx].blob =
-					blob;
-			}
-		}
-
-		/* update value and flag as dirty */
-		if (property_state->values[property_idx].value != val ||
-				info->property_data[property_idx].force_dirty) {
-			property_state->values[property_idx].value = val;
-			_msm_property_set_dirty_no_lock(info, property_state,
-					property_idx);
-
-			DBG("%s - %lld", property->name, val);
-		}
-		mutex_unlock(&info->property_lock);
-		rc = 0;
-	}
-
-	return rc;
-}
-
-int msm_property_atomic_get(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		struct drm_property *property, uint64_t *val)
-{
-	int property_idx, rc = -EINVAL;
-
-	property_idx = msm_property_index(info, property);
-	if (!info || (property_idx == -EINVAL) ||
-			!property_state->values || !val) {
-		DRM_DEBUG("Invalid argument(s)\n");
-	} else {
-		mutex_lock(&info->property_lock);
-		*val = property_state->values[property_idx].value;
-		mutex_unlock(&info->property_lock);
-		rc = 0;
-	}
-
-	return rc;
-}
-
-void *msm_property_alloc_state(struct msm_property_info *info)
-{
-	void *state = NULL;
-
-	if (!info) {
-		DRM_ERROR("invalid property info\n");
-		return NULL;
-	}
-
-	mutex_lock(&info->property_lock);
-	if (info->state_cache_size)
-		state = info->state_cache[--(info->state_cache_size)];
-	mutex_unlock(&info->property_lock);
-
-	if (!state && info->state_size)
-		state = kmalloc(info->state_size, GFP_KERNEL);
-
-	if (!state)
-		DRM_ERROR("failed to allocate state\n");
-
-	return state;
-}
-
-/**
- * _msm_property_free_state - helper function for freeing local state objects
- * @info: Pointer to property info container struct
- * @st: Pointer to state object
- */
-static void _msm_property_free_state(struct msm_property_info *info, void *st)
-{
-	if (!info || !st)
-		return;
-
-	mutex_lock(&info->property_lock);
-	if (info->state_cache_size < MSM_PROP_STATE_CACHE_SIZE)
-		info->state_cache[(info->state_cache_size)++] = st;
-	else
-		kfree(st);
-	mutex_unlock(&info->property_lock);
-}
-
-void msm_property_reset_state(struct msm_property_info *info, void *state,
-		struct msm_property_state *property_state,
-		struct msm_property_value *property_values)
-{
-	uint32_t i;
-
-	if (!info) {
-		DRM_ERROR("invalid property info\n");
-		return;
-	}
-
-	if (state)
-		memset(state, 0, info->state_size);
-
-	if (property_state) {
-		property_state->property_count = info->property_count;
-		property_state->values = property_values;
-		INIT_LIST_HEAD(&property_state->dirty_list);
-	}
-
-	/*
-	 * Assign default property values. This helper is mostly used
-	 * to initialize newly created state objects.
-	 */
-	if (property_values)
-		for (i = 0; i < info->property_count; ++i) {
-			property_values[i].value =
-				info->property_data[i].default_value;
-			property_values[i].blob = NULL;
-			INIT_LIST_HEAD(&property_values[i].dirty_node);
-		}
-}
-
-void msm_property_duplicate_state(struct msm_property_info *info,
-		void *old_state, void *state,
-		struct msm_property_state *property_state,
-		struct msm_property_value *property_values)
-{
-	uint32_t i;
-
-	if (!info || !old_state || !state) {
-		DRM_ERROR("invalid argument(s)\n");
-		return;
-	}
-
-	memcpy(state, old_state, info->state_size);
-
-	if (!property_state)
-		return;
-
-	INIT_LIST_HEAD(&property_state->dirty_list);
-	property_state->values = property_values;
-
-	if (property_state->values)
-		/* add ref count for blobs and initialize dirty nodes */
-		for (i = 0; i < info->property_count; ++i) {
-			if (property_state->values[i].blob)
-				drm_property_blob_get(
-						property_state->values[i].blob);
-			INIT_LIST_HEAD(&property_state->values[i].dirty_node);
-		}
-}
-
-void msm_property_destroy_state(struct msm_property_info *info, void *state,
-		struct msm_property_state *property_state)
-{
-	uint32_t i;
-
-	if (!info || !state) {
-		DRM_ERROR("invalid argument(s)\n");
-		return;
-	}
-	if (property_state && property_state->values) {
-		/* remove ref count for blobs */
-		for (i = 0; i < info->property_count; ++i)
-			if (property_state->values[i].blob) {
-				drm_property_blob_put(
-						property_state->values[i].blob);
-				property_state->values[i].blob = NULL;
-			}
-	}
-
-	_msm_property_free_state(info, state);
-}
-
-void *msm_property_get_blob(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		size_t *byte_len,
-		uint32_t property_idx)
-{
-	struct drm_property_blob *blob;
-	size_t len = 0;
-	void *rc = 0;
-
-	if (!info || !property_state || !property_state->values ||
-			(property_idx >= info->blob_count)) {
-		DRM_ERROR("invalid argument(s)\n");
-	} else {
-		blob = property_state->values[property_idx].blob;
-		if (blob) {
-			len = blob->length;
-			rc = &blob->data;
-		}
-	}
-
-	if (byte_len)
-		*byte_len = len;
-
-	return rc;
-}
-
-int msm_property_set_blob(struct msm_property_info *info,
-		struct drm_property_blob **blob_reference,
-		void *blob_data,
-		size_t byte_len,
-		uint32_t property_idx)
-{
-	struct drm_property_blob *blob = NULL;
-	int rc = -EINVAL;
-
-	if (!info || !blob_reference || (property_idx >= info->blob_count)) {
-		DRM_ERROR("invalid argument(s)\n");
-	} else {
-		/* create blob */
-		if (blob_data && byte_len) {
-			blob = drm_property_create_blob(info->dev,
-					byte_len,
-					blob_data);
-			if (IS_ERR_OR_NULL(blob)) {
-				rc = PTR_ERR(blob);
-				DRM_ERROR("failed to create blob, %d\n", rc);
-				goto exit;
-			}
-		}
-
-		/* update drm object */
-		rc = drm_object_property_set_value(info->base,
-				info->property_array[property_idx],
-				blob ? blob->base.id : 0);
-		if (rc) {
-			DRM_ERROR("failed to set blob to property\n");
-			if (blob)
-				drm_property_blob_put(blob);
-			goto exit;
-		}
-
-		/* update local reference */
-		if (*blob_reference)
-			drm_property_blob_put(*blob_reference);
-		*blob_reference = blob;
-	}
-
-exit:
-	return rc;
-}
-
-int msm_property_set_property(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		uint32_t property_idx,
-		uint64_t val)
-{
-	int rc = -EINVAL;
-
-	if (!info || (property_idx >= info->property_count) ||
-			property_idx < info->blob_count ||
-			!property_state || !property_state->values) {
-		DRM_ERROR("invalid argument(s)\n");
-	} else {
-		struct drm_property *drm_prop;
-
-		mutex_lock(&info->property_lock);
-
-		/* update cached value */
-		property_state->values[property_idx].value = val;
-
-		/* update the new default value for immutables */
-		drm_prop = info->property_array[property_idx];
-		if (drm_prop->flags & DRM_MODE_PROP_IMMUTABLE)
-			info->property_data[property_idx].default_value = val;
-
-		mutex_unlock(&info->property_lock);
-
-		/* update drm object */
-		rc = drm_object_property_set_value(info->base, drm_prop, val);
-		if (rc)
-			DRM_ERROR("failed set property value, idx %d rc %d\n",
-					property_idx, rc);
-
-	}
-
-	return rc;
-}
-

drivers/gpu/drm/msm/msm_prop.h deleted +0 -438

deleted file mode 100644
index 6785955..0000000
@@ -1,438 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _MSM_PROP_H_
-#define _MSM_PROP_H_
-
-#include <linux/list.h>
-#include "msm_drv.h"
-
-#define MSM_PROP_STATE_CACHE_SIZE	2
-
-/**
- * struct msm_property_data - opaque structure for tracking per
- *                            drm-object per property stuff
- * @default_value: Default property value for this drm object
- * @force_dirty: Always dirty property on incoming sets, rather than checking
- *               for modified values
- */
-struct msm_property_data {
-	uint64_t default_value;
-	bool force_dirty;
-};
-
-/**
- * struct msm_property_value - opaque structure for tracking per
- *                             drm-object per property stuff
- * @value: Current property value for this drm object
- * @blob: Pointer to associated blob data, if available
- * @dirty_node: Linked list node to track if property is dirty or not
- */
-struct msm_property_value {
-	uint64_t value;
-	struct drm_property_blob *blob;
-	struct list_head dirty_node;
-};
-
-/**
- * struct msm_property_info: Structure for property/state helper functions
- * @base: Pointer to base drm object (plane/crtc/etc.)
- * @dev: Pointer to drm device object
- * @property_array: Pointer to array for storing created property objects
- * @property_data: Pointer to array for storing private property data
- * @property_count: Total number of properties
- * @blob_count: Total number of blob properties, should be <= count
- * @install_request: Total number of property 'install' requests
- * @install_count: Total number of successful 'install' requests
- * @recent_idx: Index of property most recently accessed by set/get
- * @is_active: Whether or not drm component properties are 'active'
- * @state_cache: Cache of local states, to prevent alloc/free thrashing
- * @state_size: Size of local state structures
- * @state_cache_size: Number of state structures currently stored in state_cache
- * @property_lock: Mutex to protect local variables
- */
-struct msm_property_info {
-	struct drm_mode_object *base;
-	struct drm_device *dev;
-
-	struct drm_property **property_array;
-	struct msm_property_data *property_data;
-	uint32_t property_count;
-	uint32_t blob_count;
-	uint32_t install_request;
-	uint32_t install_count;
-
-	int32_t recent_idx;
-
-	bool is_active;
-
-	void *state_cache[MSM_PROP_STATE_CACHE_SIZE];
-	uint32_t state_size;
-	int32_t state_cache_size;
-	struct mutex property_lock;
-};
-
-/**
- * struct msm_property_state - Structure for local property state information
- * @property_count: Total number of properties
- * @values: Pointer to array of msm_property_value objects
- * @dirty_list: List of all properties that have been 'atomic_set' but not
- *              yet cleared with 'msm_property_pop_dirty'
- */
-struct msm_property_state {
-	uint32_t property_count;
-	struct msm_property_value *values;
-	struct list_head dirty_list;
-};
-
-/**
- * msm_property_index_to_drm_property - get drm property struct from prop index
- * @info: Pointer to property info container struct
- * @property_idx: Property index
- * Returns: drm_property pointer associated with property index
- */
-static inline
-struct drm_property *msm_property_index_to_drm_property(
-		struct msm_property_info *info, uint32_t property_idx)
-{
-	if (!info || property_idx >= info->property_count)
-		return NULL;
-
-	return info->property_array[property_idx];
-}
-
-/**
- * msm_property_get_default - query default value of a property
- * @info: Pointer to property info container struct
- * @property_idx: Property index
- * Returns: Default value for specified property
- */
-static inline
-uint64_t msm_property_get_default(struct msm_property_info *info,
-		uint32_t property_idx)
-{
-	uint64_t rc = 0;
-
-	if (!info)
-		return 0;
-
-	mutex_lock(&info->property_lock);
-	if (property_idx < info->property_count)
-		rc = info->property_data[property_idx].default_value;
-	mutex_unlock(&info->property_lock);
-
-	return rc;
-}
-
-/**
- * msm_property_set_is_active - set overall 'active' status for all properties
- * @info: Pointer to property info container struct
- * @is_active: New 'is active' status
- */
-static inline
-void msm_property_set_is_active(struct msm_property_info *info, bool is_active)
-{
-	if (info) {
-		mutex_lock(&info->property_lock);
-		info->is_active = is_active;
-		mutex_unlock(&info->property_lock);
-	}
-}
-
-/**
- * msm_property_get_is_active - query property 'is active' status
- * @info: Pointer to property info container struct
- * Returns: Current 'is active's status
- */
-static inline
-bool msm_property_get_is_active(struct msm_property_info *info)
-{
-	bool rc = false;
-
-	if (info) {
-		mutex_lock(&info->property_lock);
-		rc = info->is_active;
-		mutex_unlock(&info->property_lock);
-	}
-
-	return rc;
-}
-
-/**
- * msm_property_pop_dirty - determine next dirty property and clear
- *                          its dirty flag
- * @info: Pointer to property info container struct
- * @property_state: Pointer to property state container struct
- * Returns: Valid msm property index on success,
- *          -EAGAIN if no dirty properties are available
- *          Property indicies returned from this function are similar
- *          to those returned by the msm_property_index function.
- */
-int msm_property_pop_dirty(struct msm_property_info *info,
-		struct msm_property_state *property_state);
-
-/**
- * msm_property_init - initialize property info structure
- * @info: Pointer to property info container struct
- * @base: Pointer to base drm object (plane/crtc/etc.)
- * @dev: Pointer to drm device object
- * @property_array: Pointer to array for storing created property objects
- * @property_data: Pointer to array for storing private property data
- * @property_count: Total number of properties
- * @blob_count: Total number of blob properties, should be <= count
- * @state_size: Size of local state object
- */
-void msm_property_init(struct msm_property_info *info,
-		struct drm_mode_object *base,
-		struct drm_device *dev,
-		struct drm_property **property_array,
-		struct msm_property_data *property_data,
-		uint32_t property_count,
-		uint32_t blob_count,
-		uint32_t state_size);
-
-/**
- * msm_property_destroy - destroy helper info structure
- *
- * @info: Pointer to property info container struct
- */
-void msm_property_destroy(struct msm_property_info *info);
-
-/**
- * msm_property_install_range - install standard drm range property
- * @info: Pointer to property info container struct
- * @name: Property name
- * @flags: Other property type flags, e.g. DRM_MODE_PROP_IMMUTABLE
- * @min: Min property value
- * @max: Max property value
- * @init: Default Property value
- * @property_idx: Property index
- */
-void msm_property_install_range(struct msm_property_info *info,
-		const char *name,
-		int flags,
-		uint64_t min,
-		uint64_t max,
-		uint64_t init,
-		uint32_t property_idx);
-
-/**
- * msm_property_install_volatile_range - install drm range property
- *	This function is similar to msm_property_install_range, but assumes
- *	that the property is meant for holding user pointers or descriptors
- *	that may reference volatile data without having an updated value.
- * @info: Pointer to property info container struct
- * @name: Property name
- * @flags: Other property type flags, e.g. DRM_MODE_PROP_IMMUTABLE
- * @min: Min property value
- * @max: Max property value
- * @init: Default Property value
- * @property_idx: Property index
- */
-void msm_property_install_volatile_range(struct msm_property_info *info,
-		const char *name,
-		int flags,
-		uint64_t min,
-		uint64_t max,
-		uint64_t init,
-		uint32_t property_idx);
-
-/**
- * msm_property_install_rotation - install standard drm rotation property
- * @info: Pointer to property info container struct
- * @plane: Pointer to drm_plane which this property is installed on
- * @rotation: The default value for this new property
- * @supported_rotations: Bitmask of supported rotation values (see
- *                       drm_plane_create_rotation_property for more details)
- * @property_idx: Property index
- */
-void msm_property_install_rotation(struct msm_property_info *info,
-		struct drm_plane *plane,
-		unsigned int rotation,
-		unsigned int supported_rotations,
-		uint32_t property_idx);
-
-/**
- * msm_property_install_enum - install standard drm enum/bitmask property
- * @info: Pointer to property info container struct
- * @name: Property name
- * @flags: Other property type flags, e.g. DRM_MODE_PROP_IMMUTABLE
- * @is_bitmask: Set to non-zero to create a bitmask property, rather than an
- *              enumeration one
- * @values: Array of allowable enumeration/bitmask values
- * @num_values: Size of values array
- * @property_idx: Property index
- */
-void msm_property_install_enum(struct msm_property_info *info,
-		const char *name,
-		int flags,
-		int is_bitmask,
-		const struct drm_prop_enum_list *values,
-		int num_values,
-		uint32_t property_idx);
-
-/**
- * msm_property_install_blob - install standard drm blob property
- * @info: Pointer to property info container struct
- * @name: Property name
- * @flags: Extra flags for property creation
- * @property_idx: Property index
- */
-void msm_property_install_blob(struct msm_property_info *info,
-		const char *name,
-		int flags,
-		uint32_t property_idx);
-
-/**
- * msm_property_install_get_status - query overal status of property additions
- * @info: Pointer to property info container struct
- * Returns: Zero if previous property install calls were all successful
- */
-int msm_property_install_get_status(struct msm_property_info *info);
-
-/**
- * msm_property_index - determine property index from drm_property ptr
- * @info: Pointer to property info container struct
- * @property: Incoming property pointer
- * Returns: Valid property index, or -EINVAL on error
- */
-int msm_property_index(struct msm_property_info *info,
-		struct drm_property *property);
-
-/**
- * msm_property_set_dirty - forcibly flag a property as dirty
- * @info: Pointer to property info container struct
- * @property_state: Pointer to property state container struct
- * @property_idx: Property index
- * Returns: Zero on success
- */
-int msm_property_set_dirty(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		int property_idx);
-
-/**
- * msm_property_atomic_set - helper function for atomic property set callback
- * @info: Pointer to property info container struct
- * @property_state: Pointer to local state structure
- * @property: Incoming property pointer
- * @val: Incoming property value
- * Returns: Zero on success
- */
-int msm_property_atomic_set(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		struct drm_property *property,
-		uint64_t val);
-
-/**
- * msm_property_atomic_get - helper function for atomic property get callback
- * @info: Pointer to property info container struct
- * @property_state: Pointer to local state structure
- * @property: Incoming property pointer
- * @val: Pointer to variable for receiving property value
- * Returns: Zero on success
- */
-int msm_property_atomic_get(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		struct drm_property *property,
-		uint64_t *val);
-
-/**
- * msm_property_alloc_state - helper function for allocating local state objects
- * @info: Pointer to property info container struct
- */
-void *msm_property_alloc_state(struct msm_property_info *info);
-
-/**
- * msm_property_reset_state - helper function for state reset callback
- * @info: Pointer to property info container struct
- * @state: Pointer to local state structure
- * @property_state: Pointer to property state container struct
- * @property_values: Pointer to property values cache array
- */
-void msm_property_reset_state(struct msm_property_info *info, void *state,
-		struct msm_property_state *property_state,
-		struct msm_property_value *property_values);
-
-/**
- * msm_property_duplicate_state - helper function for duplicate state cb
- * @info: Pointer to property info container struct
- * @old_state: Pointer to original state structure
- * @state: Pointer to newly created state structure
- * @property_state: Pointer to destination property state container struct
- * @property_values: Pointer to property values cache array
- */
-void msm_property_duplicate_state(struct msm_property_info *info,
-		void *old_state,
-		void *state,
-		struct msm_property_state *property_state,
-		struct msm_property_value *property_values);
-
-/**
- * msm_property_destroy_state - helper function for destroy state cb
- * @info: Pointer to property info container struct
- * @state: Pointer to local state structure
- * @property_state: Pointer to property state container struct
- */
-void msm_property_destroy_state(struct msm_property_info *info,
-		void *state,
-		struct msm_property_state *property_state);
-
-/**
- * msm_property_get_blob - obtain cached data pointer for drm blob property
- * @info: Pointer to property info container struct
- * @property_state: Pointer to property state container struct
- * @byte_len: Optional pointer to variable for accepting blob size
- * @property_idx: Property index
- * Returns: Pointer to blob data
- */
-void *msm_property_get_blob(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		size_t *byte_len,
-		uint32_t property_idx);
-
-/**
- * msm_property_set_blob - update blob property on a drm object
- * This function updates the blob property value of the given drm object. Its
- * intended use is to update blob properties that have been created with the
- * DRM_MODE_PROP_IMMUTABLE flag set.
- * @info: Pointer to property info container struct
- * @blob_reference: Reference to a pointer that holds the created data blob
- * @blob_data: Pointer to blob data
- * @byte_len: Length of blob data, in bytes
- * @property_idx: Property index
- * Returns: Zero on success
- */
-int msm_property_set_blob(struct msm_property_info *info,
-		struct drm_property_blob **blob_reference,
-		void *blob_data,
-		size_t byte_len,
-		uint32_t property_idx);
-
-/**
- * msm_property_set_property - update property on a drm object
- * This function updates the property value of the given drm object. Its
- * intended use is to update properties that have been created with the
- * DRM_MODE_PROP_IMMUTABLE flag set.
- * Note: This function cannot be called on a blob.
- * @info: Pointer to property info container struct
- * @property_state: Pointer to property state container struct
- * @property_idx: Property index
- * @val: value of the property to set
- * Returns: Zero on success
- */
-int msm_property_set_property(struct msm_property_info *info,
-		struct msm_property_state *property_state,
-		uint32_t property_idx,
-		uint64_t val);
-
-#endif /* _MSM_PROP_H_ */
-

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