net: phy: broadcom: Enable 125 MHz clock on LED4 pin for BCM54612E by default.
Subsystems (4)
PATCH 1/1 net: phy: broadcom: Enable 125 MHz clock on LED4 pin for BCM54612E by default.
BCM54612E have 4 multi-functional LED pins that can be configured through register setting; the LED4 pin can be configured to a 125MHz reference clock output by setting the spare register. Since the dedicated CLK125 reference clock pin is not brought out on the 48-Pin MLP, the LED4 pin is the only pin to provide such function in this package, and therefore it is beneficial to just enable the reference clock by default.
--- drivers/net/phy/broadcom.c | 16 ++++++++++++++-- include/linux/brcmphy.h | 4 ++++ 2 files changed, 18 insertions(+), 2 deletions(-)
drivers/net/phy/broadcom.c +14 -2
@@ -54,6 +54,8 @@ static int bcm54210e_config_init(struct phy_device *phydev)static int bcm54612e_config_init (struct phy_device *phydev) { +int reg; +/* Clear TX internal delay unless requested. */ if ((phydev->interface !=PHY_INTERFACE_MODE_RGMII_ID ) && (phydev->interface !=PHY_INTERFACE_MODE_RGMII_TXID )) {
@@ -65,8 +67,6 @@ static int bcm54612e_config_init(struct phy_device *phydev)/* Clear RX internal delay unless requested. */ if ((phydev->interface !=PHY_INTERFACE_MODE_RGMII_ID ) && (phydev->interface !=PHY_INTERFACE_MODE_RGMII_RXID )) { -u16 reg; - reg =bcm54xx_auxctl_read (phydev,MII_BCM54XX_AUXCTL_SHDWSEL_MISC );/* Disable RXD to RXC delay (default set) */
@@ -77,6 +77,18 @@ static int bcm54612e_config_init(struct phy_device *phydev) MII_BCM54XX_AUXCTL_MISC_WREN | reg); } +/* Enable CLK125 MUX on LED4 if ref clock is enabled. */ +if (!(phydev->dev_flags &PHY_BRCM_RX_REFCLK_UNUSED )) { +int err; + + reg =bcm_phy_read_exp (phydev,BCM54612E_EXP_SPARE0 ); + err =bcm_phy_write_exp (phydev,BCM54612E_EXP_SPARE0 , +BCM54612E_LED4_CLK125OUT_EN | reg); + +if (err <0 ) +return err; + } +return 0 ; }
include/linux/brcmphy.h +4 -0
@@ -85,6 +85,7 @@#define MII_BCM54XX_EXP_SEL 0x17/* Expansion register select */ #define MII_BCM54XX_EXP_SEL_SSD 0x0e00/* Secondary SerDes select */ #define MII_BCM54XX_EXP_SEL_ER 0x0f00/* Expansion register select */ +#define MII_BCM54XX_EXP_SEL_ETC 0x0d00/* Expansion register spare + 2k mem */ #define MII_BCM54XX_AUX_CTL 0x18/* Auxiliary control register */ #define MII_BCM54XX_ISR 0x1a/* BCM54xx interrupt status register */
@@ -219,6 +220,9 @@#define BCM54810_SHD_CLK_CTL 0x3#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9) +/* BCM54612E Registers */ +#define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34) +#define BCM54612E_LED4_CLK125OUT_EN (1 << 1)/*****************************************************************************/ /* Fast Ethernet Transceiver definitions. */
Signature · 1 line
2.17.1.1185.g55be947832-goog
Le 06/04/18 à 13:17, Kun Yi a écrit :
Quoted 6 lines
BCM54612E have 4 multi-functional LED pins that can be configured through register setting; the LED4 pin can be configured to a 125MHz reference clock output by setting the spare register. Since the dedicated CLK125 reference clock pin is not brought out on the 48-Pin MLP, the LED4 pin is the only pin to provide such function in this package, and therefore it is beneficial to just enable the reference clock by default.
Checked the data sheet and this appears to be absolutely correct:
Signature · 1 line
Florian
From: Kun Yi <[email protected]>
Date: Mon, 4 Jun 2018 13:17:04 -0700
Quoted 8 lines
BCM54612E have 4 multi-functional LED pins that can be configured through register setting; the LED4 pin can be configured to a 125MHz reference clock output by setting the spare register. Since the dedicated CLK125 reference clock pin is not brought out on the 48-Pin MLP, the LED4 pin is the only pin to provide such function in this package, and therefore it is beneficial to just enable the reference clock by default.
Signed-off-by Kun Yi <[email protected]>
Applied, thank you.