arch: arm: mach-rockchip: rk3288: Enable regulators in board_init

---
 arch/arm/mach-rockchip/rk3288-board.c | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/mach-rockchip/rk3288-board.c +6 -0

index 8c128d4..759bfbe 100644
@@ -159,6 +159,12 @@ err:
 #else
 	int ret;
 
+	ret = regulators_enable_boot_on(false);
+	if (ret) {
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+		return ret;
+	}
+
 	/* We do some SoC one time setting here */
 	if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
 		ret = veyron_init();

Signature · 1 line

2.7.4

Janine Hagemann

author

2018-06-14 09:48 UTC #1 lore raw

PATCH 2/12 config: phycore-rk3288_defconfig: add PHY_TI

add PHY_TI to support dp83867

---
 configs/phycore-rk3288_defconfig | 1 +
 1 file changed, 1 insertion(+)

configs/phycore-rk3288_defconfig +1 -0

index 50b0c98..7d0535f 100644
@@ -53,6 +53,7 @@ CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_TI=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y

Signature · 1 line

2.7.4

Janine Hagemann

author

2018-06-14 09:48 UTC #2 lore raw

PATCH 3/12 net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii

We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii() to enable the RX delay.
The MASK was used in a wrong way.

---
 drivers/net/gmac_rockchip.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/net/gmac_rockchip.c +1 -1

index 30a24d1..0f91731 100644
@@ -350,7 +350,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
 		     RK3328_TXCLK_DLY_ENA_GMAC_MASK,
 		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
-		     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3328_RXCLK_DLY_ENA_GMAC_ENABLE |
 		     RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
 
 	rk_clrsetreg(&grf->mac_con[0],

Signature · 1 line

2.7.4

Joe Hershberger

2018-06-14 17:39 UTC #3 lore raw

PATCH 3/12 net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii

Quoted 6 lines · Janine Hagemann

We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii() to enable the RX delay.
The MASK was used in a wrong way.
Signed-off-by Janine Hagemann <[email protected]>

Dr. Philipp Tomsich

2018-06-14 18:12 UTC #4 lore raw

PATCH 3/12 net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii

Quoted 12 lines · Joe Hershberger

Quoted 6 lines · Janine Hagemann
We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii() to enable the RX delay.
The MASK was used in a wrong way.
Signed-off-by Janine Hagemann <[email protected]>
Acked-by Joe Hershberger <[email protected]>

Reviewed-by Philipp Tomsich <[email protected]>

Joe Hershberger

2018-06-14 18:26 UTC #5 lore raw

PATCH 3/12 net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii

Quoted 9 lines · Dr. Philipp Tomsich

Quoted 9 lines · Joe Hershberger
Quoted 5 lines · Janine Hagemann
We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii() to enable the RX delay.
The MASK was used in a wrong way.

Quoted 5 lines

Quoted 3 lines
Quoted 1 line
Signed-off-by Janine Hagemann <[email protected]>
Acked-by Joe Hershberger <[email protected]>
Reviewed-by Philipp Tomsich <[email protected]>

I assume I should take this series? Or would you prefer to?

-Joe

Dr. Philipp Tomsich

2018-07-13 10:42 UTC #6 lore raw

PATCH 3/12 net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii

Joe,

Quoted 13 lines · Joe Hershberger

Quoted 9 lines · Dr. Philipp Tomsich
Quoted 9 lines · Joe Hershberger
Quoted 5 lines · Janine Hagemann
We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii() to enable the RX delay.
The MASK was used in a wrong way.

Quoted 7 lines

Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Janine Hagemann <[email protected]>
Acked-by Joe Hershberger <[email protected]>
Reviewed-by Philipp Tomsich <[email protected]>
I assume I should take this series? Or would you prefer to?

Iâ€™ll take these as part of the larger series.

Thanks,
Philipp.

Janine Hagemann

author

2018-06-14 09:48 UTC #7 lore raw

PATCH 4/12 Net: phy: ti: Fix fifo_depth register write

The register was not read before the writing, so the previous value was overwritten.

---
 drivers/net/phy/ti.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

drivers/net/phy/ti.c +9 -2

index 8f3ed8a..d7ae881 100644
@@ -51,6 +51,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* PHY CTRL bits */
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
+#define DP83867_PHYCR_FIFO_DEPTH_MASK	(3 << 14)
+#define DP83867_PHYCR_RESERVED_MASK	BIT(11)
 #define DP83867_MDI_CROSSOVER		5
 #define DP83867_MDI_CROSSOVER_AUTO	2
 #define DP83867_MDI_CROSSOVER_MDIX	2

@@ -233,9 +235,14 @@ static int dp83867_config(struct phy_device *phydev)
 		  val | DP83867_SW_RESTART);
 
 	if (phy_interface_is_rgmii(phydev)) {
+		val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
+		if (val < 0)
+			return val;
+		val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
+		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 		ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
-			(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
-			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+				val);
+
 		if (ret)
 			goto err_out;
 	} else if (phy_interface_is_sgmii(phydev)) {

Signature · 1 line

2.7.4

Janine Hagemann

author

2018-06-14 09:48 UTC #8 lore raw

PATCH 5/12 net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver

This patch adds support for enabling or disabling the lane swapping (called "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY device.

One use case is when bootstrap configuration enables this feature (because of e.g. LED_0 wrong wiring) so then one needs to disable it in software (at u-boot/Linux).

Based on commit 'fc6d39c39581f3c12c95f166ce95ef8beb2047e8' of mainline linux kernel

---
 drivers/net/phy/ti.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

drivers/net/phy/ti.c +40 -0

index d7ae881..086ea4a 100644
@@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_CTRL		0x1f
 
 /* Extended Registers */
+#define DP83867_CFG4		0x0031
 #define DP83867_RGMIICTL	0x0032
 #define DP83867_RGMIIDCTL	0x0086
 #define DP83867_IO_MUX_CFG	0x0170

@@ -92,11 +93,21 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f
 
+/* CFG4 bits */
+#define DP83867_CFG4_PORT_MIRROR_EN		BIT(0)
+
+enum {
+	DP83867_PORT_MIRRORING_KEEP,
+	DP83867_PORT_MIRRORING_EN,
+	DP83867_PORT_MIRRORING_DIS,
+};
+
 struct dp83867_private {
 	int rx_id_delay;
 	int tx_id_delay;
 	int fifo_depth;
 	int io_impedance;
+	int port_mirroring;
 };
 
 /**

@@ -165,6 +176,26 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
 	phy_write(phydev, addr, MII_MMD_DATA, data);
 }
 
+static int dp83867_config_port_mirroring(struct phy_device *phydev)
+{
+	struct dp83867_private *dp83867 =
+		(struct dp83867_private *)phydev->priv;
+	u16 val;
+
+	val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+		 phydev->addr);
+
+	if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
+		val |= DP83867_CFG4_PORT_MIRROR_EN;
+	else
+		val &= ~DP83867_CFG4_PORT_MIRROR_EN;
+
+	phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+		phydev->addr, val);
+
+	return 0;
+}
+
 #if defined(CONFIG_DM_ETH)
 /**
  * dp83867_data_init - Convenience function for setting PHY specific data

@@ -191,6 +222,12 @@ static int dp83867_of_init(struct phy_device *phydev)
 	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 				 "ti,tx-internal-delay", -1);
 
+	if (fdtdec_get_bool(fdt, node, "enet-phy-lane-swap"))
+		dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
+
+	if (fdtdec_get_bool(fdt, node, "enet-phy-lane-no-swap"))
+		dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
+
 	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 				 "ti,fifo-depth", -1);

@@ -307,6 +344,9 @@ static int dp83867_config(struct phy_device *phydev)
 		}
 	}
 
+	if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
+		dp83867_config_port_mirroring(phydev);
+
 	genphy_config_aneg(phydev);
 	return 0;

Signature · 1 line

2.7.4

Joe Hershberger

2018-06-14 17:47 UTC #9 lore raw

PATCH 5/12 net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver

Quoted 10 lines · Janine Hagemann

This patch adds support for enabling or disabling the lane swapping (called "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY device.
One use case is when bootstrap configuration enables this feature (because of e.g. LED_0 wrong wiring) so then one needs to disable it in software (at u-boot/Linux).
Based on commit 'fc6d39c39581f3c12c95f166ce95ef8beb2047e8' of mainline linux kernel

I think you are always supposed to include the summary text when referencing a commit as well. Does checkpatch not complain about this?

Quoted 2 lines

Signed-off-by Janine Hagemann <[email protected]>

Otherwise,

Quoted 95 lines

---
 drivers/net/phy/ti.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

drivers/net/phy/ti.c +40 -1

index d7ae881..086ea4a 100644
@@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_CTRL           0x1f
 
 /* Extended Registers */
+#define DP83867_CFG4           0x0031
 #define DP83867_RGMIICTL       0x0032
 #define DP83867_RGMIIDCTL      0x0086
 #define DP83867_IO_MUX_CFG     0x0170

@@ -92,11 +93,21 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX    0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN    0x1f
 
+/* CFG4 bits */
+#define DP83867_CFG4_PORT_MIRROR_EN            BIT(0)
+
+enum {
+       DP83867_PORT_MIRRORING_KEEP,
+       DP83867_PORT_MIRRORING_EN,
+       DP83867_PORT_MIRRORING_DIS,
+};
+
 struct dp83867_private {
        int rx_id_delay;
        int tx_id_delay;
        int fifo_depth;
        int io_impedance;
+       int port_mirroring;
 };
 
 /**

@@ -165,6 +176,26 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
        phy_write(phydev, addr, MII_MMD_DATA, data);
 }
 
+static int dp83867_config_port_mirroring(struct phy_device *phydev)
+{
+       struct dp83867_private *dp83867 =
+               (struct dp83867_private *)phydev->priv;
+       u16 val;
+
+       val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+                phydev->addr);
+
+       if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
+               val |= DP83867_CFG4_PORT_MIRROR_EN;
+       else
+               val &= ~DP83867_CFG4_PORT_MIRROR_EN;
+
+       phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+               phydev->addr, val);
+
+       return 0;
+}
+
 #if defined(CONFIG_DM_ETH)
 /**
  * dp83867_data_init - Convenience function for setting PHY specific data

@@ -191,6 +222,12 @@ static int dp83867_of_init(struct phy_device *phydev)
        dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
                                 "ti,tx-internal-delay", -1);
 
+       if (fdtdec_get_bool(fdt, node, "enet-phy-lane-swap"))
+               dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
+
+       if (fdtdec_get_bool(fdt, node, "enet-phy-lane-no-swap"))
+               dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
+
        dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
                                 "ti,fifo-depth", -1);

@@ -307,6 +344,9 @@ static int dp83867_config(struct phy_device *phydev)
                }
        }
 
+       if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
+               dp83867_config_port_mirroring(phydev);
+
        genphy_config_aneg(phydev);
        return 0;
 
--

2.7.4

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot

Lukasz Majewski

2018-06-15 07:24 UTC #10 lore raw

PATCH 5/12 net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver

Hi Janine,

Quoted 4 lines

This patch adds support for enabling or disabling the lane swapping (called "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY device.

Quoted 8 lines

One use case is when bootstrap configuration enables this feature (because of e.g. LED_0 wrong wiring) so then one needs to disable it in software (at u-boot/Linux).
Based on commit 'fc6d39c39581f3c12c95f166ce95ef8beb2047e8' of mainline linux kernel
Signed-off-by Janine Hagemann <[email protected]>

Thanks for bringing it into u-boot.

Acked-by Lukasz Majewski <[email protected]>

Quoted 80 lines

---
 drivers/net/phy/ti.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

drivers/net/phy/ti.c +31 -0

index d7ae881..086ea4a 100644
@@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_CTRL		0x1f
 
 /* Extended Registers */
+#define DP83867_CFG4		0x0031
 #define DP83867_RGMIICTL	0x0032
 #define DP83867_RGMIIDCTL	0x0086
 #define DP83867_IO_MUX_CFG	0x0170

@@ -92,11 +93,21 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f
 
+/* CFG4 bits */
+#define DP83867_CFG4_PORT_MIRROR_EN		BIT(0)
+
+enum {
+	DP83867_PORT_MIRRORING_KEEP,
+	DP83867_PORT_MIRRORING_EN,
+	DP83867_PORT_MIRRORING_DIS,
+};
+
 struct dp83867_private {
 	int rx_id_delay;
 	int tx_id_delay;
 	int fifo_depth;
 	int io_impedance;
+	int port_mirroring;
 };
 
 /**

@@ -165,6 +176,26 @@ void phy_write_mmd_indirect(struct phy_device
 *phydev, int prtad, phy_write(phydev, addr, MII_MMD_DATA, data);
 }
 
+static int dp83867_config_port_mirroring(struct phy_device *phydev)
+{
+	struct dp83867_private *dp83867 =
+		(struct dp83867_private *)phydev->priv;
+	u16 val;
+
+	val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
 DP83867_DEVADDR,
+		 phydev->addr);
+
+	if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
+		val |= DP83867_CFG4_PORT_MIRROR_EN;
+	else
+		val &= ~DP83867_CFG4_PORT_MIRROR_EN;
+
+	phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+		phydev->addr, val);
+
+	return 0;
+}
+
 #if defined(CONFIG_DM_ETH)
 /**

* dp83867_data_init - Convenience function for setting PHY specific
data @@ -191,6 +222,12 @@ static int dp83867_of_init(struct phy_device *phydev) dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ti,tx-internal-delay", -1);

drivers/net/phy/ti.c +6 -0

+	if (fdtdec_get_bool(fdt, node, "enet-phy-lane-swap"))
+		dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
+
+	if (fdtdec_get_bool(fdt, node, "enet-phy-lane-no-swap"))
+		dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
+
 	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob,

dev_of_offset(dev), "ti,fifo-depth", -1);

drivers/net/phy/ti.c static int dp83867_config(struct phy_device · line 352

Quoted 9 lines

drivers/net/phy/ti.c +3 -0

@@ -307,6 +344,9 @@ static int dp83867_config(struct phy_device
 *phydev) }
 	}
 
+	if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
+		dp83867_config_port_mirroring(phydev);
+
 	genphy_config_aneg(phydev);
 	return 0;

Best regards,

Lukasz Majewski

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de -------------- next part --------------
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Janine Hagemann

author

2018-06-14 09:48 UTC #11 lore raw

PATCH 6/12 net: phy: ti: Recover from "port mirroring" N/A MODE4

https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954

The DP83867 when not properly bootstrapped - especially with LED_0 pin - can enter N/A MODE4 for "port mirroring" feature.

To provide normal operation of the PHY, one needs not only to explicitly disable the port mirroring feature, but as well stop some IC internal testing (which disables RGMII communication).

To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit 11 examined. When it is set, the another RESERVED bit (11) at PHYCR (0x0010) register must be clear to disable testing mode and enable RGMII communication.

Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) - Linux driver"

Based on commit 'ac6e058b75be71208e98a5808453aae9a17be480' of mainline linux kernel.

---
 drivers/net/phy/ti.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

drivers/net/phy/ti.c +23 -1

index 086ea4a..16c8929 100644
@@ -26,6 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Extended Registers */
 #define DP83867_CFG4		0x0031
 #define DP83867_RGMIICTL	0x0032
+#define DP83867_STRAP_STS1	0x006E
 #define DP83867_RGMIIDCTL	0x0086
 #define DP83867_IO_MUX_CFG	0x0170

@@ -50,6 +51,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_RGMII_TX_CLK_DELAY_EN		BIT(1)
 #define DP83867_RGMII_RX_CLK_DELAY_EN		BIT(0)
 
+/* STRAP_STS1 bits */
+#define DP83867_STRAP_STS1_RESERVED		BIT(11)
+
 /* PHY CTRL bits */
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
 #define DP83867_PHYCR_FIFO_DEPTH_MASK	(3 << 14)

@@ -251,7 +255,7 @@ static int dp83867_config(struct phy_device *phydev)
 {
 	struct dp83867_private *dp83867;
 	unsigned int val, delay, cfg2;
-	int ret;
+	int ret, bs;
 
 	if (!phydev->priv) {
 		dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);

@@ -282,6 +286,24 @@ static int dp83867_config(struct phy_device *phydev)
 
 		if (ret)
 			goto err_out;
+
+		/* The code below checks if "port mirroring" N/A MODE4 has been
+		 * enabled during power on bootstrap.
+		 *
+		 * Such N/A mode enabled by mistake can put PHY IC in some
+		 * internal testing mode and disable RGMII transmission.
+		 *
+		 * In this particular case one needs to check STRAP_STS1
+		 * register's bit 11 (marked as RESERVED).
+		 */
+
+		bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1,
+						DP83867_DEVADDR, phydev->addr);
+		if (bs & DP83867_STRAP_STS1_RESERVED)
+			val &= ~DP83867_PHYCR_RESERVED_MASK;
+
+		phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, val);
+
 	} else if (phy_interface_is_sgmii(phydev)) {
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 			  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));

Signature · 1 line

2.7.4

Joe Hershberger

2018-06-14 17:49 UTC #12 lore raw

PATCH 6/12 net: phy: ti: Recover from "port mirroring" N/A MODE4

Quoted 12 lines · Janine Hagemann

The DP83867 when not properly bootstrapped - especially with LED_0 pin - can enter N/A MODE4 for "port mirroring" feature.
To provide normal operation of the PHY, one needs not only to explicitly disable the port mirroring feature, but as well stop some IC internal testing (which disables RGMII communication).
To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit 11 examined. When it is set, the another RESERVED bit (11) at PHYCR (0x0010) register must be clear to disable testing mode and enable RGMII communication.

Quoted 8 lines

Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) - Linux driver"
https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
Based on commit 'ac6e058b75be71208e98a5808453aae9a17be480' of mainline linux kernel.

Same comment about commit reference format.

Quoted 2 lines

Signed-off-by Janine Hagemann <[email protected]>

Otherwise,

Lukasz Majewski

2018-06-15 07:24 UTC #13 lore raw

PATCH 6/12 net: phy: ti: Recover from "port mirroring" N/A MODE4

Hi Janine,

Quoted 12 lines

The DP83867 when not properly bootstrapped - especially with LED_0 pin - can enter N/A MODE4 for "port mirroring" feature.
To provide normal operation of the PHY, one needs not only to explicitly disable the port mirroring feature, but as well stop some IC internal testing (which disables RGMII communication).
To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit 11 examined. When it is set, the another RESERVED bit (11) at PHYCR (0x0010) register must be clear to disable testing mode and enable RGMII communication.

Quoted 9 lines

Thorough explanation of the problem can be found at following e2e
thread: "DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) - Linux driver"
https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
Based on commit 'ac6e058b75be71208e98a5808453aae9a17be480' of mainline linux kernel.

Thanks for bringing it into u-boot.

Acked-by Lukasz Majewski <[email protected]>

Quoted 67 lines

---
 drivers/net/phy/ti.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

drivers/net/phy/ti.c +7 -1

index 086ea4a..16c8929 100644
@@ -26,6 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Extended Registers */
 #define DP83867_CFG4		0x0031
 #define DP83867_RGMIICTL	0x0032
+#define DP83867_STRAP_STS1	0x006E
 #define DP83867_RGMIIDCTL	0x0086
 #define DP83867_IO_MUX_CFG	0x0170

@@ -50,6 +51,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_RGMII_TX_CLK_DELAY_EN		BIT(1)
 #define DP83867_RGMII_RX_CLK_DELAY_EN		BIT(0)
 
+/* STRAP_STS1 bits */
+#define DP83867_STRAP_STS1_RESERVED		BIT(11)
+
 /* PHY CTRL bits */
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
 #define DP83867_PHYCR_FIFO_DEPTH_MASK	(3 << 14)

@@ -251,7 +255,7 @@ static int dp83867_config(struct phy_device
 *phydev) {
 	struct dp83867_private *dp83867;
 	unsigned int val, delay, cfg2;
-	int ret;
+	int ret, bs;
 
 	if (!phydev->priv) {
 		dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);

@@ -282,6 +286,24 @@ static int dp83867_config(struct phy_device
 *phydev) 
 		if (ret)
 			goto err_out;
+
+		/* The code below checks if "port mirroring" N/A

MODE4 has been

drivers/net/phy/ti.c +3 -0

+		 * enabled during power on bootstrap.
+		 *
+		 * Such N/A mode enabled by mistake can put PHY IC

in some

drivers/net/phy/ti.c +1 -0

+		 * internal testing mode and disable RGMII

transmission.

drivers/net/phy/ti.c +2 -0

+		 *
+		 * In this particular case one needs to check

STRAP_STS1

drivers/net/phy/ti.c +4 -0

+		 * register's bit 11 (marked as RESERVED).
+		 */
+
+		bs = phy_read_mmd_indirect(phydev,

DP83867_STRAP_STS1,

drivers/net/phy/ti.c +1 -0

+						DP83867_DEVADDR,

phydev->addr);

drivers/net/phy/ti.c +4 -0

+		if (bs & DP83867_STRAP_STS1_RESERVED)
+			val &= ~DP83867_PHYCR_RESERVED_MASK;
+
+		phy_write(phydev, MDIO_DEVAD_NONE,

MII_DP83867_PHYCTRL, val); +

drivers/net/phy/ti.c +0 -0

 	} else if (phy_interface_is_sgmii(phydev)) {
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 			  (BMCR_ANENABLE | BMCR_FULLDPLX |

Quoted 1 line

BMCR_SPEED1000));

Best regards,

Lukasz Majewski

Janine Hagemann

author

2018-06-14 09:48 UTC #14 lore raw

PATCH 7/12 net: phy: ti: add workaround for incorrect RX_CTRL pin strap

[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf

The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)).

There are some boards which have the pin strapped this way and need software workaround suggested by the data manual. Bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This ensures proper operation of the PHY.

Implement driver support for device-tree property meant to advertise the wrong strapping.

Based on commit '371444764b9882d754d1e67dd212c932359a2293' of mainline linux kernel.

---
 drivers/net/phy/ti.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

drivers/net/phy/ti.c +13 -0

index 16c8929..cc04789 100644
@@ -112,6 +112,7 @@ struct dp83867_private {
 	int fifo_depth;
 	int io_impedance;
 	int port_mirroring;
+	bool rxctrl_strap_quirk;
 };
 
 /**

@@ -220,6 +221,9 @@ static int dp83867_of_init(struct phy_device *phydev)
 	else
 		dp83867->io_impedance = -EINVAL;
 
+	dp83867->rxctrl_strap_quirk = fdtdec_get_bool(fdt, node,
+					"ti,dp83867-rxctrl-strap-quirk");
+
 	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 				 "ti,rx-internal-delay", -1);

@@ -275,6 +279,15 @@ static int dp83867_config(struct phy_device *phydev)
 	phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 		  val | DP83867_SW_RESTART);
 
+	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
+	if (dp83867->rxctrl_strap_quirk) {
+		val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
+						DP83867_DEVADDR, phydev->addr);
+		val &= ~BIT(7);
+		phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+					phydev->addr, val);
+	}
+
 	if (phy_interface_is_rgmii(phydev)) {
 		val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
 		if (val < 0)

Signature · 1 line

2.7.4

Joe Hershberger

2018-06-14 17:51 UTC #15 lore raw

PATCH 7/12 net: phy: ti: add workaround for incorrect RX_CTRL pin strap

Quoted 9 lines · Janine Hagemann

The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)).
There are some boards which have the pin strapped this way and need software workaround suggested by the data manual. Bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This ensures proper operation of the PHY.

Quoted 7 lines

Implement driver support for device-tree property meant to advertise the wrong strapping.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
Based on commit '371444764b9882d754d1e67dd212c932359a2293' of mainline linux kernel.

And here...

Quoted 1 line

Signed-off-by Janine Hagemann <[email protected]>

Otherwise,

Janine Hagemann

author

2018-06-14 09:48 UTC #16 lore raw

PATCH 8/12 net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID

Using PHY internal delays in combination with the phy-mode rgmii-id/rxid/txid was not possible. Only rgmii was supported.

Now we can disable rockchip's gmac delay lines and also use rgmii-id/rxid/txid.

Based on commit 'eaf70ad14cbbb99d46b78b1307628a16a3f6075d' from mainline linux kernel.

---
 drivers/net/gmac_rockchip.c | 80 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 63 insertions(+), 17 deletions(-)

drivers/net/gmac_rockchip.c +63 ~~-17~~

index 0f91731..c01ae75 100644
@@ -24,6 +24,11 @@
 #include <dt-bindings/clock/rk3288-cru.h>
 #include "designware.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+#define DELAY_ENABLE(soc, tx, rx) \
+	(((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
+	((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
+
 /*
  * Platform data for the gmac
  *

@@ -286,8 +291,7 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     RK3228_RXCLK_DLY_ENA_GMAC_MASK |
 		     RK3228_TXCLK_DLY_ENA_GMAC_MASK,
 		     RK3228_GMAC_PHY_INTF_SEL_RGMII |
-		     RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
-		     RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+		     DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
 
 	rk_clrsetreg(&grf->mac_con[0],
 		     RK3228_CLK_RX_DL_CFG_GMAC_MASK |

@@ -310,8 +314,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     RK3288_TXCLK_DLY_ENA_GMAC_MASK |
 		     RK3288_CLK_RX_DL_CFG_GMAC_MASK |
 		     RK3288_CLK_TX_DL_CFG_GMAC_MASK,
-		     RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
-		     RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
+		     DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
 		     pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
 		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }

@@ -350,8 +353,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
 		     RK3328_TXCLK_DLY_ENA_GMAC_MASK,
 		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
-		     RK3328_RXCLK_DLY_ENA_GMAC_ENABLE |
-		     RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+		     DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
 
 	rk_clrsetreg(&grf->mac_con[0],
 		     RK3328_CLK_RX_DL_CFG_GMAC_MASK |

@@ -392,8 +394,7 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     RK3368_TXCLK_DLY_ENA_GMAC_MASK |
 		     RK3368_CLK_RX_DL_CFG_GMAC_MASK |
 		     RK3368_CLK_TX_DL_CFG_GMAC_MASK,
-		     RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
-		     RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
+		     DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
 		     pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
 		     pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
 }

@@ -413,8 +414,7 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     RK3399_TXCLK_DLY_ENA_GMAC_MASK |
 		     RK3399_CLK_RX_DL_CFG_GMAC_MASK |
 		     RK3399_CLK_TX_DL_CFG_GMAC_MASK,
-		     RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
-		     RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
+		     DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
 		     pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
 		     pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
 }

@@ -451,40 +451,86 @@ static int gmac_rockchip_probe(struct udevice *dev)
 
 	switch (eth_pdata->phy_interface) {
 	case PHY_INTERFACE_MODE_RGMII:
+		/* Set to RGMII mode */
+		if (ops->set_to_rgmii)
+			ops->set_to_rgmii(pdata);
+		else
+			return -EPERM;
+
 		/*
 		 * If the gmac clock is from internal pll, need to set and
 		 * check the return value for gmac clock at RGMII mode. If
 		 * the gmac clock is from external source, the clock rate
 		 * is not set, because of it is bypassed.
 		 */
+
 		if (!pdata->clock_input) {
 			rate = clk_set_rate(&clk, 125000000);
 			if (rate != 125000000)
 				return -EINVAL;
 		}
+		break;
 
+	case PHY_INTERFACE_MODE_RGMII_ID:
 		/* Set to RGMII mode */
-		if (ops->set_to_rgmii)
+		if (ops->set_to_rgmii) {
+			pdata->tx_delay = 0;
+			pdata->rx_delay = 0;
 			ops->set_to_rgmii(pdata);
-		else
+		} else
 			return -EPERM;
 
-		break;
-	case PHY_INTERFACE_MODE_RMII:
-		/* The commet is the same as RGMII mode */
 		if (!pdata->clock_input) {
-			rate = clk_set_rate(&clk, 50000000);
-			if (rate != 50000000)
+			rate = clk_set_rate(&clk, 125000000);
+			if (rate != 125000000)
 				return -EINVAL;
 		}
+		break;
 
+	case PHY_INTERFACE_MODE_RMII:
 		/* Set to RMII mode */
 		if (ops->set_to_rmii)
 			ops->set_to_rmii(pdata);
 		else
 			return -EPERM;
 
+		if (!pdata->clock_input) {
+			rate = clk_set_rate(&clk, 50000000);
+			if (rate != 50000000)
+				return -EINVAL;
+		}
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+		 /* Set to RGMII_RXID mode */
+		if (ops->set_to_rgmii) {
+			pdata->tx_delay = 0;
+			ops->set_to_rgmii(pdata);
+		} else
+			return -EPERM;
+
+		if (!pdata->clock_input) {
+			rate = clk_set_rate(&clk, 125000000);
+			if (rate != 125000000)
+				return -EINVAL;
+		}
 		break;
+
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* Set to RGMII_TXID mode */
+		if (ops->set_to_rgmii) {
+			pdata->rx_delay = 0;
+			ops->set_to_rgmii(pdata);
+		} else
+			return -EPERM;
+
+		if (!pdata->clock_input) {
+			rate = clk_set_rate(&clk, 125000000);
+			if (rate != 125000000)
+				return -EINVAL;
+		}
+		break;
+
 	default:
 		debug("NO interface defined!\n");
 		return -ENXIO;

Signature · 1 line

2.7.4

Joe Hershberger

2018-06-14 17:53 UTC #17 lore raw

PATCH 8/12 net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID

Quoted 8 lines · Janine Hagemann

Using PHY internal delays in combination with the phy-mode rgmii-id/rxid/txid was not possible. Only rgmii was supported.
Now we can disable rockchip's gmac delay lines and also use rgmii-id/rxid/txid.
Based on commit 'eaf70ad14cbbb99d46b78b1307628a16a3f6075d' from mainline linux kernel.

Same here...

Quoted 1 line

Signed-off-by Janine Hagemann <[email protected]>

Otherwise,

Janine Hagemann

author

2018-06-14 09:48 UTC #18 lore raw

PATCH 9/12 drivers: net: designware: Add reading of DT phy-handle node

Add the ability to read the phy-handle node of the gmac. Upon reading this handle the phy-id can be stored based on the reg node in the DT.

The phy-handle also needs to be stored and passed to the phy to access any phy data that is available.

---
 drivers/net/designware.c | 11 ++++++++++-
 drivers/net/designware.h |  1 +
 2 files changed, 11 insertions(+), 1 deletion(-)

drivers/net/designware.c +10 -1

index cf12521..8cc7fb9 100644
@@ -467,7 +467,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
 {
 	struct phy_device *phydev;
 	int mask = 0xffffffff, ret;
-
+	struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
 #ifdef CONFIG_PHY_ADDR
 	mask = 1 << CONFIG_PHY_ADDR;
 #endif

@@ -486,6 +486,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
 	}
 	phydev->advertising = phydev->supported;
 
+#ifdef CONFIG_DM_ETH
+	if (dw_pdata->phy_of_handle)
+		dev_set_of_offset(phydev->dev, dw_pdata->phy_of_handle);
+#endif
+
 	priv->phydev = phydev;
 	phy_config(phydev);

@@ -786,6 +791,7 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev)
 	int reset_flags = GPIOD_IS_OUT;
 #endif
 	int ret = 0;
+	int node = dev_of_offset(dev);
 
 	pdata->iobase = dev_read_addr(dev);
 	pdata->phy_interface = -1;

@@ -797,6 +803,9 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	dw_pdata->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
+							 "phy-handle");
+
 	pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
 
 #ifdef CONFIG_DM_GPIO

drivers/net/designware.h +1 -0

index dea12b7..a6b0443 100644
@@ -255,6 +255,7 @@ extern const struct eth_ops designware_eth_ops;
 struct dw_eth_pdata {
 	struct eth_pdata eth_pdata;
 	u32 reset_delays[3];
+	int phy_of_handle;
 };
 
 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);

Signature · 1 line

2.7.4

Joe Hershberger

2018-06-14 17:53 UTC #19 lore raw

PATCH 9/12 drivers: net: designware: Add reading of DT phy-handle node

Quoted 8 lines · Janine Hagemann

Add the ability to read the phy-handle node of the gmac. Upon reading this handle the phy-id can be stored based on the reg node in the DT.
The phy-handle also needs to be stored and passed to the phy to access any phy data that is available.
Signed-off-by Janine Hagemann <[email protected]>

Janine Hagemann

author

2018-06-14 09:48 UTC #20 lore raw

PATCH 10/12 net: phy: ti: Add binding for the CLK_OUT pin muxing

The DP83867 has a muxing option for the CLK_OUT pin. It is possible to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Based on commit '9708fb630d19ee51ae3aeb3a533e3010da0e8570' mainline linux kernel.

---
 drivers/net/phy/ti.c                 | 24 ++++++++++++++++++++++++
 include/dt-bindings/net/ti-dp83867.h | 15 +++++++++++++++
 2 files changed, 39 insertions(+)

drivers/net/phy/ti.c +24 -0

index cc04789..9044b0f 100644
@@ -96,6 +96,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK	(0x1f << 8)
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT	8
 
 /* CFG4 bits */
 #define DP83867_CFG4_PORT_MIRROR_EN		BIT(0)

@@ -113,6 +115,7 @@ struct dp83867_private {
 	int io_impedance;
 	int port_mirroring;
 	bool rxctrl_strap_quirk;
+	int clk_output_sel;
 };
 
 /**

@@ -213,6 +216,16 @@ static int dp83867_of_init(struct phy_device *phydev)
 	struct udevice *dev = phydev->dev;
 	int node = dev_of_offset(dev);
 	const void *fdt = gd->fdt_blob;
+	u16 val;
+
+	/* Optional configuration */
+
+	/* Keep the default value if ti,clk-output-sel is not set
+	 * or to high
+	 */
+
+	dp83867->clk_output_sel = fdtdec_get_uint(fdt, node,
+						  "ti,clk-output-sel", DP83867_CLK_O_SEL_REF_CLK);
 
 	if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;

@@ -239,6 +252,17 @@ static int dp83867_of_init(struct phy_device *phydev)
 	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 				 "ti,fifo-depth", -1);
 
+	/* Clock output selection if muxing property is set */
+	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
+		val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+					    DP83867_DEVADDR, phydev->addr);
+		val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
+		val |= (dp83867->clk_output_sel <<
+			DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
+		phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+					DP83867_DEVADDR, phydev->addr, val);
+	}
+
 	return 0;
 }
 #else

include/dt-bindings/net/ti-dp83867.h +15 -0

index b8e5df6..85d08f6 100644
@@ -31,4 +31,19 @@
 #define DP83867_RGMIIDCTL_3_75_NS	0xe
 #define DP83867_RGMIIDCTL_4_00_NS	0xf
 
+/* IO_MUX_CFG - Clock output selection */
+#define DP83867_CLK_O_SEL_CHN_A_RCLK		0x0
+#define DP83867_CLK_O_SEL_CHN_B_RCLK		0x1
+#define DP83867_CLK_O_SEL_CHN_C_RCLK		0x2
+#define DP83867_CLK_O_SEL_CHN_D_RCLK		0x3
+#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5	0x4
+#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5	0x5
+#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5	0x6
+#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5	0x7
+#define DP83867_CLK_O_SEL_CHN_A_TCLK		0x8
+#define DP83867_CLK_O_SEL_CHN_B_TCLK		0x9
+#define DP83867_CLK_O_SEL_CHN_C_TCLK		0xA
+#define DP83867_CLK_O_SEL_CHN_D_TCLK		0xB
+#define DP83867_CLK_O_SEL_REF_CLK		0xC
+
 #endif

Signature · 1 line

2.7.4

Joe Hershberger

2018-06-14 18:01 UTC #21 lore raw

PATCH 10/12 net: phy: ti: Add binding for the CLK_OUT pin muxing

Quoted 6 lines · Janine Hagemann

The DP83867 has a muxing option for the CLK_OUT pin. It is possible to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Based on commit '9708fb630d19ee51ae3aeb3a533e3010da0e8570' mainline linux kernel.

Same here...

Quoted 4 lines

---
 drivers/net/phy/ti.c                 | 24 ++++++++++++++++++++++++
 include/dt-bindings/net/ti-dp83867.h | 15 +++++++++++++++

Please also add to doc/device-tree-bindings/net/ti,dp83867.txt

drivers/net/phy/ti.c DECLARE_GLOBAL_DATA_PTR; · line 100

Quoted 12 lines

 2 files changed, 39 insertions(+)

drivers/net/phy/ti.c +2 -0

index cc04789..9044b0f 100644
@@ -96,6 +96,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX    0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN    0x1f
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK      (0x1f << 8)
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT     8

Reverse order of these defines and use the shift to make the mask.

Also, use GENMASK(13, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)

Quoted 12 lines

drivers/net/phy/ti.c +1 -0

 /* CFG4 bits */
 #define DP83867_CFG4_PORT_MIRROR_EN            BIT(0)

@@ -113,6 +115,7 @@ struct dp83867_private {
        int io_impedance;
        int port_mirroring;
        bool rxctrl_strap_quirk;
+       int clk_output_sel;
 };
 
 /**

drivers/net/phy/ti.c static int dp83867_of_init(struct phy_device *phydev) · line 223

Quoted 8 lines

drivers/net/phy/ti.c +5 -0

@@ -213,6 +216,16 @@ static int dp83867_of_init(struct phy_device *phydev)
        struct udevice *dev = phydev->dev;
        int node = dev_of_offset(dev);
        const void *fdt = gd->fdt_blob;
+       u16 val;
+
+       /* Optional configuration */
+
+       /* Keep the default value if ti,clk-output-sel is not set

Please use standard mutli-line comment format.... "/*" gets its own line.

Quoted 57 lines

drivers/net/phy/ti.c +16 -0

+        * or to high
+        */
+
+       dp83867->clk_output_sel = fdtdec_get_uint(fdt, node,
+                                                 "ti,clk-output-sel", DP83867_CLK_O_SEL_REF_CLK);
 
        if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
                dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;

@@ -239,6 +252,17 @@ static int dp83867_of_init(struct phy_device *phydev)
        dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
                                 "ti,fifo-depth", -1);
 
+       /* Clock output selection if muxing property is set */
+       if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
+               val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+                                           DP83867_DEVADDR, phydev->addr);
+               val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
+               val |= (dp83867->clk_output_sel <<
+                       DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
+               phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+                                       DP83867_DEVADDR, phydev->addr, val);
+       }
+
        return 0;
 }
 #else

include/dt-bindings/net/ti-dp83867.h +15 -1

index b8e5df6..85d08f6 100644
@@ -31,4 +31,19 @@
 #define DP83867_RGMIIDCTL_3_75_NS      0xe
 #define DP83867_RGMIIDCTL_4_00_NS      0xf
 
+/* IO_MUX_CFG - Clock output selection */
+#define DP83867_CLK_O_SEL_CHN_A_RCLK           0x0
+#define DP83867_CLK_O_SEL_CHN_B_RCLK           0x1
+#define DP83867_CLK_O_SEL_CHN_C_RCLK           0x2
+#define DP83867_CLK_O_SEL_CHN_D_RCLK           0x3
+#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5      0x4
+#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5      0x5
+#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5      0x6
+#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5      0x7
+#define DP83867_CLK_O_SEL_CHN_A_TCLK           0x8
+#define DP83867_CLK_O_SEL_CHN_B_TCLK           0x9
+#define DP83867_CLK_O_SEL_CHN_C_TCLK           0xA
+#define DP83867_CLK_O_SEL_CHN_D_TCLK           0xB
+#define DP83867_CLK_O_SEL_REF_CLK              0xC
+
 #endif
--

2.7.4

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Janine Hagemann

author

2018-06-14 09:48 UTC #22 lore raw

PATCH 11/12 ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing

The CLK_O_SEL default is synchronus to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

---
 arch/arm/dts/rk3288-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)

arch/arm/dts/rk3288-phycore-som.dtsi +1 -0

index 02d1196..2dba0aa 100644
@@ -191,6 +191,7 @@
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			enet-phy-lane-no-swap;
+			ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
 		};
 	};
 };

Signature · 1 line

2.7.4

Janine Hagemann

author

2018-06-14 09:48 UTC #23 lore raw

PATCH 12/12 rockchip: rk3288-phycore: set flash1 iodomain to 1.8V

This pin is supplied by 1.8V, but the default iodomain setting is 3.3V.