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Add initial RISC-V architecture support

PATCH Superseded Antony Pavlov 2 participants 18 messages Jun 28, 2018 – Jun 29, 2018

Subsystems (7)

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v2 cover Add initial RISC-V architecture support

This patchseries adds initial RISC-V architecture support for barebox.

See Documentation/boards/riscv.rst for instructions.

You can obtain this patchseries from github:

    $ git clone -b 20180628.riscv https://github.com/frantony/barebox

Changes since PATCH v1 (20170415)
(http://lists.infradead.org/pipermail/barebox/2018-April/032647.html)

* drop skeleton.dtsi;
* drop SPI GPIO bindings for erizo_generic;
* improve erizo-nmon-image;
* generic linker script is dropped;
* use generic GCC library routines from lib.

Changes since RFC v4 (20170927)
(http://lists.infradead.org/pipermail/barebox/2017-September/031226.html)

* drop 64-bit support;
* sync with RISC-V linux;
* RISC-V in barebox now is little endian only;
* fix according to notes by Oleksij Rempel.

Changes since RFC v3 (20161212)
(http://lists.infradead.org/pipermail/barebox/2016-December/028716.html)

* drop SiFive support, add support for custom Erizo SoC;
* barebox runs on real hardware (e.g. DE0-Nano FPGA board, see https://github.com/miet-riscv-workgroup/rv32-simple-soc for
details);
* introduce NMON for RISC-V;
* add relocator to start.S.

Changes since RFC v2 (20161113)
(http://lists.infradead.org/pipermail/barebox/2016-November/028533.html):

* add RV32 support.

Changes since RFC v1 (20161013)
(http://lists.infradead.org/pipermail/barebox/2016-October/028309.html):

* drop spike pk support;
* add qemu-sifive board support;
* add Documentation/boards/riscv.rst;
* fix guard macro names.

Antony Pavlov (12):
lib: Add shared copies of some GCC library routines
MIPS: Use generic GCC library routines from lib/ Add initial RISC-V architecture support
RISC-V: add Erizo SoC support
RISC-V: add low-level debug macros for ns16550
RISC-V: add nmon nano-monitor
RISC-V: erizo: add DEBUG_LL support
RISC-V: erizo: enable nmon
RISC-V: erizo: add nmon image creation
RISC-V: add erizo_generic_defconfig
scripts: add nmon-loader
Documentation: add RISC-V docs

 Documentation/boards/riscv.rst                |  91 +++++++
 arch/mips/Kconfig                             |   3 +
 arch/mips/lib/Makefile                        |   5 -
 arch/mips/lib/ashldi3.c                       |  28 ---
 arch/mips/lib/ashrdi3.c                       |  30 ---
 arch/mips/lib/libgcc.h                        |  29 ---
 arch/mips/lib/lshrdi3.c                       |  28 ---
 arch/riscv/Kconfig                            |  99 ++++++++
 arch/riscv/Makefile                           |  86 +++++++
 arch/riscv/boards/erizo-generic/.gitignore    |   1 +
 arch/riscv/boards/erizo-generic/Makefile      |   1 +
 arch/riscv/boards/erizo-generic/board.c       |  28 +++
 arch/riscv/boot/Makefile                      |   2 +
 arch/riscv/boot/main_entry.c                  |  40 +++
 arch/riscv/boot/start.S                       |  71 ++++++
 arch/riscv/configs/erizo_generic_defconfig    |  53 ++++
 arch/riscv/dts/.gitignore                     |   1 +
 arch/riscv/dts/Makefile                       |   9 +
 arch/riscv/dts/erizo.dtsi                     |  44 ++++
 arch/riscv/dts/erizo_generic.dts              |  12 +
 arch/riscv/include/asm/barebox.h              |   1 +
 arch/riscv/include/asm/bitops.h               |  35 +++
 arch/riscv/include/asm/bitsperlong.h          |  10 +
 arch/riscv/include/asm/byteorder.h            |   6 +
 arch/riscv/include/asm/common.h               |   6 +
 arch/riscv/include/asm/debug_ll_ns16550.h     | 186 ++++++++++++++
 arch/riscv/include/asm/elf.h                  |  11 +
 arch/riscv/include/asm/io.h                   |   8 +
 arch/riscv/include/asm/mmu.h                  |   6 +
 arch/riscv/include/asm/posix_types.h          |   1 +
 arch/riscv/include/asm/riscv_nmon.h           | 238 ++++++++++++++++++
 arch/riscv/include/asm/sections.h             |   1 +
 arch/riscv/include/asm/string.h               |   1 +
 arch/riscv/include/asm/swab.h                 |   6 +
 arch/riscv/include/asm/types.h                |  60 +++++
 arch/riscv/include/asm/unaligned.h            |  19 ++
 arch/riscv/lib/.gitignore                     |   1 +
 arch/riscv/lib/Makefile                       |   5 +
 arch/riscv/lib/asm-offsets.c                  |  12 +
 arch/riscv/lib/barebox.lds.S                  |  89 +++++++
 arch/riscv/lib/dtb.c                          |  41 +++
 arch/riscv/lib/riscv_timer.c                  |  67 +++++
 arch/riscv/mach-erizo/Kconfig                 |  11 +
 arch/riscv/mach-erizo/Makefile                |   3 +
 arch/riscv/mach-erizo/include/mach/debug_ll.h |  37 +++
 drivers/of/Kconfig                            |   2 +-
 include/lib/libgcc.h                          |  47 ++++
 lib/Kconfig                                   |   9 +
 lib/Makefile                                  |   7 +
 lib/ashldi3.c                                 |  44 ++++
 lib/ashrdi3.c                                 |  46 ++++
 lib/lshrdi3.c                                 |  45 ++++
 scripts/erizo-nmon-image                      |  10 +
 scripts/nmon-loader                           |  31 +++
 54 files changed, 1642 insertions(+), 121 deletions(-)
 create mode 100644 Documentation/boards/riscv.rst
 delete mode 100644 arch/mips/lib/ashldi3.c
 delete mode 100644 arch/mips/lib/ashrdi3.c
 delete mode 100644 arch/mips/lib/libgcc.h
 delete mode 100644 arch/mips/lib/lshrdi3.c
 create mode 100644 arch/riscv/Kconfig
 create mode 100644 arch/riscv/Makefile
 create mode 100644 arch/riscv/boards/erizo-generic/.gitignore
 create mode 100644 arch/riscv/boards/erizo-generic/Makefile
 create mode 100644 arch/riscv/boards/erizo-generic/board.c
 create mode 100644 arch/riscv/boot/Makefile
 create mode 100644 arch/riscv/boot/main_entry.c
 create mode 100644 arch/riscv/boot/start.S
 create mode 100644 arch/riscv/configs/erizo_generic_defconfig
 create mode 100644 arch/riscv/dts/.gitignore
 create mode 100644 arch/riscv/dts/Makefile
 create mode 100644 arch/riscv/dts/erizo.dtsi
 create mode 100644 arch/riscv/dts/erizo_generic.dts
 create mode 100644 arch/riscv/include/asm/barebox.h
 create mode 100644 arch/riscv/include/asm/bitops.h
 create mode 100644 arch/riscv/include/asm/bitsperlong.h
 create mode 100644 arch/riscv/include/asm/byteorder.h
 create mode 100644 arch/riscv/include/asm/common.h
 create mode 100644 arch/riscv/include/asm/debug_ll_ns16550.h
 create mode 100644 arch/riscv/include/asm/elf.h
 create mode 100644 arch/riscv/include/asm/io.h
 create mode 100644 arch/riscv/include/asm/mmu.h
 create mode 100644 arch/riscv/include/asm/posix_types.h
 create mode 100644 arch/riscv/include/asm/riscv_nmon.h
 create mode 100644 arch/riscv/include/asm/sections.h
 create mode 100644 arch/riscv/include/asm/string.h
 create mode 100644 arch/riscv/include/asm/swab.h
 create mode 100644 arch/riscv/include/asm/types.h
 create mode 100644 arch/riscv/include/asm/unaligned.h
 create mode 100644 arch/riscv/lib/.gitignore
 create mode 100644 arch/riscv/lib/Makefile
 create mode 100644 arch/riscv/lib/asm-offsets.c
 create mode 100644 arch/riscv/lib/barebox.lds.S
 create mode 100644 arch/riscv/lib/dtb.c
 create mode 100644 arch/riscv/lib/riscv_timer.c
 create mode 100644 arch/riscv/mach-erizo/Kconfig
 create mode 100644 arch/riscv/mach-erizo/Makefile
 create mode 100644 arch/riscv/mach-erizo/include/mach/debug_ll.h
 create mode 100644 include/lib/libgcc.h
 create mode 100644 lib/ashldi3.c
 create mode 100644 lib/ashrdi3.c
 create mode 100644 lib/lshrdi3.c
 create mode 100755 scripts/erizo-nmon-image
 create mode 100755 scripts/nmon-loader
Signature · 7 lines
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#1 lore raw

PATCH v2 1/12 lib: Add shared copies of some GCC library routines

This commit is based on these linux kernel commits:

| commit b35cd9884fa5d81c9d5e7f57c9d03264ae2bd835
| Author: Palmer Dabbelt <[email protected]>
| Date:   Tue May 23 10:28:26 2017 -0700
|
|     lib: Add shared copies of some GCC library routines
|
| commit e3d5980568fdf83c15a5a3c8ddca1590551ab7a2
| Author: Matt Redfearn <[email protected]>
| Date:   Wed Apr 11 08:50:17 2018 +0100
|
|     lib: Rename compiler intrinsic selects to GENERIC_LIB_*
---
 include/lib/libgcc.h | 47 ++++++++++++++++++++++++++++++++++++++++++++
 lib/Kconfig          |  9 +++++++++
 lib/Makefile         |  7 +++++++
 lib/ashldi3.c        | 44 +++++++++++++++++++++++++++++++++++++++++
 lib/ashrdi3.c        | 46 +++++++++++++++++++++++++++++++++++++++++++
 lib/lshrdi3.c        | 45 ++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 198 insertions(+)
include/lib/libgcc.h new file +47 -0
new file mode 100644
index 0000000000..adad27704a
@@ -0,0 +1,47 @@
+/*
+ * include/lib/libgcc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.
+ */
+
+#ifndef __LIB_LIBGCC_H
+#define __LIB_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+	int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+	int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+	struct DWstruct s;
+	long long ll;
+} DWunion;
+
+long long __lshrdi3(long long u, word_type b);
+long long __ashldi3(long long u, word_type b);
+long long __ashrdi3(long long u, word_type b);
+
+#endif /* __ASM_LIBGCC_H */
lib/Kconfig +9 -0
index 3d06655707..860d471de9 100644
@@ -129,4 +129,13 @@ source lib/bootstrap/Kconfig
 config PRINTF_UUID
 	bool
 
+config GENERIC_LIB_ASHLDI3
+	bool
+
+config GENERIC_LIB_ASHRDI3
+	bool
+
+config GENERIC_LIB_LSHRDI3
+	bool
+
 endmenu
lib/Makefile +7 -0
index a7498288af..693945fb2c 100644
@@ -65,3 +65,10 @@ obj-y			+= int_sqrt.o
 obj-y			+= parseopt.o
 obj-y			+= clz_ctz.o
 obj-$(CONFIG_CRC_CCITT) += crc-ccitt.o
+
+# GCC library routines
+obj-$(CONFIG_GENERIC_LIB_ASHLDI3) += ashldi3.o
+obj-$(CONFIG_GENERIC_LIB_ASHRDI3) += ashrdi3.o
+obj-$(CONFIG_GENERIC_LIB_LSHRDI3) += lshrdi3.o
+
+pbl-$(CONFIG_GENERIC_LIB_ASHLDI3) += ashldi3.o
lib/ashldi3.c new file +44 -0

44 lines not on this page · raw message

lib/ashrdi3.c new file +46 -0

46 lines not on this page · raw message

lib/lshrdi3.c new file +45 -0

45 lines not on this page · raw message

Signature · 7 lines
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#2 lore raw

PATCH v2 2/12 MIPS: Use generic GCC library routines from lib/

In reply to Antony Pavlov

This is a port of Linux kernel commit

| commit 740129b36faf049e6845819144542a0455e1e285
| Author: Antony Pavlov <[email protected]>
| Date:   Wed Apr 11 08:50:19 2018 +0100
|
|     MIPS: Use generic GCC library routines from lib/
---
 arch/mips/Kconfig       |  3 +++
 arch/mips/lib/Makefile  |  5 -----
 arch/mips/lib/ashldi3.c | 28 ----------------------------
 arch/mips/lib/ashrdi3.c | 30 ------------------------------
 arch/mips/lib/libgcc.h  | 29 -----------------------------
 arch/mips/lib/lshrdi3.c | 28 ----------------------------
 6 files changed, 3 insertions(+), 120 deletions(-)
arch/mips/Kconfig +3 -0
index 359f67883c..5dd95b42a7 100644
@@ -3,6 +3,9 @@
 #
 config MIPS
 	bool
+	select GENERIC_LIB_ASHLDI3
+	select GENERIC_LIB_ASHRDI3
+	select GENERIC_LIB_LSHRDI3
 	select HAS_KALLSYMS
 	select HAVE_CONFIGURABLE_MEMORY_LAYOUT
 	select HAVE_CONFIGURABLE_TEXT_BASE
arch/mips/lib/Makefile +0 -5
index d25d0969fc..1a049c7914 100644
@@ -1,8 +1,5 @@
 extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds
 obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
-obj-y += lshrdi3.o
-obj-y += ashldi3.o
-obj-y += ashrdi3.o
 obj-y += cpu-probe.o
 obj-y += traps.o
 obj-y += genex.o
@@ -17,5 +14,3 @@ obj-$(CONFIG_CPU_MIPS64) += c-r4k.o
 
 obj-$(CONFIG_CMD_MIPS_CPUINFO) += cpuinfo.o
 obj-$(CONFIG_CMD_BOOTM)	+= bootm.o
-
-pbl-y	+= ashldi3.o
arch/mips/lib/ashldi3.c deleted +0 -28
deleted file mode 100644
index cbdbcbb6a9..0000000000
@@ -1,28 +0,0 @@
-#include <module.h>
-
-#include "libgcc.h"
-
-long long __ashldi3(long long u, word_type b)
-{
-	DWunion uu, w;
-	word_type bm;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-	bm = 32 - b;
-
-	if (bm <= 0) {
-		w.s.low = 0;
-		w.s.high = (unsigned int) uu.s.low << -bm;
-	} else {
-		const unsigned int carries = (unsigned int) uu.s.low >> bm;
-
-		w.s.low = (unsigned int) uu.s.low << b;
-		w.s.high = ((unsigned int) uu.s.high << b) | carries;
-	}
-
-	return w.ll;
-}
-EXPORT_SYMBOL(__ashldi3);
arch/mips/lib/ashrdi3.c deleted +0 -30
deleted file mode 100644
index 928d6d97ce..0000000000
@@ -1,30 +0,0 @@
-#include <module.h>
-
-#include "libgcc.h"
-
-long long __ashrdi3(long long u, word_type b)
-{
-	DWunion uu, w;
-	word_type bm;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-	bm = 32 - b;
-
-	if (bm <= 0) {
-		/* w.s.high = 1..1 or 0..0 */
-		w.s.high =
-		    uu.s.high >> 31;
-		w.s.low = uu.s.high >> -bm;
-	} else {
-		const unsigned int carries = (unsigned int) uu.s.high << bm;
-
-		w.s.high = uu.s.high >> b;
-		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
-	}
-
-	return w.ll;
-}
-EXPORT_SYMBOL(__ashrdi3);
arch/mips/lib/libgcc.h deleted +0 -29
deleted file mode 100644
index 593e598022..0000000000
@@ -1,29 +0,0 @@
-#ifndef __ASM_LIBGCC_H
-#define __ASM_LIBGCC_H
-
-#include <asm/byteorder.h>
-
-typedef int word_type __attribute__ ((mode (__word__)));
-
-#ifdef __BIG_ENDIAN
-struct DWstruct {
-	int high, low;
-};
-#elif defined(__LITTLE_ENDIAN)
-struct DWstruct {
-	int low, high;
-};
-#else
-#error I feel sick.
-#endif
-
-typedef union {
-	struct DWstruct s;
-	long long ll;
-} DWunion;
-
-long long __lshrdi3(long long u, word_type b);
-long long __ashldi3(long long u, word_type b);
-long long __ashrdi3(long long u, word_type b);
-
-#endif /* __ASM_LIBGCC_H */
arch/mips/lib/lshrdi3.c deleted +0 -28
deleted file mode 100644
index 74a4846e97..0000000000
@@ -1,28 +0,0 @@
-#include <module.h>
-
-#include "libgcc.h"
-
-long long __lshrdi3(long long u, word_type b)
-{
-	DWunion uu, w;
-	word_type bm;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-	bm = 32 - b;
-
-	if (bm <= 0) {
-		w.s.high = 0;
-		w.s.low = (unsigned int) uu.s.high >> -bm;
-	} else {
-		const unsigned int carries = (unsigned int) uu.s.high << bm;
-
-		w.s.high = (unsigned int) uu.s.high >> b;
-		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
-	}
-
-	return w.ll;
-}
-EXPORT_SYMBOL(__lshrdi3);
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#3 lore raw

PATCH v2 3/12 Add initial RISC-V architecture support

In reply to Antony Pavlov
---
 arch/riscv/Kconfig                   | 62 +++++++++++++++++++
 arch/riscv/Makefile                  | 72 ++++++++++++++++++++++
 arch/riscv/boot/Makefile             |  2 +
 arch/riscv/boot/main_entry.c         | 40 +++++++++++++
 arch/riscv/boot/start.S              | 63 ++++++++++++++++++++
 arch/riscv/dts/.gitignore            |  1 +
 arch/riscv/dts/Makefile              |  9 +++
 arch/riscv/include/asm/barebox.h     |  1 +
 arch/riscv/include/asm/bitops.h      | 35 +++++++++++
 arch/riscv/include/asm/bitsperlong.h | 10 ++++
 arch/riscv/include/asm/byteorder.h   |  6 ++
 arch/riscv/include/asm/common.h      |  6 ++
 arch/riscv/include/asm/elf.h         | 11 ++++
 arch/riscv/include/asm/io.h          |  8 +++
 arch/riscv/include/asm/mmu.h         |  6 ++
 arch/riscv/include/asm/posix_types.h |  1 +
 arch/riscv/include/asm/sections.h    |  1 +
 arch/riscv/include/asm/string.h      |  1 +
 arch/riscv/include/asm/swab.h        |  6 ++
 arch/riscv/include/asm/types.h       | 60 +++++++++++++++++++
 arch/riscv/include/asm/unaligned.h   | 19 ++++++
 arch/riscv/lib/.gitignore            |  1 +
 arch/riscv/lib/Makefile              |  5 ++
 arch/riscv/lib/asm-offsets.c         | 12 ++++
 arch/riscv/lib/barebox.lds.S         | 89 ++++++++++++++++++++++++++++
 arch/riscv/lib/dtb.c                 | 41 +++++++++++++
 arch/riscv/lib/riscv_timer.c         | 67 +++++++++++++++++++++
 drivers/of/Kconfig                   |  2 +-
 28 files changed, 636 insertions(+), 1 deletion(-)
arch/riscv/Kconfig new file +62 -0
new file mode 100644
index 0000000000..8bbe52f232
@@ -0,0 +1,62 @@
+config RISCV
+	def_bool y
+	select GENERIC_FIND_NEXT_BIT
+	select HAVE_CONFIGURABLE_MEMORY_LAYOUT
+	select HAVE_CONFIGURABLE_TEXT_BASE
+	select GPIOLIB
+	select OFTREE
+	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
+	select CLKDEV_LOOKUP
+
+config ARCH_TEXT_BASE
+	hex
+	default 0x0
+
+menu "Machine selection"
+
+choice
+	prompt "Base ISA"
+	default ARCH_RV32I
+
+config ARCH_RV32I
+	bool "RV32I"
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select GENERIC_LIB_ASHLDI3
+	select GENERIC_LIB_ASHRDI3
+	select GENERIC_LIB_LSHRDI3
+
+endchoice
+
+config CPU_SUPPORTS_32BIT_KERNEL
+	bool
+
+choice
+	prompt "barebox code model"
+	default 32BIT
+
+config 32BIT
+	bool "32-bit barebox"
+	depends on CPU_SUPPORTS_32BIT_KERNEL
+	help
+	  Select this option to build a 32-bit barebox.
+
+endchoice
+
+config BUILTIN_DTB
+	bool "link a DTB into the barebox image"
+	depends on OFTREE
+
+config BUILTIN_DTB_NAME
+	string "DTB to build into the barebox image"
+	depends on BUILTIN_DTB
+
+endmenu
+
+source common/Kconfig
+source commands/Kconfig
+source net/Kconfig
+source drivers/Kconfig
+source fs/Kconfig
+source lib/Kconfig
+source crypto/Kconfig
arch/riscv/Makefile new file +72 -0

72 lines not on this page · raw message

arch/riscv/boot/Makefile new file +2 -0
new file mode 100644
index 0000000000..d6d28ce652
@@ -0,0 +1,2 @@
+obj-y += start.o
+obj-y += main_entry.o
arch/riscv/boot/main_entry.c new file +40 -0
new file mode 100644
index 0000000000..18db86da58
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <[email protected]>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <memory.h>
+#include <asm-generic/memory_layout.h>
+#include <asm/sections.h>
+
+void main_entry(void);
+
+/**
+ * Called plainly from assembler code
+ *
+ * @note The C environment isn't initialized yet
+ */
+void main_entry(void)
+{
+	/* clear the BSS first */
+	memset(__bss_start, 0x00, __bss_stop - __bss_start);
+
+	mem_malloc_init((void *)MALLOC_BASE,
+			(void *)(MALLOC_BASE + MALLOC_SIZE - 1));
+
+	start_barebox();
+}
arch/riscv/boot/start.S new file +63 -0

63 lines not on this page · raw message

arch/riscv/dts/.gitignore new file +1 -0
new file mode 100644
index 0000000000..077903c50a
@@ -0,0 +1 @@
+*dtb*
arch/riscv/dts/Makefile new file +9 -0
new file mode 100644
index 0000000000..f8380b11c9
@@ -0,0 +1,9 @@
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
+obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
+
+# just to build a built-in.o. Otherwise compilation fails when no devicetree is
+# created.
+obj- += dummy.o
+
+always := $(dtb-y)
+clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
arch/riscv/include/asm/barebox.h new file +1 -0
new file mode 100644
index 0000000000..2997587d82
@@ -0,0 +1 @@
+/* dummy */
arch/riscv/include/asm/bitops.h new file +35 -0
new file mode 100644
index 0000000000..e77ab83202
@@ -0,0 +1,35 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#ifndef _ASM_BITOPS_H_
+#define _ASM_BITOPS_H_
+
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ops.h>
+
+#define set_bit(x, y)			__set_bit(x, y)
+#define clear_bit(x, y)			__clear_bit(x, y)
+#define change_bit(x, y)		__change_bit(x, y)
+#define test_and_set_bit(x, y)		__test_and_set_bit(x, y)
+#define test_and_clear_bit(x, y)	__test_and_clear_bit(x, y)
+#define test_and_change_bit(x, y)	__test_and_change_bit(x, y)
+
+#endif /* _ASM_BITOPS_H_ */
arch/riscv/include/asm/bitsperlong.h new file +10 -0
new file mode 100644
index 0000000000..4641e7e485
@@ -0,0 +1,10 @@
+#ifndef __ASM_BITSPERLONG_H
+#define __ASM_BITSPERLONG_H
+
+#ifdef __riscv64
+#define BITS_PER_LONG 64
+#else
+#define BITS_PER_LONG 32
+#endif
+
+#endif /* __ASM_BITSPERLONG_H */
arch/riscv/include/asm/byteorder.h new file +6 -0
new file mode 100644
index 0000000000..0be826927b
@@ -0,0 +1,6 @@
+#ifndef _ASM_RISCV_BYTEORDER_H
+#define _ASM_RISCV_BYTEORDER_H
+
+#include <linux/byteorder/little_endian.h>
+
+#endif /* _ASM_RISCV_BYTEORDER_H */
arch/riscv/include/asm/common.h new file +6 -0
new file mode 100644
index 0000000000..bc8a17e30b
@@ -0,0 +1,6 @@
+#ifndef ASM_RISCV_COMMON_H
+#define ASM_RISCV_COMMON_H
+
+/* nothing special yet */
+
+#endif /* ASM_RISCV_COMMON_H */
arch/riscv/include/asm/elf.h new file +11 -0
new file mode 100644
index 0000000000..7134fa0582
@@ -0,0 +1,11 @@
+#ifndef __ASM_RISCV_ELF_H__
+#define __ASM_RISCV_ELF_H__
+
+#if __SIZEOF_POINTER__ == 8
+#define ELF_CLASS	ELFCLASS64
+#define CONFIG_PHYS_ADDR_T_64BIT
+#else
+#define ELF_CLASS	ELFCLASS32
+#endif
+
+#endif /* __ASM_RISCV_ELF_H__ */
arch/riscv/include/asm/io.h new file +8 -0
new file mode 100644
index 0000000000..3cdea7fcac
@@ -0,0 +1,8 @@
+#ifndef __ASM_RISCV_IO_H
+#define __ASM_RISCV_IO_H
+
+#define IO_SPACE_LIMIT 0
+
+#include <asm-generic/io.h>
+
+#endif /* __ASM_RISCV_IO_H */
arch/riscv/include/asm/mmu.h new file +6 -0
new file mode 100644
index 0000000000..95af871420
@@ -0,0 +1,6 @@
+#ifndef __ASM_MMU_H
+#define __ASM_MMU_H
+
+#define MAP_ARCH_DEFAULT MAP_UNCACHED
+
+#endif /* __ASM_MMU_H */
arch/riscv/include/asm/posix_types.h new file +1 -0
new file mode 100644
index 0000000000..22cae6230c
@@ -0,0 +1 @@
+#include <asm-generic/posix_types.h>
arch/riscv/include/asm/sections.h new file +1 -0
new file mode 100644
index 0000000000..2b8c516038
@@ -0,0 +1 @@
+#include <asm-generic/sections.h>
arch/riscv/include/asm/string.h new file +1 -0
new file mode 100644
index 0000000000..2997587d82
@@ -0,0 +1 @@
+/* dummy */
arch/riscv/include/asm/swab.h new file +6 -0
new file mode 100644
index 0000000000..60a90120b6
@@ -0,0 +1,6 @@
+#ifndef _ASM_SWAB_H
+#define _ASM_SWAB_H
+
+/* nothing. use generic functions */
+
+#endif /* _ASM_SWAB_H */
arch/riscv/include/asm/types.h new file +60 -0

60 lines not on this page · raw message

arch/riscv/include/asm/unaligned.h new file +19 -0
new file mode 100644
index 0000000000..aaebc06411
@@ -0,0 +1,19 @@
+#ifndef _ASM_RISCV_UNALIGNED_H
+#define _ASM_RISCV_UNALIGNED_H
+
+/*
+ * FIXME: this file is copy-n-pasted from sandbox's unaligned.h
+ */
+
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define get_unaligned __get_unaligned_le
+#define put_unaligned __put_unaligned_le
+#else
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+#endif
+
+#endif /* _ASM_RISCV_UNALIGNED_H */
arch/riscv/lib/.gitignore new file +1 -0
new file mode 100644
index 0000000000..d1165788c9
@@ -0,0 +1 @@
+barebox.lds
arch/riscv/lib/Makefile new file +5 -0
new file mode 100644
index 0000000000..8dcd1e2728
@@ -0,0 +1,5 @@
+extra-y += barebox.lds
+
+obj-y += riscv_timer.o
+
+obj-$(CONFIG_BUILTIN_DTB) += dtb.o
arch/riscv/lib/asm-offsets.c new file +12 -0
new file mode 100644
index 0000000000..22f382b71e
@@ -0,0 +1,12 @@
+/*
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ */
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+	return 0;
+}
arch/riscv/lib/barebox.lds.S new file +89 -0

89 lines not on this page · raw message

arch/riscv/lib/dtb.c new file +41 -0

41 lines not on this page · raw message

arch/riscv/lib/riscv_timer.c new file +67 -0

67 lines not on this page · raw message

drivers/of/Kconfig +1 -1
index a1fac0e613..24cf4465a8 100644
@@ -4,7 +4,7 @@ config OFTREE
 
 config OFTREE_MEM_GENERIC
 	depends on OFTREE
-	depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX
+	depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX || RISCV
 	def_bool y
 
 config DTC
Signature · 7 lines
2.18.0


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#4 lore raw
Quoted 32 lines · Antony Pavlov

---
+++ b/arch/riscv/lib/barebox.lds.S

arch/riscv/lib/barebox.lds.S new file +28 -0
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <[email protected]>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm-generic/barebox.lds.h>
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SECTIONS
+{
+	. = TEXT_BASE;
+
+	. = ALIGN(8);
+	.text      :
+	{

arch/riscv/lib/barebox.lds.S line 38

Quoted 10 lines
arch/riscv/lib/barebox.lds.S new file +10 -0
+		_stext = .;
+		_start = .;
+		KEEP(*(.text_entry*))
+		_text = .;
+		__bare_init_start = .;
+		*(.text_bare_init*)
+		__bare_init_end = .;
+		*(.text*)
+	}
+	BAREBOX_BARE_INIT_SIZE

Do you need these __bare_init* stuff? If not I would prefer to remove it.

arch/riscv/lib/barebox.lds.S line 40

Quoted 2 lines
arch/riscv/lib/barebox.lds.S new file +2 -0
+
+	PRE_IMAGE

Same here.

Quoted 5 lines
arch/riscv/lib/dtb.c new file +5 -0
+static int of_riscv_init(void)
+{
+	struct device_node *root;
+
+	root = of_get_root_node();

arch/riscv/lib/dtb.c line 37

Quoted 10 lines
arch/riscv/lib/dtb.c new file +10 -0
+	if (root)
+		return 0;
+
+	root = of_unflatten_dtb(__dtb_start);
+	if (!IS_ERR(root)) {
+		pr_debug("using internal DTB\n");
+		of_set_root_node(root);
+		if (IS_ENABLED(CONFIG_OFDEVICE))
+			of_probe();
+	}

Can we just call of_unflatten_dtb()/of_set_root_node() from the board code and use obj-dtb-y to include the dtb?

That way a board can specify the dtb and not the config.

Sascha

Signature · 9 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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#5 lore raw
Quoted 38 lines · On Fri, 29 Jun 2018 09:29:08 +0200 Sascha Hauer <[email protected]> wrote:
Quoted 37 lines · Antony Pavlov

---
+++ b/arch/riscv/lib/barebox.lds.S

arch/riscv/lib/barebox.lds.S new file +33 -0
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2016 Antony Pavlov <[email protected]>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm-generic/barebox.lds.h>
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SECTIONS
+{
+	. = TEXT_BASE;
+
+	. = ALIGN(8);
+	.text      :
+	{
+		_stext = .;
+		_start = .;
+		KEEP(*(.text_entry*))
+		_text = .;
+		__bare_init_start = .;
Quoted 8 lines

arch/riscv/lib/barebox.lds.S line 38

Quoted 5 lines
arch/riscv/lib/barebox.lds.S new file +5 -0
+		*(.text_bare_init*)
+		__bare_init_end = .;
+		*(.text*)
+	}
+	BAREBOX_BARE_INIT_SIZE

Do you need these __bare_init* stuff? If not I would prefer to remove it.

Hmmm. You are right! I have not realized PBL for RISC-V yet so it's better to drop all these bare_inits.

Quoted 24 lines

arch/riscv/lib/barebox.lds.S line 40

Quoted 2 lines
arch/riscv/lib/barebox.lds.S new file +2 -0
+
+	PRE_IMAGE

Same here.

Quoted 5 lines
arch/riscv/lib/dtb.c new file +5 -0
+static int of_riscv_init(void)
+{
+	struct device_node *root;
+
+	root = of_get_root_node();

arch/riscv/lib/dtb.c line 37

Quoted 10 lines
arch/riscv/lib/dtb.c new file +10 -0
+	if (root)
+		return 0;
+
+	root = of_unflatten_dtb(__dtb_start);
+	if (!IS_ERR(root)) {
+		pr_debug("using internal DTB\n");
+		of_set_root_node(root);
+		if (IS_ENABLED(CONFIG_OFDEVICE))
+			of_probe();
+	}

Can we just call of_unflatten_dtb()/of_set_root_node() from the board code and use obj-dtb-y to include the dtb?

Quoted 1 line

That way a board can specify the dtb and not the config.

Good idea! MIPS code lacks this feature at the moment.

Can I use of_arm_init() as a reference?

Signature · 7 lines
Best regards,
  Antony Pavlov

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#6 lore raw
Quoted 8 lines · Antony Pavlov

On Fri, 29 Jun 2018 09:29:08 +0200

Quoted 3 lines

Do you need these __bare_init* stuff? If not I would prefer to remove it.

Hmmm. You are right! I have not realized PBL for RISC-V yet so it's better to drop all these bare_inits.

This isn't needed for PBL either. It is only for cases where the boot ROM only loads the initial image portion.

Quoted 20 lines
Quoted 20 lines
Quoted 6 lines
arch/riscv/lib/dtb.c new file +5 -0
+static int of_riscv_init(void)
+{
+	struct device_node *root;
+
+	root = of_get_root_node();

arch/riscv/lib/dtb.c line 37

Quoted 10 lines
arch/riscv/lib/dtb.c new file +10 -0
+	if (root)
+		return 0;
+
+	root = of_unflatten_dtb(__dtb_start);
+	if (!IS_ERR(root)) {
+		pr_debug("using internal DTB\n");
+		of_set_root_node(root);
+		if (IS_ENABLED(CONFIG_OFDEVICE))
+			of_probe();
+	}

Can we just call of_unflatten_dtb()/of_set_root_node() from the board code and use obj-dtb-y to include the dtb?

Quoted 5 lines
Quoted 1 line

That way a board can specify the dtb and not the config.

Good idea! MIPS code lacks this feature at the moment.

Can I use of_arm_init() as a reference?

Not sure what you mean. of_riscv_init() is nearly a copy of of_arm_init() already.

Sascha

Signature · 9 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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#7 lore raw
Quoted 33 lines · On Fri, 29 Jun 2018 13:32:55 +0200 Sascha Hauer <[email protected]> wrote:
Quoted 8 lines · Antony Pavlov

On Fri, 29 Jun 2018 09:29:08 +0200

Quoted 3 lines

Do you need these __bare_init* stuff? If not I would prefer to remove it.

Hmmm. You are right! I have not realized PBL for RISC-V yet so it's better to drop all these bare_inits.

This isn't needed for PBL either. It is only for cases where the boot ROM only loads the initial image portion.

Quoted 20 lines
Quoted 20 lines
Quoted 6 lines
arch/riscv/lib/dtb.c new file +5 -0
+static int of_riscv_init(void)
+{
+	struct device_node *root;
+
+	root = of_get_root_node();

arch/riscv/lib/dtb.c line 37

Quoted 10 lines
arch/riscv/lib/dtb.c new file +10 -0
+	if (root)
+		return 0;
+
+	root = of_unflatten_dtb(__dtb_start);
+	if (!IS_ERR(root)) {
+		pr_debug("using internal DTB\n");
+		of_set_root_node(root);
+		if (IS_ENABLED(CONFIG_OFDEVICE))
+			of_probe();
+	}

Can we just call of_unflatten_dtb()/of_set_root_node() from the board code and use obj-dtb-y to include the dtb?

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

That way a board can specify the dtb and not the config.

Good idea! MIPS code lacks this feature at the moment.

Can I use of_arm_init() as a reference?

Not sure what you mean. of_riscv_init() is nearly a copy of of_arm_init() already.

Actually of_riscv_init() is a copy of of_mips_init().

Signature · 7 lines
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  Antony Pavlov

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#8 lore raw

PATCH v2 4/12 RISC-V: add Erizo SoC support

In reply to Antony Pavlov

Erizo is an opensource hardware SoC for FPGA.

---
 arch/riscv/Kconfig                         | 11 ++++++
 arch/riscv/Makefile                        |  3 ++
 arch/riscv/boards/erizo-generic/.gitignore |  1 +
 arch/riscv/boards/erizo-generic/Makefile   |  1 +
 arch/riscv/boards/erizo-generic/board.c    | 28 ++++++++++++++
 arch/riscv/dts/erizo.dtsi                  | 44 ++++++++++++++++++++++
 arch/riscv/dts/erizo_generic.dts           | 12 ++++++
 arch/riscv/mach-erizo/Kconfig              | 11 ++++++
 arch/riscv/mach-erizo/Makefile             |  3 ++
 9 files changed, 114 insertions(+)
arch/riscv/Kconfig +11 -0
index 8bbe52f232..bcca385e14 100644
@@ -15,6 +15,15 @@ config ARCH_TEXT_BASE
 
 menu "Machine selection"
 
+choice
+	prompt "System type"
+	default MACH_ERIZO
+
+config MACH_ERIZO
+	bool "erizo family"
+
+endchoice
+
 choice
 	prompt "Base ISA"
 	default ARCH_RV32I
@@ -51,6 +60,8 @@ config BUILTIN_DTB_NAME
 	string "DTB to build into the barebox image"
 	depends on BUILTIN_DTB
 
+source arch/riscv/mach-erizo/Kconfig
+
 endmenu
 
 source common/Kconfig
arch/riscv/Makefile +3 -0
index e9c407354c..9a3921065c 100644
@@ -11,6 +11,9 @@ cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \
 LDFLAGS += $(ldflags-y)
 LDFLAGS_barebox += -nostdlib
 
+machine-$(CONFIG_MACH_ERIZO)	:= erizo
+board-$(CONFIG_BOARD_ERIZO_GENERIC)	:= erizo-generic
+
 TEXT_BASE = $(CONFIG_TEXT_BASE)
 CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
 
arch/riscv/boards/erizo-generic/.gitignore new file +1 -0
new file mode 100644
index 0000000000..d1165788c9
@@ -0,0 +1 @@
+barebox.lds
arch/riscv/boards/erizo-generic/Makefile new file +1 -0
new file mode 100644
index 0000000000..dcfc2937d3
@@ -0,0 +1 @@
+obj-y += board.o
arch/riscv/boards/erizo-generic/board.c new file +28 -0
new file mode 100644
index 0000000000..46c9ca34f0
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2017 Antony Pavlov <[email protected]>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+
+static int hostname_init(void)
+{
+	barebox_set_hostname("erizo-generic");
+
+	return 0;
+}
+postcore_initcall(hostname_init);
arch/riscv/dts/erizo.dtsi new file +44 -0

44 lines not on this page · raw message

arch/riscv/dts/erizo_generic.dts new file +12 -0
new file mode 100644
index 0000000000..fae265fd96
@@ -0,0 +1,12 @@
+#include "erizo.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "generic Erizo SoC board";
+	compatible = "miet-riscv-workgroup,erizo-generic-board";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x80000000 0x00800000>;
+	};
+};
arch/riscv/mach-erizo/Kconfig new file +11 -0
new file mode 100644
index 0000000000..2400b4437b
@@ -0,0 +1,11 @@
+if MACH_ERIZO
+
+choice
+	prompt "Board type"
+
+config BOARD_ERIZO_GENERIC
+	bool "erizo generic board"
+
+endchoice
+
+endif
arch/riscv/mach-erizo/Makefile new file +3 -0
new file mode 100644
index 0000000000..d9c51e74c3
@@ -0,0 +1,3 @@
+# just to build a built-in.o. Otherwise compilation fails when no o-files is
+# created.
+obj- += dummy.o
Signature · 7 lines
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#9 lore raw

PATCH v2 5/12 RISC-V: add low-level debug macros for ns16550

In reply to Antony Pavlov

This patch adds macros for ns16550 port initialization and single char output. The macros can be used in MIPS asm pbl code.

---
 arch/riscv/include/asm/debug_ll_ns16550.h | 186 ++++++++++++++++++++++
 1 file changed, 186 insertions(+)
arch/riscv/include/asm/debug_ll_ns16550.h new file +186 -0
new file mode 100644
index 0000000000..6929453b1e
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2016, 2017 Antony Pavlov <[email protected]>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/** @file
+ *  This file contains declaration for early output support
+ */
+#ifndef __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__
+#define __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__
+
+#include <linux/kconfig.h>
+
+#ifdef CONFIG_DEBUG_LL
+
+#ifndef DEBUG_LL_UART_ADDR
+#error DEBUG_LL_UART_ADDR is undefined!
+#endif
+
+#ifndef DEBUG_LL_UART_SHIFT
+#error DEBUG_LL_UART_SHIFT is undefined!
+#endif
+
+#ifndef DEBUG_LL_UART_DIVISOR
+#error DEBUG_LL_UART_DIVISOR is undefined!
+#endif
+
+#endif /* CONFIG_DEBUG_LL */
+
+#define UART_THR	(0x0 << DEBUG_LL_UART_SHIFT)
+#define UART_RBR	(0x0 << DEBUG_LL_UART_SHIFT)
+#define UART_DLL	(0x0 << DEBUG_LL_UART_SHIFT)
+#define UART_DLM	(0x1 << DEBUG_LL_UART_SHIFT)
+#define UART_LCR	(0x3 << DEBUG_LL_UART_SHIFT)
+#define UART_LSR	(0x5 << DEBUG_LL_UART_SHIFT)
+
+#define UART_LCR_W	0x07	/* Set UART to 8,N,2 & DLAB = 0 */
+#define UART_LCR_DLAB	0x87	/* Set UART to 8,N,2 & DLAB = 1 */
+
+#define UART_LSR_DR	0x01    /* UART received data present */
+#define UART_LSR_THRE	0x20	/* Xmit holding register empty */
+
+#if defined(DEBUG_LL_UART_IOSIZE32)
+#define UART_REG_L	lw
+#define UART_REG_S	sw
+#elif defined(DEBUG_LL_UART_IOSIZE8)
+#define UART_REG_L	lbu
+#define UART_REG_S	sb
+#else
+#error "Please define DEBUG_LL_UART_IOSIZE{8,32}"
+#endif
+
+#ifndef __ASSEMBLY__
+/*
+ * C macros
+ */
+
+#include <asm/io.h>
+
+static inline void PUTC_LL(char ch)
+{
+#ifdef CONFIG_DEBUG_LL
+	while (!(__raw_readl((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
+		;
+	__raw_writel(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
+#endif /* CONFIG_DEBUG_LL */
+}
+
+static inline void debug_ll_ns16550_init(void)
+{
+#ifdef CONFIG_DEBUG_LL
+	__raw_writel(UART_LCR_DLAB, (u8 *)DEBUG_LL_UART_ADDR + UART_LCR);
+	__raw_writel(DEBUG_LL_UART_DIVISOR & 0xff, (u8 *)DEBUG_LL_UART_ADDR + UART_DLL);
+	__raw_writel((DEBUG_LL_UART_DIVISOR >> 8) & 0xff, (u8 *)DEBUG_LL_UART_ADDR + UART_DLM);
+	__raw_writel(UART_LCR_W, (u8 *)DEBUG_LL_UART_ADDR + UART_LCR);
+#endif /* CONFIG_DEBUG_LL */
+}
+#else /* __ASSEMBLY__ */
+/*
+ * Macros for use in assembly language code
+ */
+
+.macro	debug_ll_ns16550_init
+#ifdef CONFIG_DEBUG_LL
+	li	t0, DEBUG_LL_UART_ADDR
+
+	li	t1, UART_LCR_DLAB		/* DLAB on */
+	UART_REG_S	t1, UART_LCR(t0)		/* Write it out */
+
+	li	t1, DEBUG_LL_UART_DIVISOR
+	UART_REG_S	t1, UART_DLL(t0)		/* write low order byte */
+	srl	t1, t1, 8
+	UART_REG_S	t1, UART_DLM(t0)		/* write high order byte */
+
+	li	t1, UART_LCR_W			/* DLAB off */
+	UART_REG_S	t1, UART_LCR(t0)		/* Write it out */
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output a character in a0
+ */
+.macro	debug_ll_outc_a0
+#ifdef CONFIG_DEBUG_LL
+
+	li	t0, DEBUG_LL_UART_ADDR
+
+201:
+	UART_REG_L	t1, UART_LSR(t0)	/* get line status */
+	andi	t1, t1, UART_LSR_THRE	/* check for transmitter empty */
+	beqz	t1, 201b			/* try again */
+
+	UART_REG_S	a0, UART_THR(t0)	/* write the character */
+
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output a character
+ */
+.macro	debug_ll_outc chr
+#ifdef CONFIG_DEBUG_LL
+	li	a0, \chr
+	debug_ll_outc_a0
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output CR + NL
+ */
+.macro	debug_ll_ns16550_outnl
+#ifdef CONFIG_DEBUG_LL
+	debug_ll_outc '\r'
+	debug_ll_outc '\n'
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * check character in input buffer
+ * return value:
+ *  v0 = 0   no character in input buffer
+ *  v0 != 0  character in input buffer
+ */
+.macro	debug_ll_tstc
+#ifdef CONFIG_DEBUG_LL
+	li      t0, DEBUG_LL_UART_ADDR
+
+	/* get line status and check for data present */
+	UART_REG_L	s0, UART_LSR(t0)
+	andi	s0, s0, UART_LSR_DR
+
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * get character to v0
+ */
+.macro	debug_ll_getc
+#ifdef CONFIG_DEBUG_LL
+
+204:
+	debug_ll_tstc
+
+	/* try again */
+	beqz	s0, 204b
+
+	/* read a character */
+	UART_REG_L	s0, UART_RBR(t0)
+
+#endif /* CONFIG_DEBUG_LL */
+.endm
+#endif /* __ASSEMBLY__ */
+
+#endif /* __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ */
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#10 lore raw

PATCH v2 6/12 RISC-V: add nmon nano-monitor

In reply to Antony Pavlov

nmon is a tiny (<1024 bytes) monitor program
for the RV32I processors.

It can operate with NO working RAM at all!

It uses only the processor registers and NS16550-compatible UART port for operation, so it can be used for a memory controller setup code debugging.

---
 arch/riscv/Kconfig                  |  24 +++
 arch/riscv/boot/start.S             |   8 +
 arch/riscv/include/asm/riscv_nmon.h | 238 ++++++++++++++++++++++++++++
 3 files changed, 270 insertions(+)
arch/riscv/Kconfig +24 -0
index bcca385e14..d0e934e939 100644
@@ -64,6 +64,30 @@ source arch/riscv/mach-erizo/Kconfig
 
 endmenu
 
+menu "RISC-V specific settings"
+
+config HAS_NMON
+	bool
+
+config NMON
+	bool "nmon"
+	depends on HAS_NMON
+	depends on DEBUG_LL
+	help
+	  Say yes here to add the nmon to pbl.
+	  nmon -- nano-monitor program for the RISC-V processors.
+	  It can operate with NO working RAM, using only
+	  the processor registers.
+
+config NMON_HELP
+	bool "nmon help message"
+	depends on NMON
+	help
+	  Say yes here to get the nmon commands message on
+	  every nmon start.
+
+endmenu
+
 source common/Kconfig
 source commands/Kconfig
 source net/Kconfig
arch/riscv/boot/start.S +8 -0
index be3aed1507..de1f18fcb9 100644
@@ -21,12 +21,20 @@
 
 #include <asm-generic/memory_layout.h>
 
+#include "mach/debug_ll.h"
+
+#include "asm/riscv_nmon.h"
+
 	.text
 	.section ".text_entry"
 	.align 2
 
 .globl _start
 _start:
+	debug_ll_ns16550_init
+
+	riscv_nmon
+
 	li	sp, STACK_BASE + STACK_SIZE
 
 	/* copy barebox to link location */
arch/riscv/include/asm/riscv_nmon.h new file +238 -0

238 lines not on this page · raw message

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#11 lore raw

PATCH v2 7/12 RISC-V: erizo: add DEBUG_LL support

In reply to Antony Pavlov
---
 arch/riscv/Kconfig                            |  1 +
 arch/riscv/mach-erizo/include/mach/debug_ll.h | 37 +++++++++++++++++++
 2 files changed, 38 insertions(+)
arch/riscv/Kconfig +1 -0
index d0e934e939..f754aef05e 100644
@@ -21,6 +21,7 @@ choice
 
 config MACH_ERIZO
 	bool "erizo family"
+	select HAS_DEBUG_LL
 
 endchoice
 
arch/riscv/mach-erizo/include/mach/debug_ll.h new file +37 -0
new file mode 100644
index 0000000000..913b323d99
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2017 Antony Pavlov <[email protected]>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_ERIZO_DEBUG_LL__
+#define __MACH_ERIZO_DEBUG_LL__
+
+/** @file
+ *  This File contains declaration for early output support
+ */
+
+#include <linux/kconfig.h>
+
+#define DEBUG_LL_UART_ADDR	0x90000000
+#define DEBUG_LL_UART_SHIFT	2
+#define DEBUG_LL_UART_IOSIZE32
+
+#define DEBUG_LL_UART_CLK       (24000000 / 16)
+#define DEBUG_LL_UART_BPS       CONFIG_BAUDRATE
+#define DEBUG_LL_UART_DIVISOR   (DEBUG_LL_UART_CLK / DEBUG_LL_UART_BPS)
+
+#include <asm/debug_ll_ns16550.h>
+
+#endif /* __MACH_ERIZO_DEBUG_LL__ */
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#12 lore raw

PATCH v2 8/12 RISC-V: erizo: enable nmon

In reply to Antony Pavlov
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/riscv/Kconfig +1 -0
index f754aef05e..ff0d584761 100644
@@ -22,6 +22,7 @@ choice
 config MACH_ERIZO
 	bool "erizo family"
 	select HAS_DEBUG_LL
+	select HAS_NMON
 
 endchoice
 
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#13 lore raw

PATCH v2 9/12 RISC-V: erizo: add nmon image creation

In reply to Antony Pavlov
---
 arch/riscv/Makefile      | 11 +++++++++++
 scripts/erizo-nmon-image | 10 ++++++++++
 2 files changed, 21 insertions(+)
arch/riscv/Makefile +11 -0
index 9a3921065c..c837d4e2e4 100644
@@ -73,3 +73,14 @@ CFLAGS += $(cflags-y)
 lds-y	:= arch/riscv/lib/barebox.lds
 
 CLEAN_FILES += arch/riscv/lib/barebox.lds
+
+ifeq ($(CONFIG_MACH_ERIZO),y)
+KBUILD_IMAGE := barebox.erizo.nmon
+endif
+
+quiet_cmd_erizo_nmon_image = MKIMAGE $@
+      cmd_erizo_nmon_image = $(srctree)/scripts/erizo-nmon-image $< $@ || \
+	echo "WARNING: Couldn't create erizo nmon image due to previous errors."
+
+barebox.erizo.nmon: $(KBUILD_BINARY) FORCE
+	$(call if_changed,erizo_nmon_image)
scripts/erizo-nmon-image new file +10 -0
new file mode 100755
index 0000000000..b56fd365c6
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ $# != 2 ]; then
+	echo "Usage:"
+	echo "  erizo-nmon-image <input-binary-file> <output-expect-file>"
+
+	exit 1
+fi
+
+hexdump -v -e '/4 "%08x\n"' $1 | perl -e '$a = 0x80000000; while (<>) { chop; printf("expect \"nmon> \"\n"); printf("send \"w%08x$_\"\n", $a); $a = $a + 4; }' > $2
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#14 lore raw

PATCH v2 10/12 RISC-V: add erizo_generic_defconfig

In reply to Antony Pavlov
---
 arch/riscv/configs/erizo_generic_defconfig | 53 ++++++++++++++++++++++
 1 file changed, 53 insertions(+)
arch/riscv/configs/erizo_generic_defconfig new file +53 -0
new file mode 100644
index 0000000000..e62b6ec719
@@ -0,0 +1,53 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="erizo_generic"
+# CONFIG_GLOBALVAR is not set
+CONFIG_TEXT_BASE=0x80000000
+CONFIG_MEMORY_LAYOUT_FIXED=y
+CONFIG_STACK_BASE=0x800e0000
+CONFIG_STACK_SIZE=0x20000
+CONFIG_MALLOC_BASE=0x80100000
+CONFIG_MALLOC_SIZE=0x100000
+CONFIG_MALLOC_TLSF=y
+CONFIG_PANIC_HANG=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_TIMESTAMP is not set
+# CONFIG_BOOTM is not set
+# CONFIG_ENV_HANDLING is not set
+CONFIG_POLLER=y
+CONFIG_DEBUG_LL=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_CMP=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_OF_DUMP=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_OFDEVICE=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SPI_GPIO=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
+CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_MTD_M25P80=y
+CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
+CONFIG_EEPROM_AT24=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_PINCTRL is not set
+CONFIG_DIGEST_CRC32_GENERIC=y
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#15 lore raw

PATCH v2 11/12 scripts: add nmon-loader

In reply to Antony Pavlov
---
 scripts/nmon-loader | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
scripts/nmon-loader new file +31 -0
new file mode 100755
index 0000000000..d80a53097a
@@ -0,0 +1,31 @@
+#!/usr/bin/expect -f
+
+# device
+set image [lindex $argv 0];
+set modem [lindex $argv 1];
+set speed [lindex $argv 2];
+
+if {$argc != 3} {
+    puts "Usage:"
+    puts "    nmon-loader.expect <file> <device> <speed>"
+    exit 2
+}
+
+# keep it open
+exec sh -c "sleep 3 < $modem" &
+
+# serial port parameters
+exec stty -F $modem $speed raw -clocal -echo -istrip -hup
+
+# connect
+send_user "connecting to $modem, exit with ~.\n"
+spawn -open [open $modem w+]
+send_user "connected\n"
+send "\r"
+
+source $image
+
+interact {
+    ~- exit
+    ~~ {send "\034"}
+}
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#16 lore raw

PATCH v2 12/12 Documentation: add RISC-V docs

In reply to Antony Pavlov
---
 Documentation/boards/riscv.rst | 91 ++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)
Documentation/boards/riscv.rst new file +91 -0
new file mode 100644
index 0000000000..1a51d4d44f
@@ -0,0 +1,91 @@
+RISC-V
+======
+
+Running RISC-V barebox on qemu
+------------------------------
+
+Obtain RISC-V GCC/Newlib Toolchain,
+see https://github.com/riscv/riscv-tools/blob/master/README.md
+for details. The ``build.sh`` script from ``riscv-tools`` should
+create toolchain.
+
+Next compile qemu emulator::
+
+  $ git clone -b 20180409.erizo https://github.com/miet-riscv-workgroup/riscv-qemu
+  $ cd riscv-qemu
+  $ cap="no" ./configure \
+    --extra-cflags="-Wno-maybe-uninitialized" \
+    --audio-drv-list="" \
+    --disable-attr \
+    --disable-blobs \
+    --disable-bluez \
+    --disable-brlapi \
+    --disable-curl \
+    --disable-curses \
+    --disable-docs \
+    --disable-kvm \
+    --disable-spice \
+    --disable-sdl \
+    --disable-vde \
+    --disable-vnc-sasl \
+    --disable-werror \
+    --enable-trace-backend=simple \
+    --disable-stack-protector \
+    --target-list=riscv32-softmmu,riscv64-softmmu
+  $ make
+
+
+Next compile barebox::
+
+  $ make erizo_generic_defconfig ARCH=riscv
+  ...
+  $ make ARCH=riscv CROSS_COMPILE=<path to your riscv toolchain>/riscv32-unknown-elf-
+
+Run barebox::
+
+  $ <path to riscv-qemu source>/riscv32-softmmu/qemu-system-riscv32 \
+      -nographic -M erizo -bios <path to barebox sources >/barebox.bin \
+      -serial stdio -monitor none -trace file=/dev/null
+  Switch to console [cs0]
+  
+  
+  barebox 2018.06.0-00157-g3f41f41593 #0 Thu Jun 17 11:40:43 MSK 2018
+  
+  
+  Board: generic Erizo SoC board
+  malloc space: 0x80100000 -> 0x801fffff (size 1 MiB)
+  running /env/bin/init...
+  /env/bin/init not found
+  barebox:/
+
+
+Running RISC-V barebox on DE0-Nano FPGA board
+---------------------------------------------
+
+See https://github.com/open-design/riscv-soc-cores/ for instructions
+on DE0-Nano bitstream generation and loading.
+
+Connect to board's UART with your favorite serial communication software
+(e.g. minicom) and check 'nmon> ' prompt (nmon runs from onchip ROM).
+
+Next close your communication software and use ./scripts/nmon-loader
+to load barebox image into board's DRAM, e.g.
+
+  # ./scripts/nmon-loader barebox.erizo.nmon /dev/ttyUSB0 115200
+
+Wait several munutes for 'nmon> ' prompt.
+
+Next, start barebox from DRAM:
+
+  nmon> g 80000000
+  Switch to console [cs0]
+  
+  
+  barebox 2018.06.0-00157-g3f41f41593 #0 Thu Jun 17 11:40:43 MSK 2018
+  
+  
+  Board: generic Erizo SoC board
+  malloc space: 0x80100000 -> 0x801fffff (size 1 MiB)
+  running /env/bin/init...
+  /env/bin/init not found
+  barebox:/ 
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#17 lore raw
In reply to Antony Pavlov

Hi Antony,

Quoted 3 lines · Antony Pavlov

This patchseries adds initial RISC-V architecture support for barebox.

See Documentation/boards/riscv.rst for instructions.

Applied patches 1 and 2 for now. The rest looks mostly fine except for the two suggestions I made for patch 3.

Sascha

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