sunxi: Fix USB PHY index for H3 (missed chage)

PATCH New Jagan Teki 3 participants 4 messages Jun 28, 2018 – Jun 29, 2018

Subsystems (5)

Arm (32-bit) USB Arm/Allwinner sunXi SoC support USB ehci driver +1 more subsystems

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Jagan Teki

author

2018-06-28 14:10 UTC #0 lore raw

PATCH 1/2 sunxi: Fix USB PHY index for H3 (missed chage)

This patch update the USB PHY index for Allwinner H3.

Same change[1] initially sent, by 'Chen-Yu Tai' but missed to apply due to recursive version changes on the same series.

[1] https://lists.denx.de/pipermail/u-boot/2018-January/318817.html

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +7 -3

index 8afeaf872e..3a59016955 100644
@@ -275,9 +275,13 @@ struct sunxi_ccm_reg {
  * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
  * them 0 - 2 like they were called on older SoCs.
  */
+#define AHB_GATE_OFFSET_USB_OHCI3	31
+#define AHB_GATE_OFFSET_USB_OHCI2	30
+#define AHB_GATE_OFFSET_USB_OHCI1	29
 #define AHB_GATE_OFFSET_USB_OHCI0	28
-#define AHB_GATE_OFFSET_USB_EHCI2	27
-#define AHB_GATE_OFFSET_USB_EHCI1	26
+#define AHB_GATE_OFFSET_USB_EHCI3	27
+#define AHB_GATE_OFFSET_USB_EHCI2	26
+#define AHB_GATE_OFFSET_USB_EHCI1	25
 #define AHB_GATE_OFFSET_USB_EHCI0	24
 #elif defined(CONFIG_MACH_SUN50I)
 #define AHB_GATE_OFFSET_USB_OHCI0	28

@@ -290,7 +294,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
 #endif
-#ifdef CONFIG_MACH_SUN50I
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5)
 #define AHB_GATE_OFFSET_USB0		23
 #elif !defined(CONFIG_MACH_SUN8I_R40)
 #define AHB_GATE_OFFSET_USB0		24

Signature · 1 line

2.17.1

Jagan Teki

author

2018-06-28 14:10 UTC #1 lore raw

PATCH 2/2 usb: sunxi: Use proper reg_mask for clock gate, reset

Masking clock gate, reset register bits based on the probed controller is proper only due to the assumption that masking should start with 0 even thought the controller has separate PHY or shared between OTG.

unfortunately these are fixed due to lack of separate clock, reset drivers.

Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) so we need to start reg_mask 0 - 2.

This patch calculated the mask, based on the register base so that we can get the proper bits to set with respect to probed controller.

We even do this masking by using PHY index specifier from dt, but dev_read_addr_size is failing for 64-bit boards.

Signed-off-by Jagan Teki <[email protected]>

---
Note:
This is another version[1] via dt pharsing, but dev_read_addr_size failed in 64-bit boards.
[1] https://paste.ubuntu.com/p/YRtJT4kzc3/

 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  9 +++++----
 drivers/usb/host/ehci-sunxi.c               |  8 ++++++--
 drivers/usb/host/ohci-sunxi.c               | 10 +++++++---
 3 files changed, 18 insertions(+), 9 deletions(-)

arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +5 -4

index ee648366c7..02ce73954d 100644
@@ -63,10 +63,11 @@
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 #define SUNXI_USBPHY_BASE		0x01c19000
-#define SUNXI_USB0_BASE			0x01c1a000
-#define SUNXI_USB1_BASE			0x01c1b000
-#define SUNXI_USB2_BASE			0x01c1c000
-#define SUNXI_USB3_BASE			0x01c1d000
+#define SUNXI_USB0_BASE			SUNXI_USBPHY_BASE
+#define SUNXI_USB1_BASE			0x01c1a000
+#define SUNXI_USB2_BASE			0x01c1b000
+#define SUNXI_USB3_BASE			0x01c1c000
+#define SUNXI_USB4_BASE			0x01c1d000
 #else
 #define SUNXI_USB0_BASE			0x01c19000
 #define SUNXI_USB1_BASE			0x01c1a000

drivers/usb/host/ehci-sunxi.c +6 -2

index 97d06d5975..7a79931a97 100644
@@ -17,8 +17,10 @@
 #include <generic-phy.h>
 
 #ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST		0x8000
 #define AHB_CLK_DIST		2
 #else
+#define BASE_DIST		0x1000
 #define AHB_CLK_DIST		1
 #endif

@@ -47,6 +49,7 @@ static int ehci_usb_probe(struct udevice *dev)
 	struct ehci_hccr *hccr = (struct ehci_hccr *)devfdt_get_addr(dev);
 	struct ehci_hcor *hcor;
 	int extra_ahb_gate_mask = 0;
+	u8 reg_mask = 0;
 	int phys, ret;
 
 	priv->cfg = (const struct ehci_sunxi_cfg *)dev_get_driver_data(dev);

@@ -86,10 +89,11 @@ no_phy:
 	 * This should go away once we've moved to the driver model for
 	 * clocks resp. phys.
 	 */
+	reg_mask = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
 	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 	extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask;
-	priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
-	extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
+	priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST;
+	extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST;
 
 	setbits_le32(&priv->ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);

drivers/usb/host/ohci-sunxi.c +7 -3

index db6f438275..0ddbdbe460 100644
@@ -17,8 +17,10 @@
 #include <generic-phy.h>
 
 #ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST		0x8000
 #define AHB_CLK_DIST		2
 #else
+#define BASE_DIST		0x1000
 #define AHB_CLK_DIST		1
 #endif

@@ -48,6 +50,7 @@ static int ohci_usb_probe(struct udevice *dev)
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
 	int extra_ahb_gate_mask = 0;
+	u8 reg_mask = 0;
 	int phys, ret;
 
 	priv->cfg = (const struct ohci_sunxi_cfg *)dev_get_driver_data(dev);

@@ -89,12 +92,13 @@ no_phy:
 	 * This should go away once we've moved to the driver model for
 	 * clocks resp. phys.
 	 */
+	reg_mask = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
 	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
 	extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask;
 	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
-	priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
-	extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
-	priv->usb_gate_mask <<= phys;
+	priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST;
+	extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST;
+	priv->usb_gate_mask <<= reg_mask;
 
 	setbits_le32(&priv->ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);

Signature · 1 line

2.17.1

Adam Sampson

2018-06-28 18:52 UTC #2 lore raw

PATCH 2/2 usb: sunxi: Use proper reg_mask for clock gate, reset

Quoted 2 lines · Jagan Teki

Masking clock gate, reset register bits based on the probed controller is proper only due to the assumption [...]

With this patch, both USB ports work correctly on Cubieboard (A10) and pcDuino3 Nano (A20). Thanks for the quick fix!

Tested-by Adam Sampson <[email protected]>

Signature · 1 line

Adam Sampson <[email protected]>                         <http://offog.org/>

Marek Vasut

2018-06-29 08:54 UTC #3 lore raw

PATCH 2/2 usb: sunxi: Use proper reg_mask for clock gate, reset

In reply to Jagan Teki

Quoted 11 lines · Jagan Teki

Masking clock gate, reset register bits based on the probed controller is proper only due to the assumption that masking should start with 0 even thought the controller has separate PHY or shared between OTG.
unfortunately these are fixed due to lack of separate clock, reset drivers.
Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) so we need to start reg_mask 0 - 2.

Quoted 8 lines

This patch calculated the mask, based on the register base so that we can get the proper bits to set with respect to probed controller.
We even do this masking by using PHY index specifier from dt, but dev_read_addr_size is failing for 64-bit boards.
Signed-off-by Jagan Teki <[email protected]>

Applied both

Signature · 2 lines

Best regards,
Marek Vasut