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Building for 32-bit RISC-V kernel

PATCH In review Zong Li 4 participants 15 messages Jun 25, 2018 – Jul 5, 2018

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Zong Li

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#0 lore raw

v2 cover Building for 32-bit RISC-V kernel

These patches for building 32-bit RISC-V kernel.
- Fix the compile errors and warnings on RV32I.
- Fix some incompatible problem on RV32I.
- Add format.h for compatible of print format.

The fixed width integer types format for Elf_Addr will move to generic header by another patch. For now, there are some warning about unexpected argument of type on RV32I.

Change in v1:
- Fix some error in v1
- Remove implementation of fixed width integer types format for Elf_Addr.

Zong Li (4):
RISC-V: Add conditional macro for zone of DMA32
RISC-V: Select GENERIC_UCMPDI2 on RV32I
RISC-V: Add definiion of extract symbol's index and type for 32-bit
RISC-V: Change variable type for 32-bit compatible

 arch/riscv/Kconfig                |  1 +
 arch/riscv/include/uapi/asm/elf.h |  9 +++++++--
 arch/riscv/kernel/module.c        | 22 +++++++++++-----------
 arch/riscv/mm/init.c              |  2 ++
 4 files changed, 21 insertions(+), 13 deletions(-)
Signature · 1 line
2.16.1
author
#1 lore raw

PATCH v2 1/4 RISC-V: Add conditional macro for zone of DMA32

The DMA32 is for 64-bit usage.

Signed-off-by Zong Li <[email protected]>
---
 arch/riscv/mm/init.c | 2 ++
 1 file changed, 2 insertions(+)
arch/riscv/mm/init.c +2 -0
index c77df8142be2..58a522f9bcc3 100644
@@ -28,7 +28,9 @@ static void __init zone_sizes_init(void)
 {
 	unsigned long max_zone_pfns[MAX_NR_ZONES] = { 0, };
 
+#ifdef CONFIG_ZONE_DMA32
 	max_zone_pfns[ZONE_DMA32] = PFN_DOWN(min(4UL * SZ_1G, max_low_pfn));
+#endif
 	max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
 
 	free_area_init_nodes(max_zone_pfns);
Signature · 1 line
2.16.1
author
#3 lore raw

PATCH v2 2/4 RISC-V: Select GENERIC_UCMPDI2 on RV32I

In reply to Zong Li

On 32-bit, it need to use __ucmpdi2, otherwise, it can't find the __ucmpdi2 symbol.

Signed-off-by Zong Li <[email protected]>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/riscv/Kconfig +1 -0
index 6debcc4afc72..3e683be9b7a8 100644
@@ -122,6 +122,7 @@ config ARCH_RV32I
 	select GENERIC_ASHLDI3
 	select GENERIC_ASHRDI3
 	select GENERIC_LSHRDI3
+	select GENERIC_UCMPDI2
 
 config ARCH_RV64I
 	bool "RV64I"
Signature · 1 line
2.16.1
author
#5 lore raw

PATCH v2 3/4 RISC-V: Add definiion of extract symbol's index and type for 32-bit

In reply to Zong Li

Use generic marco to get the index and type of symbol.

Signed-off-by Zong Li <[email protected]>
---
 arch/riscv/include/uapi/asm/elf.h | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
arch/riscv/include/uapi/asm/elf.h +7 -2
index 5cae4c30cd8e..1e0dfc36aab9 100644
@@ -21,8 +21,13 @@ typedef struct user_regs_struct elf_gregset_t;
 
 typedef union __riscv_fp_state elf_fpregset_t;
 
-#define ELF_RISCV_R_SYM(r_info) ((r_info) >> 32)
-#define ELF_RISCV_R_TYPE(r_info) ((r_info) & 0xffffffff)
+#if __riscv_xlen == 64
+#define ELF_RISCV_R_SYM(r_info)		ELF64_R_SYM(r_info)
+#define ELF_RISCV_R_TYPE(r_info)	ELF64_R_TYPE(r_info)
+#else
+#define ELF_RISCV_R_SYM(r_info)		ELF32_R_SYM(r_info)
+#define ELF_RISCV_R_TYPE(r_info)	ELF32_R_TYPE(r_info)
+#endif
 
 /*
  * RISC-V relocation types
Signature · 1 line
2.16.1
#6 lore raw

Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit

Quoted 1 line · Zong Li

Use generic marco to get the index and type of symbol.

Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM and ELF_RISCV_R_TYPE move to module.c? In that case we could just use CONFIG_64BIT.

#7 lore raw

Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit

Christoph Hellwig <[email protected]> ? 2018?6?29? ?? ??3:12???

Quoted 7 lines · Zong Li
Quoted 1 line

Use generic marco to get the index and type of symbol.

Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM and ELF_RISCV_R_TYPE move to module.c? In that case we could just use CONFIG_64BIT.

Make sense. I even think the all definitions can be move to include/asm/elf.h. How do you think about that?

#8 lore raw

Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit

Quoted 11 lines · zongbox at gmail.com

Christoph Hellwig <[email protected]> ? 2018?6?29? ?? ??3:12???

Quoted 7 lines · Zong Li
Quoted 1 line

Use generic marco to get the index and type of symbol.

Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM and ELF_RISCV_R_TYPE move to module.c? In that case we could just use CONFIG_64BIT.

Make sense. I even think the all definitions can be move to include/asm/elf.h. How do you think about that?

Sorry I've been slow about reviewing this, but I think just in the interest of getting a sane RV32I port up and running quickly (so we can try to get glibc in shape) I'm going to take this for now.

Do you mind submitting a cleanup patch?

#9 lore raw

Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit

Palmer Dabbelt <[email protected]> ? 2018?7?5? ?? ??4:58???

Quoted 11 lines · zongbox at gmail.com
Quoted 9 lines

Christoph Hellwig <[email protected]> ? 2018?6?29? ?? ??3:12???

Quoted 7 lines · Zong Li
Quoted 1 line

Use generic marco to get the index and type of symbol.

Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM and ELF_RISCV_R_TYPE move to module.c? In that case we could just use CONFIG_64BIT.

Quoted 8 lines
Quoted 2 lines

Make sense. I even think the all definitions can be move to include/asm/elf.h. How do you think about that?

Sorry I've been slow about reviewing this, but I think just in the interest of getting a sane RV32I port up and running quickly (so we can try to get glibc in shape) I'm going to take this for now.

Do you mind submitting a cleanup patch?

I will send a patch to clean up. Thanks everyone to review this patchset.

#10 lore raw

Re: [PATCH v2 3/4] RISC-V: Add definiion of extract symbol's index and type for 32-bit

Quoted 15 lines · zongbox at gmail.com

Palmer Dabbelt <[email protected]> ? 2018?7?5? ?? ??4:58???

Quoted 14 lines · zongbox at gmail.com
Quoted 11 lines

Christoph Hellwig <[email protected]> ? 2018?6?29? ?? ??3:12???

Quoted 7 lines · Zong Li
Quoted 1 line

Use generic marco to get the index and type of symbol.

Why do we even need this in a uapi header? Shouldn't ELF_RISCV_R_SYM and ELF_RISCV_R_TYPE move to module.c? In that case we could just use CONFIG_64BIT.

Make sense. I even think the all definitions can be move to include/asm/elf.h. How do you think about that?

Quoted 7 lines
Quoted 5 lines

Sorry I've been slow about reviewing this, but I think just in the interest of getting a sane RV32I port up and running quickly (so we can try to get glibc in shape) I'm going to take this for now.

Do you mind submitting a cleanup patch?

I will send a patch to clean up. Thanks everyone to review this patchset.

Well, thanks for doing the work :).

author
#11 lore raw

PATCH v2 4/4 RISC-V: Change variable type for 32-bit compatible

In reply to Zong Li
Signed-off-by Zong Li <[email protected]>
---
 arch/riscv/kernel/module.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)
arch/riscv/kernel/module.c +11 -11
index 29d265d0cf45..a346e0921995 100644
@@ -39,7 +39,7 @@ static int apply_r_riscv_64_rela(struct module *me, u32 *location, Elf_Addr v)
 static int apply_r_riscv_branch_rela(struct module *me, u32 *location,
 				     Elf_Addr v)
 {
-	s64 offset = (void *)v - (void *)location;
+	ptrdiff_t offset = (void *)v - (void *)location;
 	u32 imm12 = (offset & 0x1000) << (31 - 12);
 	u32 imm11 = (offset & 0x800) >> (11 - 7);
 	u32 imm10_5 = (offset & 0x7e0) << (30 - 10);

@@ -52,7 +52,7 @@ static int apply_r_riscv_branch_rela(struct module *me, u32 *location,
 static int apply_r_riscv_jal_rela(struct module *me, u32 *location,
 				  Elf_Addr v)
 {
-	s64 offset = (void *)v - (void *)location;
+	ptrdiff_t offset = (void *)v - (void *)location;
 	u32 imm20 = (offset & 0x100000) << (31 - 20);
 	u32 imm19_12 = (offset & 0xff000);
 	u32 imm11 = (offset & 0x800) << (20 - 11);

@@ -65,7 +65,7 @@ static int apply_r_riscv_jal_rela(struct module *me, u32 *location,
 static int apply_r_riscv_rcv_branch_rela(struct module *me, u32 *location,
 					 Elf_Addr v)
 {
-	s64 offset = (void *)v - (void *)location;
+	ptrdiff_t offset = (void *)v - (void *)location;
 	u16 imm8 = (offset & 0x100) << (12 - 8);
 	u16 imm7_6 = (offset & 0xc0) >> (6 - 5);
 	u16 imm5 = (offset & 0x20) >> (5 - 2);

@@ -80,7 +80,7 @@ static int apply_r_riscv_rcv_branch_rela(struct module *me, u32 *location,
 static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location,
 				       Elf_Addr v)
 {
-	s64 offset = (void *)v - (void *)location;
+	ptrdiff_t offset = (void *)v - (void *)location;
 	u16 imm11 = (offset & 0x800) << (12 - 11);
 	u16 imm10 = (offset & 0x400) >> (10 - 8);
 	u16 imm9_8 = (offset & 0x300) << (12 - 11);

@@ -98,7 +98,7 @@ static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location,
 static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location,
 					 Elf_Addr v)
 {
-	s64 offset = (void *)v - (void *)location;
+	ptrdiff_t offset = (void *)v - (void *)location;
 	s32 hi20;
 
 	if (offset != (s32)offset) {

@@ -180,7 +180,7 @@ static int apply_r_riscv_lo12_s_rela(struct module *me, u32 *location,
 static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location,
 				       Elf_Addr v)
 {
-	s64 offset = (void *)v - (void *)location;
+	ptrdiff_t offset = (void *)v - (void *)location;
 	s32 hi20;
 
 	/* Always emit the got entry */

@@ -202,7 +202,7 @@ static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location,
 static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location,
 				       Elf_Addr v)
 {
-	s64 offset = (void *)v - (void *)location;
+	ptrdiff_t offset = (void *)v - (void *)location;
 	s32 fill_v = offset;
 	u32 hi20, lo12;
 

@@ -229,7 +229,7 @@ static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location,
 static int apply_r_riscv_call_rela(struct module *me, u32 *location,
 				   Elf_Addr v)
 {
-	s64 offset = (void *)v - (void *)location;
+	ptrdiff_t offset = (void *)v - (void *)location;
 	s32 fill_v = offset;
 	u32 hi20, lo12;
 

@@ -349,7 +349,7 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
 			unsigned int j;
 
 			for (j = 0; j < sechdrs[relsec].sh_size / sizeof(*rel); j++) {
-				u64 hi20_loc =
+				unsigned long hi20_loc =
 					sechdrs[sechdrs[relsec].sh_info].sh_addr
 					+ rel[j].r_offset;
 				u32 hi20_type = ELF_RISCV_R_TYPE(rel[j].r_info);

@@ -362,12 +362,12 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
 					Elf_Sym *hi20_sym =
 						(Elf_Sym *)sechdrs[symindex].sh_addr
 						+ ELF_RISCV_R_SYM(rel[j].r_info);
-					u64 hi20_sym_val =
+					unsigned long hi20_sym_val =
 						hi20_sym->st_value
 						+ rel[j].r_addend;
 
 					/* Calculate lo12 */
-					u64 offset = hi20_sym_val - hi20_loc;
+					size_t offset = hi20_sym_val - hi20_loc;
 					if (IS_ENABLED(CONFIG_MODULE_SECTIONS)
 					    && hi20_type == R_RISCV_GOT_HI20) {
 						offset = module_emit_got_entry(
Signature · 1 line
2.16.1
#14 lore raw

Christoph Hellwig <[email protected]> ? 2018?6?29? ?? ??3:23???

Quoted 4 lines

Btw, what kind of userspace do you use for riscv32? Do you have an easy to use root file system available somewhere (or a way to build one)?

I'm porting 32 bit riscv glibc now, and it is almost completion but still has few fail cases of glibc testsuite.
I built the root file system consist of busybox, bash and dropbear and so on. I can push the
rootfs I used or a build script to github if somebody need it.