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dt-bindings: tegra186-gpio: Add information for Tegra194

PATCH New Mikko Perttunen 4 participants 13 messages Jun 20, 2018 – Jul 2, 2018

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#0 lore raw

PATCH 1/5 dt-bindings: tegra186-gpio: Add information for Tegra194

The Tegra194 GPIO controller is similar to the one in Tegra186. Add relevant information to the device tree binding documentation.

---
 Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt | 4 ++++
 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt +4 -0
index c82a2e221bc1..adff16c71d21 100644
@@ -68,6 +68,8 @@ Required properties:
     One of:
     - "nvidia,tegra186-gpio".
     - "nvidia,tegra186-gpio-aon".
+    - "nvidia,tegra194-gpio".
+    - "nvidia,tegra194-gpio-aon".
 - reg-names
     Array of strings.
     Contains a list of names for the register spaces described by the reg
@@ -91,6 +93,8 @@ Required properties:
     depending on compatible value:
     - "nvidia,tegra186-gpio": 6 entries.
     - "nvidia,tegra186-gpio-aon": 1 entry.
+    - "nvidia,tegra194-gpio": 6 entries.
+    - "nvidia,tegra194-gpio-aon": 1 entry.
 - gpio-controller
     Boolean.
     Marks the device node as a GPIO controller/provider.
Signature · 1 line
2.16.1
#1 lore raw

PATCH 2/5 gpio: tegra186: Add support for Tegra194

Add support for the Tegra194 GPIO bank configuration.

---
 drivers/gpio/gpio-tegra186.c | 74 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
drivers/gpio/gpio-tegra186.c +74 -0
index 7f1aa4c21e0d..9d0292c8a199 100644
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 
 #include <dt-bindings/gpio/tegra186-gpio.h>
+#include <dt-bindings/gpio/tegra194-gpio.h>
 
 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
 #define  TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
@@ -593,6 +594,73 @@ static const struct tegra_gpio_soc tegra186_aon_soc = {
 	.name = "tegra186-gpio-aon",
 };
 
+#define TEGRA194_MAIN_GPIO_PORT(port, base, count, controller)	\
+	[TEGRA194_MAIN_GPIO_PORT_##port] = {			\
+		.name = #port,					\
+		.offset = base,					\
+		.pins = count,					\
+		.irq = controller,				\
+	}
+
+static const struct tegra_gpio_port tegra194_main_ports[] = {
+	TEGRA194_MAIN_GPIO_PORT( A, 0x1400, 8, 1),
+	TEGRA194_MAIN_GPIO_PORT( B, 0x4e00, 2, 4),
+	TEGRA194_MAIN_GPIO_PORT( C, 0x4600, 8, 4),
+	TEGRA194_MAIN_GPIO_PORT( D, 0x4800, 4, 4),
+	TEGRA194_MAIN_GPIO_PORT( E, 0x4a00, 8, 4),
+	TEGRA194_MAIN_GPIO_PORT( F, 0x4c00, 6, 4),
+	TEGRA194_MAIN_GPIO_PORT( G, 0x4000, 8, 4),
+	TEGRA194_MAIN_GPIO_PORT( H, 0x4200, 8, 4),
+	TEGRA194_MAIN_GPIO_PORT( I, 0x4400, 5, 4),
+	TEGRA194_MAIN_GPIO_PORT( J, 0x5200, 6, 5),
+	TEGRA194_MAIN_GPIO_PORT( K, 0x3000, 8, 3),
+	TEGRA194_MAIN_GPIO_PORT( L, 0x3200, 4, 3),
+	TEGRA194_MAIN_GPIO_PORT( M, 0x2600, 8, 2),
+	TEGRA194_MAIN_GPIO_PORT( N, 0x2800, 3, 2),
+	TEGRA194_MAIN_GPIO_PORT( O, 0x5000, 6, 5),
+	TEGRA194_MAIN_GPIO_PORT( P, 0x2a00, 8, 2),
+	TEGRA194_MAIN_GPIO_PORT( Q, 0x2c00, 8, 2),
+	TEGRA194_MAIN_GPIO_PORT( R, 0x2e00, 6, 2),
+	TEGRA194_MAIN_GPIO_PORT( S, 0x3600, 8, 3),
+	TEGRA194_MAIN_GPIO_PORT( T, 0x3800, 8, 3),
+	TEGRA194_MAIN_GPIO_PORT( U, 0x3a00, 1, 3),
+	TEGRA194_MAIN_GPIO_PORT( V, 0x1000, 8, 1),
+	TEGRA194_MAIN_GPIO_PORT( W, 0x1200, 2, 1),
+	TEGRA194_MAIN_GPIO_PORT( X, 0x2000, 8, 2),
+	TEGRA194_MAIN_GPIO_PORT( Y, 0x2200, 8, 2),
+	TEGRA194_MAIN_GPIO_PORT( Z, 0x2400, 8, 2),
+	TEGRA194_MAIN_GPIO_PORT(FF, 0x3400, 2, 3),
+	TEGRA194_MAIN_GPIO_PORT(GG, 0x0000, 2, 0)
+};
+
+static const struct tegra_gpio_soc tegra194_main_soc = {
+	.num_ports = ARRAY_SIZE(tegra194_main_ports),
+	.ports = tegra194_main_ports,
+	.name = "tegra194-gpio",
+};
+
+#define TEGRA194_AON_GPIO_PORT(port, base, count, controller)	\
+	[TEGRA194_AON_GPIO_PORT_##port] = {			\
+		.name = #port,					\
+		.offset = base,					\
+		.pins = count,					\
+		.irq = controller,				\
+	}
+
+static const struct tegra_gpio_port tegra194_aon_ports[] = {
+	TEGRA194_AON_GPIO_PORT(AA, 0x0600, 8, 0),
+	TEGRA194_AON_GPIO_PORT(BB, 0x0800, 4, 0),
+	TEGRA194_AON_GPIO_PORT(CC, 0x0200, 8, 0),
+	TEGRA194_AON_GPIO_PORT(DD, 0x0400, 3, 0),
+	TEGRA194_AON_GPIO_PORT(EE, 0x0000, 7, 0)
+};
+
+static const struct tegra_gpio_soc tegra194_aon_soc = {
+	.num_ports = ARRAY_SIZE(tegra194_aon_ports),
+	.ports = tegra194_aon_ports,
+	.name = "tegra194-gpio-aon",
+};
+
 static const struct of_device_id tegra186_gpio_of_match[] = {
 	{
 		.compatible = "nvidia,tegra186-gpio",
@@ -600,6 +668,12 @@ static const struct of_device_id tegra186_gpio_of_match[] = {
 	}, {
 		.compatible = "nvidia,tegra186-gpio-aon",
 		.data = &tegra186_aon_soc
+	}, {
+		.compatible = "nvidia,tegra194-gpio",
+		.data = &tegra194_main_soc
+	}, {
+		.compatible = "nvidia,tegra194-gpio-aon",
+		.data = &tegra194_aon_soc
 	}, {
 		/* sentinel */
 	}
Signature · 1 line
2.16.1
#2 lore raw

PATCH 2/5 gpio: tegra186: Add support for Tegra194

Quoted 3 lines · Mikko Perttunen

Add support for the Tegra194 GPIO bank configuration.

Patch applied as pretty straight forward.
I don't think Thierry would mind, in worst case I can revert it.

Yours,
Linus Walleij

#3 lore raw

PATCH 2/5 gpio: tegra186: Add support for Tegra194

Quoted 9 lines · Linus Walleij
Quoted 3 lines · Mikko Perttunen

Add support for the Tegra194 GPIO bank configuration.

Patch applied as pretty straight forward.
I don't think Thierry would mind, in worst case I can revert it.

Sorry for not getting back sooner, I was out sick last week. I don't mind at all, so for what it's worth:

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#4 lore raw

PATCH 3/5 arm64: tegra: Add GPIO controller on Tegra194

In reply to Mikko Perttunen

Add the device tree node for the GPIO controller on Tegra194.

---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
arch/arm64/boot/dts/nvidia/tegra194.dtsi +17 -0
index d7f780b06fe2..abe2d688eb65 100644
@@ -18,6 +18,23 @@
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x0 0x40000000>;
 
+		gpio: gpio at 2200000 {
+			compatible = "nvidia,tegra194-gpio";
+			reg-names = "security", "gpio";
+			reg = <0x2200000 0x10000>,
+			      <0x2210000 0x10000>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			#gpio-cells = <2>;
+			gpio-controller;
+		};
+
 		uarta: serial at 3100000 {
 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 			reg = <0x03100000 0x40>;
Signature · 1 line
2.16.1
#5 lore raw

PATCH 3/5 arm64: tegra: Add GPIO controller on Tegra194

Quoted 6 lines · Mikko Perttunen

Add the device tree node for the GPIO controller on Tegra194.

---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Applied, thanks.

Thierry
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#6 lore raw

PATCH 4/5 arm64: tegra: Enable card detect for SD card on P2888

In reply to Mikko Perttunen

Now that we have a GPIO controller, enable the card detect GPIO for the SD card slot.

---
 arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 --
 1 file changed, 2 deletions(-)
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +0 -2
index 95e2433984f7..40d688f7de1c 100644
@@ -33,9 +33,7 @@
 
 		/* SDMMC1 (SD/MMC) */
 		sdhci at 3400000 {
-/*
 			cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>;
-*/
 		};
 
 		/* SDMMC4 (eMMC) */
Signature · 1 line
2.16.1
#7 lore raw

PATCH 4/5 arm64: tegra: Enable card detect for SD card on P2888

Quoted 7 lines · Mikko Perttunen

Now that we have a GPIO controller, enable the card detect GPIO for the SD card slot.

---
 arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 --
 1 file changed, 2 deletions(-)

Applied, thanks.

Thierry
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#8 lore raw

PATCH 5/5 arm64: tegra: Add ethernet controller on Tegra194

In reply to Mikko Perttunen

The Tegra194 contains the same ethernet controller as the Tegra186. Add the device tree node for it, and correspondingly the PHY node on the board device tree.

---
 arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 20 ++++++++++++++++++++
 arch/arm64/boot/dts/nvidia/tegra194.dtsi       | 22 ++++++++++++++++++++++
 2 files changed, 42 insertions(+)
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +20 -0
index 40d688f7de1c..7f2563b78bc7 100644
@@ -27,6 +27,26 @@
 	};
 
 	cbb {
+		ethernet at 2490000 {
+			status = "okay";
+
+			phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
+			phy-handle = <&phy>;
+			phy-mode = "rgmii";
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				phy: phy at 0 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <0x0>;
+					interrupt-parent = <&gpio>;
+					interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
+				};
+			};
+		};
+
 		serial at 3110000 {
 			status = "okay";
 		};
arch/arm64/boot/dts/nvidia/tegra194.dtsi +22 -0
index abe2d688eb65..11666ceb3a24 100644
@@ -35,6 +35,28 @@
 			gpio-controller;
 		};
 
+		ethernet at 2490000 {
+			compatible = "nvidia,tegra186-eqos",
+				     "snps,dwc-qos-ethernet-4.10";
+			reg = <0x02490000 0x10000>;
+			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
+				 <&bpmp TEGRA194_CLK_EQOS_AXI>,
+				 <&bpmp TEGRA194_CLK_EQOS_RX>,
+				 <&bpmp TEGRA194_CLK_EQOS_TX>,
+				 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
+			clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
+			resets = <&bpmp TEGRA194_RESET_EQOS>;
+			reset-names = "eqos";
+			status = "disabled";
+
+			snps,write-requests = <1>;
+			snps,read-requests = <3>;
+			snps,burst-map = <0x7>;
+			snps,txpbl = <16>;
+			snps,rxpbl = <8>;
+		};
+
 		uarta: serial at 3100000 {
 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 			reg = <0x03100000 0x40>;
Signature · 1 line
2.16.1
#9 lore raw

PATCH 5/5 arm64: tegra: Add ethernet controller on Tegra194

Quoted 9 lines · Mikko Perttunen

The Tegra194 contains the same ethernet controller as the Tegra186. Add the device tree node for it, and correspondingly the PHY node on the board device tree.

---
 arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 20 ++++++++++++++++++++
 arch/arm64/boot/dts/nvidia/tegra194.dtsi       | 22 ++++++++++++++++++++++
 2 files changed, 42 insertions(+)

Applied, thanks.

Thierry
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maintainer
#10 lore raw

PATCH 1/5 dt-bindings: tegra186-gpio: Add information for Tegra194

In reply to Mikko Perttunen
Quoted 7 lines · Mikko Perttunen

The Tegra194 GPIO controller is similar to the one in Tegra186. Add relevant information to the device tree binding documentation.

---
 Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt | 4 ++++
 1 file changed, 4 insertions(+)
#12 lore raw

PATCH 1/5 dt-bindings: tegra186-gpio: Add information for Tegra194

In reply to Mikko Perttunen
Quoted 7 lines · Mikko Perttunen

The Tegra194 GPIO controller is similar to the one in Tegra186. Add relevant information to the device tree binding documentation.

---
 Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt | 4 ++++
 1 file changed, 4 insertions(+)

I know this is already applied, but for the record:

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