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i.MX: Add initial CLK support

RFC New Jagan Teki 3 participants 13 messages Jul 9, 2018 – Jul 11, 2018

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Jagan Teki

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#0 lore raw

cover i.MX: Add initial CLK support

One of the blocking area where fec_mxc is unlikely to move dm can be CLK support, this series trying to add support for it and concentrated on ENET clocking for i.MX6QDL and i.MX6UL.

I've verified this on i.MX6QDL, but the reason for sending this is an 'RFC' is there are some quite few issues with existing fec_mxc driver regarding mdio handling. The dm vs non-dm code in fec_mxc looks very uncomfortable to read and add new support, so I would like create one separate dm driver to make dm related changes if all agree?

know issues:
- CLK driver still using enable_fec_anatop_clock function to set the clock, but if we handling this in CLK we need anatop via OF_LIVE. will try this next version
- fec_mxc is passing input ref clock, ENET_50MHZ. don't know how to make this dynamic, or this based on MII or any other feature, need help.
- ipu_common has legacy clk support, since may boards are using ipu_common better to handle this via CLK so-that move to CLK become easy and meaningful.

patch 1, clk/kconfig ordering

patch 2, sample i.MX6QDL DM CLK template

patch 3, 4 Implement ENET clocks for i.MX6QDL and i.MX6UL

patch 5, add generic_clk_valid function

patch 6, add CLK support in fec_mxc.c

patch 7,8 enable CLK support on engicam boards

Jagan Teki (8):
clk: Kconfig: Ascending order to sub directiory kconfigs
clk: Add DM CLK driver template for i.MX6QDL
clk: imx: imx6q: Implement ENET clocks
clk: imx: imx6ul: Implement ENET clocks
clk: Add generic_clk_valid
net: fec_mxc: Add clock support via CLK
imx6ul: engicam: Enable CLK_IMX
configs: icorem6_rqs: Enable CLK_IMX

 arch/arm/mach-imx/mx6/Kconfig       |  2 +
 configs/imx6qdl_icore_rqs_defconfig |  1 +
 drivers/clk/Kconfig                 |  9 +--
 drivers/clk/Makefile                |  1 +
 drivers/clk/imx/Kconfig             | 25 ++++++++
 drivers/clk/imx/Makefile            |  8 +++
 drivers/clk/imx/clk_imx6q.c         | 89 +++++++++++++++++++++++++++
 drivers/clk/imx/clk_imx6ul.c        | 95 +++++++++++++++++++++++++++++
 drivers/net/fec_mxc.c               | 58 ++++++++++++++++++
 drivers/net/fec_mxc.h               |  6 ++
 drivers/video/ipu_common.c          |  8 +++
 include/clk-uclass.h                | 10 +++
 12 files changed, 308 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/imx/Kconfig
 create mode 100644 drivers/clk/imx/Makefile
 create mode 100644 drivers/clk/imx/clk_imx6q.c
 create mode 100644 drivers/clk/imx/clk_imx6ul.c
Signature · 1 line
2.17.1
author
#1 lore raw

RFC 1/8 clk: Kconfig: Ascending order to sub directiory kconfigs

sourcing of sub directiory kconfig files are not in proper order, so keep them in ascending order.

---
 drivers/clk/Kconfig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/clk/Kconfig +4 -4
index edb4ca58ea..3e66dd97c1 100644
@@ -83,12 +83,12 @@ config CLK_STM32MP1
 	  Enable the STM32 clock (RCC) driver. Enable support for
 	  manipulating STM32MP1's on-SoC clocks.
 
-source "drivers/clk/tegra/Kconfig"
-source "drivers/clk/uniphier/Kconfig"
-source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/at91/Kconfig"
-source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
+source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/tegra/Kconfig"
+source "drivers/clk/uniphier/Kconfig"
 
 config ICS8N3QV01
 	bool "Enable ICS8N3QV01 VCXO driver"
Signature · 1 line
2.17.1
author
#2 lore raw

RFC 2/8 clk: Add DM CLK driver template for i.MX6QDL

In reply to Jagan Teki

Add DM CLK driver for iMX6QDL platform.
- basic template for clk_imx6qdl.c
- Kconfig support

---
 arch/arm/mach-imx/mx6/Kconfig |  1 +
 drivers/clk/Kconfig           |  1 +
 drivers/clk/Makefile          |  1 +
 drivers/clk/imx/Kconfig       | 18 +++++++++
 drivers/clk/imx/Makefile      |  7 ++++
 drivers/clk/imx/clk_imx6q.c   | 76 +++++++++++++++++++++++++++++++++++
 drivers/video/ipu_common.c    |  8 ++++
 7 files changed, 112 insertions(+)
 create mode 100644 drivers/clk/imx/Kconfig
 create mode 100644 drivers/clk/imx/Makefile
 create mode 100644 drivers/clk/imx/clk_imx6q.c
arch/arm/mach-imx/mx6/Kconfig +1 -0
index 521fad74b5..4410f53b55 100644
@@ -257,6 +257,7 @@ config TARGET_MX6Q_ENGICAM
 	select MX6QDL
 	select OF_CONTROL
 	select SPL_OF_LIBFDT
+	select CLK_IMX
 	select DM
 	select DM_ETH
 	select DM_GPIO
drivers/clk/Kconfig +1 -0
index 3e66dd97c1..7404f96dab 100644
@@ -85,6 +85,7 @@ config CLK_STM32MP1
 
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
+source "drivers/clk/imx/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/tegra/Kconfig"
drivers/clk/Makefile +1 -0
index 426c67db9b..e73a386c5b 100644
@@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
+obj-$(CONFIG_CLK_IMX) += imx/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
 obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
 obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
drivers/clk/imx/Kconfig new file +18 -0
new file mode 100644
index 0000000000..f8de5554c8
@@ -0,0 +1,18 @@
+config CLK_IMX
+	bool "Clock support for i.MX SoCs"
+	depends on ARCH_MX6
+	select CLK
+	help
+	  This enables support for common clock driver API on i.MX
+	  SoCs.
+
+if CLK_IMX
+
+config CLK_IMX6Q
+	bool "Clock driver for i.MX6QDL"
+	default MX6QDL
+	help
+	  This enables common clock driver support for platforms based
+	  on i.MX6 QDL SoC.
+
+endif # CLK_IMX
drivers/clk/imx/Makefile new file +7 -0
new file mode 100644
index 0000000000..8ae3a50eba
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2018 Arm Ltd.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_CLK_IMX6Q) += clk_imx6q.o
drivers/clk/imx/clk_imx6q.c new file +76 -0

76 lines not on this page · raw message

drivers/video/ipu_common.c +8 -0
index cbe1984e4f..9725f76477 100644
@@ -86,6 +86,7 @@ struct ipu_ch_param {
 #define IPUV3_CLK_MX6Q		264000000
 #define IPUV3_CLK_MX6DL		198000000
 
+#ifndef CONFIG_CLK
 void clk_enable(struct clk *clk)
 {
 	if (clk) {
@@ -104,6 +105,7 @@ void clk_disable(struct clk *clk)
 		}
 	}
 }
+#endif
 
 int clk_get_usecount(struct clk *clk)
 {
@@ -113,6 +115,7 @@ int clk_get_usecount(struct clk *clk)
 	return clk->usecount;
 }
 
+#ifndef CONFIG_CLK
 u32 clk_get_rate(struct clk *clk)
 {
 	if (!clk)
@@ -120,6 +123,7 @@ u32 clk_get_rate(struct clk *clk)
 
 	return clk->rate;
 }
+#endif
 
 struct clk *clk_get_parent(struct clk *clk)
 {
@@ -129,6 +133,7 @@ struct clk *clk_get_parent(struct clk *clk)
 	return clk->parent;
 }
 
+#ifndef CONFIG_CLK
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	if (!clk)
@@ -139,6 +144,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 
 	return clk->rate;
 }
+#endif
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
@@ -148,6 +154,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
 	return clk->round_rate(clk, rate);
 }
 
+#ifndef CONFIG_CLK
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
 	clk->parent = parent;
@@ -155,6 +162,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 		return clk->set_parent(clk, parent);
 	return 0;
 }
+#endif
 
 static int clk_ipu_enable(struct clk *clk)
 {
Signature · 1 line
2.17.1
author
#3 lore raw

RFC 3/8 clk: imx: imx6q: Implement ENET clocks

In reply to Jagan Teki

Add support for ENET clock on i.MX6QDL platform.

---
 drivers/clk/imx/clk_imx6q.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)
drivers/clk/imx/clk_imx6q.c +18 -5
index 3019218411..f0cb7ece1f 100644
@@ -26,18 +26,31 @@ static ulong imx6q_clk_get_rate(struct clk *clk)
 
 static ulong imx6q_clk_set_rate(struct clk *clk, ulong rate)
 {
-	debug("%s(#%ld, rate: %lu)\n", __func__, clk->id, rate);
+	debug("%s(#%ld)\n", __func__, clk->id);
 
-	debug("  unhandled\n");
-	return -EINVAL;
+	switch (clk->id) {
+	case IMX6QDL_CLK_ENET_REF:
+		return enable_fec_anatop_clock(0, rate);
+	default:
+		printf("  unhandled\n");
+		return -ENODEV;
+	}
 }
 
 static int imx6q_clk_enable(struct clk *clk)
 {
+	struct imx6q_clk_priv *priv = dev_get_priv(clk->dev);
+
 	debug("%s(#%ld)\n", __func__, clk->id);
 
-	debug("  unhandled\n");
-	return -EINVAL;
+	switch (clk->id) {
+	case IMX6QDL_CLK_ENET:
+		setbits_le32(priv->base + 0x6c, GENMASK(11, 10));
+		return 0;
+	default:
+		printf("  unhandled\n");
+		return -ENODEV;
+	}
 }
 
 static struct clk_ops imx6q_clk_ops = {
Signature · 1 line
2.17.1
author
#5 lore raw

RFC 4/8 clk: imx: imx6ul: Implement ENET clocks

In reply to Jagan Teki

Add support for ENET clock on i.MX6UL platform.

---
 drivers/clk/imx/Kconfig      |  7 +++
 drivers/clk/imx/Makefile     |  1 +
 drivers/clk/imx/clk_imx6ul.c | 95 ++++++++++++++++++++++++++++++++++++
 3 files changed, 103 insertions(+)
 create mode 100644 drivers/clk/imx/clk_imx6ul.c
drivers/clk/imx/Kconfig +7 -0
index f8de5554c8..cfb9cfe2eb 100644
@@ -15,4 +15,11 @@ config CLK_IMX6Q
 	  This enables common clock driver support for platforms based
 	  on i.MX6 QDL SoC.
 
+config CLK_IMX6UL
+	bool "Clock driver for i.MX6UL"
+	default MX6UL
+	help
+	  This enables common clock driver support for platforms based
+	  on i.MX6 UL SoC.
+
 endif # CLK_IMX
drivers/clk/imx/Makefile +1 -0
index 8ae3a50eba..67d6f9a19f 100644
@@ -5,3 +5,4 @@
 #
 
 obj-$(CONFIG_CLK_IMX6Q) += clk_imx6q.o
+obj-$(CONFIG_CLK_IMX6UL) += clk_imx6ul.o
drivers/clk/imx/clk_imx6ul.c new file +95 -0

95 lines not on this page · raw message

Signature · 1 line
2.17.1
author
#7 lore raw

RFC 5/8 clk: Add generic_clk_valid

In reply to Jagan Teki

Add clock validate function for validating
specific clock to do further clock operations.

---
 include/clk-uclass.h | 10 ++++++++++
 1 file changed, 10 insertions(+)
include/clk-uclass.h +10 -0
index e76d98e2f6..452eed008e 100644
@@ -100,4 +100,14 @@ struct clk_ops {
 	int (*disable)(struct clk *clk);
 };
 
+/**
+ * generic_clk_valid() - check if clk port is valid
+ *
+ * @clk:	the clk port to check
+ * @return TRUE if valid, or FALSE
+ */
+static inline bool generic_clk_valid(struct clk *clk)
+{
+	return clk->dev != NULL;
+}
 #endif
Signature · 1 line
2.17.1
author
#9 lore raw

RFC 6/8 net: fec_mxc: Add clock support via CLK

In reply to Jagan Teki

Now enet clock support available for imx6qdl and imx6ul, via CLK framework, so add enable, set_rate support in drivers.

---
 drivers/net/fec_mxc.c | 58 +++++++++++++++++++++++++++++++++++++++++++
 drivers/net/fec_mxc.h |  6 +++++
 2 files changed, 64 insertions(+)
drivers/net/fec_mxc.c +58 -0
index 694a0b2f7e..7998c8b8b2 100644
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <environment.h>
 #include <malloc.h>
@@ -1245,6 +1246,41 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(CLK)
+static int fec_clk_enable(struct fec_priv *priv)
+{
+	int ret;
+
+	ret = clk_enable(&priv->clk_ahb);
+	if (ret) {
+		printf("failed to enable ahb clk\n");
+		return ret;
+	}
+
+	if (generic_clk_valid(&priv->clk_ptp)) {
+		ret = clk_set_rate(&priv->clk_ptp, ENET_50MHZ);
+		if (ret) {
+			printf("failed to set 50MHz rate to ptp clk\n");
+			goto failed_clk_ahb;
+		}
+	}
+
+	if (generic_clk_valid(&priv->clk_enet_out)) {
+		ret = clk_set_rate(&priv->clk_enet_out, ENET_50MHZ);
+		if (ret) {
+			printf("failed to set 50MHz rate to enet_out clk\n");
+			goto failed_clk_ahb;
+		}
+	}
+
+	return 0;
+
+failed_clk_ahb:
+	clk_disable(&priv->clk_ahb);
+	return ret;
+}
+#endif
+
 static int fecmxc_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -1253,6 +1289,12 @@ static int fecmxc_probe(struct udevice *dev)
 	uint32_t start;
 	int ret;
 
+#if CONFIG_IS_ENABLED(CLK)
+	ret = fec_clk_enable(priv);
+	if (ret)
+		return ret;
+#endif
+
 	ret = fec_alloc_descs(priv);
 	if (ret)
 		return ret;
@@ -1331,6 +1373,22 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	}
 
+#if CONFIG_IS_ENABLED(CLK)
+	int ret;
+
+	ret = clk_get_by_name(dev, "ahb", &priv->clk_ahb);
+	if (ret)
+		ret = PTR_ERR(&priv->clk_ahb);
+
+	ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
+	if (ret)
+		dev_dbg(dev, "Warning: failed to get ptp clk\n");
+
+	ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
+	if (ret)
+		dev_dbg(dev, "Warning: failed to get enet_out clk\n");
+#endif
+
 	/* TODO
 	 * Need to get the reset-gpio and related properties from DT
 	 * and implemet the enet reset code on .probe call
drivers/net/fec_mxc.h +6 -0
index 3b935afe2c..78899e7603 100644
@@ -253,6 +253,12 @@ struct fec_priv {
 
 #ifdef CONFIG_DM_ETH
 	u32 interface;
+
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk clk_ahb;
+	struct clk clk_ptp;
+	struct clk clk_enet_out;
+#endif
 #endif
 };
 
Signature · 1 line
2.17.1
author
#11 lore raw

RFC 7/8 imx6ul: engicam: Enable CLK_IMX

In reply to Jagan Teki

CLK support for imx6ul is available, so enable
CLK_IMX for Engicam i.MX6UL boards.

---
 arch/arm/mach-imx/mx6/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-imx/mx6/Kconfig +1 -0
index 4410f53b55..4ea43db34c 100644
@@ -338,6 +338,7 @@ config TARGET_MX6UL_ENGICAM
 	select BOARD_LATE_INIT
 	select MX6UL
 	select OF_CONTROL
+	select CLK_IMX
 	select DM
 	select DM_ETH
 	select DM_GPIO
Signature · 1 line
2.17.1
author
#12 lore raw

RFC 8/8 configs: icorem6_rqs: Enable CLK_IMX

In reply to Jagan Teki

CLK support for imx6qdl is available, so enable
CLK_IMX for Engicam i.CoreM6 QDL RQS boards.

---
 configs/imx6qdl_icore_rqs_defconfig | 1 +
 1 file changed, 1 insertion(+)
configs/imx6qdl_icore_rqs_defconfig +1 -0
index 6fa494a6f9..6036719a31 100644
@@ -46,3 +46,4 @@ CONFIG_FEC_MXC=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
+CONFIG_CLK_IMX=y
Signature · 1 line
2.17.1