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phy: sun4i-usb: Call phy_passby even for PHY#0

PATCH New Jagan Teki 1 participant 5 messages Jul 20, 2018 – Jul 31, 2018

Subsystems (2)
Arm/Allwinner sunXi SoC support Generic PHY framework
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Jagan Teki

author
#0 lore raw

PATCH v2 1/4 phy: sun4i-usb: Call phy_passby even for PHY#0

On newer Allwinner SoC, there is a pair of EHCI/OHCI USB hosts for OTG host mode. USB PHY passby must be configured for its corresponding PHY. so we can call for PHY#0. on the other hand in past usb-phy code the same thing can be restricted for Lower SoC's, other than H3/H5/A64.

Now there is no need to restrict usb passby since the phy driver is DT enabled, and the respective phy calls will trigger based DT information initiated by the drivers.

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v2:
- update commit message, suggested by 'Chen-Yu'

 drivers/phy/allwinner/phy-sun4i-usb.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/phy/allwinner/phy-sun4i-usb.c +1 -2
index 2b3cf48025..01f585a283 100644
@@ -300,8 +300,7 @@ static int sun4i_usb_phy_init(struct phy *phy)
 				    data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 	}
 
-	if (usb_phy->id != 0)
-		sun4i_usb_phy_passby(phy, true);
+	sun4i_usb_phy_passby(phy, true);
 
 	sun4i_usb_phy0_reroute(data, true);
Signature · 1 line
2.17.1
author
#1 lore raw

PATCH v2 2/4 phy: sun4i-usb: Remove usb_clk_cfg set in probe

usb_clk_cfg is setting CTRL_PHYGATE bit value in probe which is BIT 0 for sun4i, 6i and 8 for a83t but all these were handling in phy ops init exit calls.

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v2:
- none

 drivers/phy/allwinner/phy-sun4i-usb.c | 2 --
 1 file changed, 2 deletions(-)
drivers/phy/allwinner/phy-sun4i-usb.c +0 -2
index 01f585a283..3096f12c1c 100644
@@ -462,8 +462,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 		phy->rst_mask = info->rst_mask;
 	};
 
-	setbits_le32(&data->ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
 	debug("Allwinner Sun4I USB PHY driver loaded\n");
 	return 0;
 }
Signature · 1 line
2.17.1
author
#2 lore raw

PATCH v2 3/4 phy: sun4i-usb: Update PHY#3 rst_mask only for H3_H5

In reply to Jagan Teki

Only H3 and H5 have 4 PHYS so restrict rst_mask only for them by checking PHY id as 3 and update the proper bits.

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v2:
- update rst_mask value for H3_H5

 drivers/phy/allwinner/phy-sun4i-usb.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
drivers/phy/allwinner/phy-sun4i-usb.c +2 -3
index 3096f12c1c..a7d7e3f044 100644
@@ -117,9 +117,6 @@ struct sun4i_usb_phy_info {
 		.gpio_vbus = CONFIG_USB3_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-#ifdef CONFIG_MACH_SUN6I
-		.rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
-#endif
 	},
 };
 

@@ -460,6 +457,8 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 
 		phy->id = i;
 		phy->rst_mask = info->rst_mask;
+		if ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3))
+			phy->rst_mask = (BIT(3) | BIT(11));
 	};
 
 	debug("Allwinner Sun4I USB PHY driver loaded\n");
Signature · 1 line
2.17.1
author
#3 lore raw

PATCH v2 4/4 configs: sunxi: Drop CONFIG_SUNXI_USB_PHYS

In reply to Jagan Teki

Now number of PHY on Allwinner is handling via dt data, drivers at phy/allwinner/phy-sun4i-usb.c

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v2:
- new patch

 include/configs/sun4i.h      |  2 --
 include/configs/sun50i.h     |  2 --
 include/configs/sun5i.h      |  2 --
 include/configs/sun6i.h      |  2 --
 include/configs/sun7i.h      |  2 --
 include/configs/sun8i.h      | 10 ----------
 scripts/config_whitelist.txt |  1 -
 7 files changed, 21 deletions(-)
include/configs/sun4i.h +0 -2
index 63c84b1ceb..af079a71ee 100644
@@ -15,8 +15,6 @@
 #define CONFIG_USB_EHCI_SUNXI
 #endif
 
-#define CONFIG_SUNXI_USB_PHYS	3
-
 /*
  * Include common sunxi configuration where most the settings are
  */
include/configs/sun50i.h +0 -2
index 5ce2cde388..8cfac38106 100644
@@ -15,8 +15,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 #endif
 
-#define CONFIG_SUNXI_USB_PHYS	1
-
 #define GICD_BASE		0x1c81000
 #define GICC_BASE		0x1c82000
include/configs/sun5i.h +0 -2
index cb33d01e16..c3692caa73 100644
@@ -15,8 +15,6 @@
 #define CONFIG_USB_EHCI_SUNXI
 #endif
 
-#define CONFIG_SUNXI_USB_PHYS	2
-
 /*
  * Include common sunxi configuration where most the settings are
  */
include/configs/sun6i.h +0 -2
index a3f768f936..1523684fad 100644
@@ -18,8 +18,6 @@
 #define CONFIG_USB_EHCI_SUNXI
 #endif
 
-#define CONFIG_SUNXI_USB_PHYS	3
-
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE    (64 * 1024) /* 64 KB */
include/configs/sun7i.h +0 -2
index d3c4c7dbcf..bb8f217b25 100644
@@ -16,8 +16,6 @@
 #define CONFIG_USB_EHCI_SUNXI
 #endif
 
-#define CONFIG_SUNXI_USB_PHYS	3
-
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE	(64 * 1024) /* 64 KB */
include/configs/sun8i.h +0 -10
index 4fdf68a491..7dc8693b76 100644
@@ -16,16 +16,6 @@
 #define CONFIG_USB_EHCI_SUNXI
 #endif
 
-#ifdef CONFIG_MACH_SUN8I_H3
-	#define CONFIG_SUNXI_USB_PHYS	4
-#elif defined CONFIG_MACH_SUN8I_A83T
-	#define CONFIG_SUNXI_USB_PHYS	3
-#elif defined CONFIG_MACH_SUN8I_V3S
-	#define CONFIG_SUNXI_USB_PHYS	1
-#else
-	#define CONFIG_SUNXI_USB_PHYS	2
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */
scripts/config_whitelist.txt +0 -1
index 2f6c9557a5..1065066bc3 100644
@@ -2017,7 +2017,6 @@ CONFIG_ST_SMI
 CONFIG_SUNXI_AHCI
 CONFIG_SUNXI_GPIO
 CONFIG_SUNXI_MAX_FB_SIZE
-CONFIG_SUNXI_USB_PHYS
 CONFIG_SUPERH_ON_CHIP_R8A66597
 CONFIG_SUPPORT_EMMC_BOOT
 CONFIG_SUVD3
Signature · 1 line
2.17.1
author
#4 lore raw

PATCH v2 4/4 configs: sunxi: Drop CONFIG_SUNXI_USB_PHYS

Quoted 5 lines · Jagan Teki

Now number of PHY on Allwinner is handling via dt data, drivers at phy/allwinner/phy-sun4i-usb.c

Signed-off-by Jagan Teki <[email protected]>

---

Applied all.