arm: socfpga: Add support for the ReflexCES R329 board

PATCH New Xavier Ruppen 2 participants 2 messages Jul 24, 2018 – Jul 25, 2018

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/socfpga architecture

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Xavier Ruppen

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2018-07-24 17:21 UTC #0 lore raw

PATCH 1/1 arm: socfpga: Add support for the ReflexCES R329 board

The ReflexCES PCIe carrier board Arria 10 SoC SoM (R329) provides access to all the features of the Arria 10 SoC SoM (R315) (Ethernet, OTG USB, Transceivers, UART) and adds further functions, including SFP+ connectors, PCIe x8 Gen3, USB3.0 and a wifi interface.

No fpga portion is provided in fit_spl_fpga.its as MSEL is hardwired on this board. Thus, a bitstream is loaded before booting by using the EPCQ. It is possible to load a bitstream from the HPS (packaged in the .sfp file) but a small hardware mod on the MSEL lines is required (tested and works).

Signed-off-by Xavier Ruppen <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

---

This patch was created and tested against u-boot-socfpga/arria10_sdmmc.

The handoff.dtsi file was created by meld'ing the (old) .dts file provided by ReflexCES and socfpga_arria10_socdk_sdmmc_handoff.dtsi.

The board was tested with what I believe is the factory bitstream written in the EPCQ.

As I copied and pasted the majority of the files from the arria10-socdk, I purposely ignored a bunch of checkpatch warnings, i.e. lenghty lines and a missing SPDX-License-Identifier in the .dts(i) files.

 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/socfpga_arria10_r329.dts         | 108 ++++++
 .../arm/dts/socfpga_arria10_r329_handoff.dtsi | 350 ++++++++++++++++++
 arch/arm/mach-socfpga/Kconfig                 |   7 +
 board/reflexces/r329-a10-pcie/Kconfig         |  18 +
 board/reflexces/r329-a10-pcie/MAINTAINERS     |   8 +
 board/reflexces/r329-a10-pcie/Makefile        |   5 +
 .../reflexces/r329-a10-pcie/fit_spl_fpga.its  |  45 +++
 board/reflexces/r329-a10-pcie/socfpga.c       |   6 +
 configs/socfpga_r329_a10_pcie_defconfig       |  67 ++++
 include/configs/socfpga_r329_a10_pcie.h       |  50 +++
 11 files changed, 665 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_r329.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_r329_handoff.dtsi
 create mode 100644 board/reflexces/r329-a10-pcie/Kconfig
 create mode 100644 board/reflexces/r329-a10-pcie/MAINTAINERS
 create mode 100644 board/reflexces/r329-a10-pcie/Makefile
 create mode 100644 board/reflexces/r329-a10-pcie/fit_spl_fpga.its
 create mode 100644 board/reflexces/r329-a10-pcie/socfpga.c
 create mode 100644 configs/socfpga_r329_a10_pcie_defconfig
 create mode 100644 include/configs/socfpga_r329_a10_pcie.h

arch/arm/dts/Makefile +1 -0

index 946023093d..05cd7af467 100644
@@ -188,6 +188,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_arria5_socdk.dtb			\
 	socfpga_arria10_socdk_sdmmc.dtb			\
+	socfpga_arria10_r329.dtb			\
 	socfpga_cyclone5_is1.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_dbm_soc1.dtb			\

arch/arm/dts/socfpga_arria10_r329.dts new file +108 -0

108 lines not on this page · raw message

arch/arm/dts/socfpga_arria10_r329_handoff.dtsi new file +350 -0

350 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +7 -0

index 30b475254c..7e96b7e976 100644
@@ -28,6 +28,10 @@ config TARGET_SOCFPGA_ARRIA10_SOCDK
 	bool "Altera SOCFPGA SoCDK (Arria 10)"
 	select TARGET_SOCFPGA_ARRIA10
 
+config TARGET_SOCFPGA_ARRIA10_R329
+	bool "Reflex CES SOCFPGA R329 PCIe (Arria 10)"
+	select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_ARRIA5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Arria V)"
 	select TARGET_SOCFPGA_ARRIA5

@@ -78,6 +82,7 @@ endchoice
 config SYS_BOARD
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+	default "r329-a10-pcie" if TARGET_SOCFPGA_ARRIA10_R329
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO

@@ -92,6 +97,7 @@ config SYS_BOARD
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
+	default "reflexces" if TARGET_SOCFPGA_ARRIA10_R329
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES

@@ -107,6 +113,7 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+	default "socfpga_r329_a10_pcie" if TARGET_SOCFPGA_ARRIA10_R329
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO

board/reflexces/r329-a10-pcie/Kconfig new file +18 -0

new file mode 100644
index 0000000000..fe4a0267e7
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "r329-a10-pcie"
+
+config SYS_VENDOR
+	default "reflexces"
+
+config SYS_SOC
+	default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+	default "socfpga_r329_a10_pcie"
+
+endif

board/reflexces/r329-a10-pcie/MAINTAINERS new file +8 -0

new file mode 100644
index 0000000000..0ed98d8023
@@ -0,0 +1,8 @@
+R329 BOARD
+M:	Xavier Ruppen <[email protected]>
+S:	Maintained
+F:	board/reflexces/r329-a10-pcie/
+F:	include/configs/socfpga_arria10_r329.h
+F:	configs/socfpga_r329_a10_pcie_defconfig
+F:	arch/arm/dts/socfpga_arria10_r329.dts
+F:	arch/arm/dts/socfpga_arria10_r329_handoff.dtsi

board/reflexces/r329-a10-pcie/Makefile new file +5 -0

new file mode 100644
index 0000000000..80d0004346
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2015 Altera Corporation <www.altera.com>
+
+obj-y	:= socfpga.o

board/reflexces/r329-a10-pcie/fit_spl_fpga.its new file +45 -0

45 lines not on this page · raw message

board/reflexces/r329-a10-pcie/socfpga.c new file +6 -0

new file mode 100644
index 0000000000..4c466cb944
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>

configs/socfpga_r329_a10_pcie_defconfig new file +67 -0

67 lines not on this page · raw message

include/configs/socfpga_r329_a10_pcie.h new file +50 -0

50 lines not on this page · raw message

Signature · 1 line

2.17.1

Marek Vasut

2018-07-25 17:41 UTC #1 lore raw

PATCH 1/1 arm: socfpga: Add support for the ReflexCES R329 board

Quoted 10 lines · Xavier Ruppen

The ReflexCES PCIe carrier board Arria 10 SoC SoM (R329) provides access to all the features of the Arria 10 SoC SoM (R315) (Ethernet, OTG USB, Transceivers, UART) and adds further functions, including SFP+ connectors, PCIe x8 Gen3, USB3.0 and a wifi interface.
No fpga portion is provided in fit_spl_fpga.its as MSEL is hardwired on this board. Thus, a bitstream is loaded before booting by using the EPCQ. It is possible to load a bitstream from the HPS (packaged in the .sfp file) but a small hardware mod on the MSEL lines is required (tested and works).

Quoted 7 lines

Signed-off-by Xavier Ruppen <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
This patch was created and tested against u-boot-socfpga/arria10_sdmmc.

Can it be based on u-boot/master and does it work ? I am not accepting patches on top of these random branches.

Quoted 9 lines

The handoff.dtsi file was created by meld'ing the (old) .dts file provided by ReflexCES and socfpga_arria10_socdk_sdmmc_handoff.dtsi.
The board was tested with what I believe is the factory bitstream written in the EPCQ.
As I copied and pasted the majority of the files from the arria10-socdk, I purposely ignored a bunch of checkpatch warnings, i.e. lenghty lines and a missing SPDX-License-Identifier in the .dts(i) files.

Those should be fixed ...

[...]

Quoted 11 lines

+++ b/include/configs/socfpga_r329_a10_pcie.h

include/configs/socfpga_r329_a10_pcie.h new file +9 -0

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include <asm/arch/base_addr_a10.h>

include/configs/socfpga_r329_a10_pcie.h line 19

Quoted 10 lines

include/configs/socfpga_r329_a10_pcie.h new file +10 -0

+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/*
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF

Is this needed ?

include/configs/socfpga_r329_a10_pcie.h line 24

Quoted 4 lines

include/configs/socfpga_r329_a10_pcie.h new file +4 -0
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE		0xC0000000
+
+/* Ethernet on SoC (EMAC) */

The comments need cleanup.

include/configs/socfpga_r329_a10_pcie.h line 33

Quoted 8 lines

include/configs/socfpga_r329_a10_pcie.h new file +8 -0

+/*
+ * U-Boot environment configurations
+ */
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32

Needed ?

include/configs/socfpga_r329_a10_pcie.h line 34

Quoted 1 line

include/configs/socfpga_r329_a10_pcie.h new file +1 -0
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}

Needed ?

If so, should be enabled on all socfpgas .

Quoted 16 lines

include/configs/socfpga_r329_a10_pcie.h new file +15 -0

+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFGPA_ARRIA10_H__ */

Signature · 2 lines

Best regards,
Marek Vasut