drm/i915: Clean up power well descriptors

It makes sense to keep unchanging data const. Extract such fields from
the i915_power_well struct into a new i915_power_well_desc struct that
we initialize during compile time. For the rest of the dynamic fields allocate an array of i915_power_well objects in i915 dev_priv, and link to each of these objects their corresponding i915_power_well_desc object.

v2:
- Fix checkpatch warnings about missing param name in fn declaration and
lines over 80 chars. (Paulo)
- Move check for unique IDs to __set_power_wells().

Cc Ville Syrjala <[email protected]>

Cc Paulo Zanoni <[email protected]>

Cc Jani Nikula <[email protected]>

Signed-off-by Imre Deak <[email protected]>

Reviewed-by Paulo Zanoni <[email protected]> (v1)

---
 drivers/gpu/drm/i915/i915_debugfs.c     |   4 +-
 drivers/gpu/drm/i915/i915_drv.c         |   8 +-
 drivers/gpu/drm/i915/i915_drv.h         |  14 ++-
 drivers/gpu/drm/i915/intel_display.h    |   4 +-
 drivers/gpu/drm/i915/intel_drv.h        |   1 +
 drivers/gpu/drm/i915/intel_hdcp.c       |   6 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 205 ++++++++++++++++++--
------------
 7 files changed, 140 insertions(+), 102 deletions(-)

drivers/gpu/drm/i915/i915_debugfs.c +2 -2

index f9ce35da4123..23f38bc257a2 100644
@@ -2845,10 +2845,10 @@ static int i915_power_domain_info(struct
 seq_file *m, void *unused)
 		enum intel_display_power_domain power_domain;
 
 		power_well = &power_domains->power_wells[i];
-		seq_printf(m, "%-25s %d\n", power_well->name,
+		seq_printf(m, "%-25s %d\n", power_well->desc->name,
 			   power_well->count);
 
-		for_each_power_domain(power_domain, power_well-
 >domains)
+		for_each_power_domain(power_domain, power_well-
 >desc->domains)

drivers/gpu/drm/i915/i915_debugfs.c +0 -0

 			seq_printf(m, "  %-23s %d\n",
 				 intel_display_power_domain_str(powe

r_domain),
power_domains-

Quoted 1 line

domain_use_count[power_domain]);

drivers/gpu/drm/i915/i915_drv.c +3 -1

index e92f374521fc..e8df8180be35 100644
@@ -924,7 +924,9 @@ static int i915_driver_init_early(struct
 drm_i915_private *dev_priv,
 	intel_uc_init_early(dev_priv);
 	intel_pm_setup(dev_priv);
 	intel_init_dpio(dev_priv);
-	intel_power_domains_init(dev_priv);
+	ret = intel_power_domains_init(dev_priv);
+	if (ret < 0)
+		goto err_uc;
 	intel_irq_init(dev_priv);
 	intel_hangcheck_init(dev_priv);

drivers/gpu/drm/i915/i915_drv.c +3 -0

 	intel_init_display_hooks(dev_priv);

@@ -936,6 +938,9 @@ static int i915_driver_init_early(struct
 drm_i915_private *dev_priv,
 
 	return 0;
 
+err_uc:
+	intel_uc_cleanup_early(dev_priv);
+	i915_gem_cleanup_early(dev_priv);
 err_workqueues:
 	i915_workqueues_cleanup(dev_priv);

err_engines:

drivers/gpu/drm/i915/i915_drv.c +1 -0

@@ -950,6 +955,7 @@ static int i915_driver_init_early(struct
 drm_i915_private *dev_priv,
 static void i915_driver_cleanup_early(struct drm_i915_private
 *dev_priv)
 {
 	intel_irq_fini(dev_priv);
+	intel_power_domains_cleanup(dev_priv);
 	intel_uc_cleanup_early(dev_priv);

drivers/gpu/drm/i915/i915_drv.c +0 -0

 	i915_gem_cleanup_early(dev_priv);
 	i915_workqueues_cleanup(dev_priv);

drivers/gpu/drm/i915/i915_drv.h +9 -5

index 4aca5344863d..85ad1909f5f0 100644
@@ -868,13 +868,9 @@ struct i915_power_well_ops {
 };
 
 /* Power well structure for haswell */
-struct i915_power_well {
+struct i915_power_well_desc {
 	const char *name;
 	bool always_on;
-	/* power well enable/disable usage count */
-	int count;
-	/* cached hw enabled state */
-	bool hw_enabled;
 	u64 domains;
 	/* unique identifier for this power well */
 	enum i915_power_well_id id;

@@ -897,6 +893,14 @@ struct i915_power_well {
 	const struct i915_power_well_ops *ops;
 };
 
+struct i915_power_well {
+	const struct i915_power_well_desc *desc;
+	/* power well enable/disable usage count */
+	int count;
+	/* cached hw enabled state */
+	bool hw_enabled;
+};
+
 struct i915_power_domains {
 	/*
 	 * Power wells needed for initialization at driver init and

suspend

drivers/gpu/drm/i915/intel_display.h +1 -1

index 0a79a46d5805..6a28bac71128 100644
@@ -329,11 +329,11 @@ struct intel_link_m_n {
 
 #define for_each_power_domain_well(__dev_priv, __power_well,
 __domain_mask)	\
 	for_each_power_well(__dev_priv, __power_well)		
 		\
-		for_each_if((__power_well)->domains &
 (__domain_mask))
+		for_each_if((__power_well)->desc->domains &
 (__domain_mask))
 
 #define for_each_power_domain_well_rev(__dev_priv, __power_well,
 __domain_mask) \

drivers/gpu/drm/i915/intel_display.h +0 -1

 	for_each_power_well_rev(__dev_priv, __power_well)		
        \
-		for_each_if((__power_well)->domains &

(__domain_mask))

drivers/gpu/drm/i915/intel_display.h +1 -0

+		for_each_if((__power_well)->desc->domains &

(__domain_mask))

#define for_each_new_intel_plane_in_state(__state, plane,
new_plane_state, __i) \

drivers/gpu/drm/i915/intel_display.h +0 -0

 	for ((__i) = 0; \

drivers/gpu/drm/i915/intel_drv.h +1 -0

index 3576ab5735b1..0601abb8c71f 100644
@@ -1948,6 +1948,7 @@ int intel_psr_wait_for_idle(const struct
 intel_crtc_state *new_crtc_state);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
+void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv,
 bool resume);

void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv); void intel_power_domains_suspend(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_hdcp.c +2 -3

index 0cc6a861bcf8..26e48fc95543 100644
@@ -57,9 +57,9 @@ static bool hdcp_key_loadable(struct
 drm_i915_private *dev_priv)
 
 	/* PG1 (power well #1) needs to be enabled */
 	for_each_power_well(dev_priv, power_well) {
-		if (power_well->id == id) {
-			enabled = power_well->ops-
 >is_enabled(dev_priv,
-							      power_
 well);
+		if (power_well->desc->id == id) {
+			enabled = power_well->desc->ops-

Quoted 1 line

is_enabled(dev_priv,

drivers/gpu/drm/i915/intel_hdcp.c +1 -0

+								    

power_well);

drivers/gpu/drm/i915/intel_hdcp.c +0 -0

 			break;
 		}
 	}

drivers/gpu/drm/i915/intel_runtime_pm.c +3 -3

index b2d182cc3319..a8916090a85e 100644
@@ -159,17 +159,17 @@ intel_display_power_domain_str(enum
 intel_display_power_domain domain)
 static void intel_power_well_enable(struct drm_i915_private
 *dev_priv,
 				    struct i915_power_well
 *power_well)
 {
-	DRM_DEBUG_KMS("enabling %s\n", power_well->name);
-	power_well->ops->enable(dev_priv, power_well);
+	DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name);
+	power_well->desc->ops->enable(dev_priv, power_well);
 	power_well->hw_enabled = true;
 }
 
 static void intel_power_well_disable(struct drm_i915_private
 *dev_priv,
 				     struct i915_power_well
 *power_well)
 {
-	DRM_DEBUG_KMS("disabling %s\n", power_well->name);
+	DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name);

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -2

 	power_well->hw_enabled = false;
-	power_well->ops->disable(dev_priv, power_well);
+	power_well->desc->ops->disable(dev_priv, power_well);
 }
 
 static void intel_power_well_get(struct drm_i915_private *dev_priv,

@@ -183,7 +183,7 @@ static void intel_power_well_put(struct
 drm_i915_private *dev_priv,
 				 struct i915_power_well *power_well)
 {
 	WARN(!power_well->count, "Use count on power well %s is
 already zero",
-	     power_well->name);
+	     power_well->desc->name);
 

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	if (!--power_well->count)
 		intel_power_well_disable(dev_priv, power_well);

@@ -213,7 +213,7 @@ bool __intel_display_power_is_enabled(struct
 drm_i915_private *dev_priv,
 	is_enabled = true;
 
 	for_each_power_domain_well_rev(dev_priv, power_well,
 BIT_ULL(domain)) {
-		if (power_well->always_on)
+		if (power_well->desc->always_on)
 			continue;

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		if (!power_well->hw_enabled) {

@@ -323,7 +323,7 @@ static void hsw_power_well_pre_disable(struct
 drm_i915_private *dev_priv,
 static void hsw_wait_for_power_well_enable(struct drm_i915_private
 *dev_priv,
 					   struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id id = power_well->id;
+	enum i915_power_well_id id = power_well->desc->id;

/* Timeout for PW1:10 us, AUX:not specified, other PWs:20
us. */

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	WARN_ON(intel_wait_for_register(dev_priv,

@@ -350,7 +350,7 @@ static u32 hsw_power_well_requesters(struct
 drm_i915_private *dev_priv,
 static void hsw_wait_for_power_well_disable(struct drm_i915_private
 *dev_priv,
 					    struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id id = power_well->id;
+	enum i915_power_well_id id = power_well->desc->id;

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	bool disabled;
 	u32 reqs;

@@ -370,7 +370,7 @@ static void
 hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
 		return;
 
 	DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d
 debug:%d)\n",
-		      power_well->name,
+		      power_well->desc->name,
 		      !!(reqs & 1), !!(reqs & 2), !!(reqs & 4),

!!(reqs & 8));
}

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -2

@@ -386,8 +386,8 @@ static void gen9_wait_for_power_well_fuses(struct
 drm_i915_private *dev_priv,
 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 				  struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id id = power_well->id;
-	bool wait_fuses = power_well->hsw.has_fuses;
+	enum i915_power_well_id id = power_well->desc->id;
+	bool wait_fuses = power_well->desc->hsw.has_fuses;
 	enum skl_power_gate uninitialized_var(pg);

drivers/gpu/drm/i915/intel_runtime_pm.c +4 -4

 	u32 val;

@@ -421,17 +421,19 @@ static void hsw_power_well_enable(struct
 drm_i915_private *dev_priv,
 	if (wait_fuses)
 		gen9_wait_for_power_well_fuses(dev_priv, pg);
 
-	hsw_power_well_post_enable(dev_priv, power_well-
 >hsw.irq_pipe_mask,
-				   power_well->hsw.has_vga);
+	hsw_power_well_post_enable(dev_priv,
+				   power_well->desc-
 >hsw.irq_pipe_mask,
+				   power_well->desc->hsw.has_vga);
 }
 
 static void hsw_power_well_disable(struct drm_i915_private
 *dev_priv,
 				   struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id id = power_well->id;
+	enum i915_power_well_id id = power_well->desc->id;
 	u32 val;
 
-	hsw_power_well_pre_disable(dev_priv, power_well-

Quoted 1 line

hsw.irq_pipe_mask);

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -0

+	hsw_power_well_pre_disable(dev_priv,
+				   power_well->desc-

Quoted 1 line

hsw.irq_pipe_mask);

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
 	I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),

@@ -445,7 +447,7 @@ static void
 icl_combo_phy_aux_power_well_enable(struct drm_i915_private
 *dev_priv,
 				    struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id id = power_well->id;
+	enum i915_power_well_id id = power_well->desc->id;
 	enum port port = ICL_AUX_PW_TO_PORT(id);

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	u32 val;

@@ -462,7 +464,7 @@ static void
 icl_combo_phy_aux_power_well_disable(struct drm_i915_private
 *dev_priv,
 				     struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id id = power_well->id;
+	enum i915_power_well_id id = power_well->desc->id;
 	enum port port = ICL_AUX_PW_TO_PORT(id);

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	u32 val;

@@ -484,7 +486,7 @@ icl_combo_phy_aux_power_well_disable(struct
 drm_i915_private *dev_priv,
 static bool hsw_power_well_enabled(struct drm_i915_private
 *dev_priv,
 				   struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id id = power_well->id;
+	enum i915_power_well_id id = power_well->desc->id;

u32 mask = HSW_PWR_WELL_CTL_REQ(id) |
HSW_PWR_WELL_CTL_STATE(id);

return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) ==
mask;

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

@@ -723,7 +725,7 @@ static void skl_enable_dc6(struct
 drm_i915_private *dev_priv)
 static void hsw_power_well_sync_hw(struct drm_i915_private
 *dev_priv,
 				   struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id id = power_well->id;
+	enum i915_power_well_id id = power_well->desc->id;

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -2

 	u32 mask = HSW_PWR_WELL_CTL_REQ(id);
 	u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id));

@@ -740,19 +742,19 @@ static void hsw_power_well_sync_hw(struct
 drm_i915_private *dev_priv,
 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private
 *dev_priv,
 					   struct i915_power_well
 *power_well)
 {
-	bxt_ddi_phy_init(dev_priv, power_well->bxt.phy);
+	bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
 }
 
 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private
 *dev_priv,
 					    struct i915_power_well
 *power_well)
 {
-	bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy);
+	bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
 }
 
 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private
 *dev_priv,

struct i915_power_well
*power_well)
{

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -1

-	return bxt_ddi_phy_is_enabled(dev_priv, power_well-

Quoted 1 line

bxt.phy);

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -0

+	return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc-

Quoted 1 line

bxt.phy);

}

static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private
*dev_priv)

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -2

@@ -761,16 +763,17 @@ static void
 bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 
 	power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 	if (power_well->count > 0)
-		bxt_ddi_phy_verify_state(dev_priv, power_well-
 >bxt.phy);
+		bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
 >bxt.phy);
 
 	power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 	if (power_well->count > 0)
-		bxt_ddi_phy_verify_state(dev_priv, power_well-
 >bxt.phy);
+		bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
 >bxt.phy);
 
 	if (IS_GEMINILAKE(dev_priv)) {
 		power_well = lookup_power_well(dev_priv,

GLK_DPIO_CMN_C);

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -1

 		if (power_well->count > 0)
-			bxt_ddi_phy_verify_state(dev_priv,

power_well->bxt.phy);

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -0

+			bxt_ddi_phy_verify_state(dev_priv,
+						 power_well->desc-

Quoted 1 line

bxt.phy);

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	}
 }

@@ -869,7 +872,7 @@ static void i830_pipes_power_well_sync_hw(struct
 drm_i915_private *dev_priv,
 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 			       struct i915_power_well *power_well,
 bool enable)
 {
-	enum i915_power_well_id power_well_id = power_well->id;
+	enum i915_power_well_id power_well_id = power_well->desc-
 >id;

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	u32 mask;
 	u32 state;
 	u32 ctrl;

@@ -917,7 +920,7 @@ static void vlv_power_well_disable(struct
 drm_i915_private *dev_priv,
 static bool vlv_power_well_enabled(struct drm_i915_private
 *dev_priv,
 				   struct i915_power_well
 *power_well)
 {
-	enum i915_power_well_id power_well_id = power_well->id;
+	enum i915_power_well_id power_well_id = power_well->desc-

Quoted 1 line

id;

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	bool enabled = false;
 	u32 mask;
 	u32 state;

@@ -1107,7 +1110,7 @@ lookup_power_well(struct drm_i915_private
 *dev_priv,
 		struct i915_power_well *power_well;
 
 		power_well = &power_domains->power_wells[i];
-		if (power_well->id == power_well_id)
+		if (power_well->desc->id == power_well_id)
 			return power_well;
 	}

@@ -1146,7 +1149,7 @@ static void assert_chv_phy_status(struct
 drm_i915_private *dev_priv)
 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY1

, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0, 1));

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

-	if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
+	if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
 		phy_status |= PHY_POWERGOOD(DPIO_PHY0);
 
 		/* this assumes override is only used to enable

lanes */

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

@@ -1187,7 +1190,7 @@ static void assert_chv_phy_status(struct
 drm_i915_private *dev_priv)
 			phy_status |=
 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
 	}
 
-	if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
+	if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
 		phy_status |= PHY_POWERGOOD(DPIO_PHY1);

/* this assumes override is only used to enable
lanes */

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -1

@@ -1231,10 +1234,10 @@ static void
 chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 	enum pipe pipe;
 	uint32_t tmp;
 
-	WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC

&&

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

-		     power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
+	WARN_ON_ONCE(power_well->desc->id !=

PUNIT_POWER_WELL_DPIO_CMN_BC &&

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -0

+		     power_well->desc->id !=

PUNIT_POWER_WELL_DPIO_CMN_D);

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -2

-	if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+	if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 		pipe = PIPE_A;
 		phy = DPIO_PHY0;
 	} else {

@@ -1262,7 +1265,7 @@ static void
 chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 		DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
 
-	if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+	if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 		tmp = vlv_dpio_read(dev_priv, pipe,
 _CHV_CMN_DW6_CH1);

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -0

 		tmp |= DPIO_DYNPWRDOWNEN_CH1;
 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1,

tmp);

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -1

@@ -1293,10 +1296,10 @@ static void
 chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 {
 	enum dpio_phy phy;
 
-	WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC

&&

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

-		     power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
+	WARN_ON_ONCE(power_well->desc->id !=

PUNIT_POWER_WELL_DPIO_CMN_BC &&

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -0

+		     power_well->desc->id !=

PUNIT_POWER_WELL_DPIO_CMN_D);

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -2

-	if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+	if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 		phy = DPIO_PHY0;
 		assert_pll_disabled(dev_priv, PIPE_A);
 		assert_pll_disabled(dev_priv, PIPE_B);

@@ -2051,7 +2054,7 @@ static const struct i915_power_well_ops
 chv_dpio_cmn_power_well_ops = {
 	.is_enabled = vlv_power_well_enabled,
 };
 
-static struct i915_power_well i9xx_always_on_power_well[] = {
+static const struct i915_power_well_desc i9xx_always_on_power_well[]
 = {
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "always-on",
 		.always_on = 1,

@@ -2068,7 +2071,7 @@ static const struct i915_power_well_ops
 i830_pipes_power_well_ops = {
 	.is_enabled = i830_pipes_power_well_enabled,
 };
 
-static struct i915_power_well i830_power_wells[] = {
+static const struct i915_power_well_desc i830_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.always_on = 1,

@@ -2105,7 +2108,7 @@ static const struct i915_power_well_ops
 bxt_dpio_cmn_power_well_ops = {
 	.is_enabled = bxt_dpio_cmn_power_well_enabled,
 };
 
-static struct i915_power_well hsw_power_wells[] = {
+static const struct i915_power_well_desc hsw_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.always_on = 1,

@@ -2124,7 +2127,7 @@ static struct i915_power_well hsw_power_wells[]
 = {
 	},
 };
 
-static struct i915_power_well bdw_power_wells[] = {
+static const struct i915_power_well_desc bdw_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.always_on = 1,

@@ -2165,7 +2168,7 @@ static const struct i915_power_well_ops
 vlv_dpio_power_well_ops = {
 	.is_enabled = vlv_power_well_enabled,
 };
 
-static struct i915_power_well vlv_power_wells[] = {
+static const struct i915_power_well_desc vlv_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.always_on = 1,

@@ -2223,7 +2226,7 @@ static struct i915_power_well vlv_power_wells[]
 = {
 	},
 };
 
-static struct i915_power_well chv_power_wells[] = {
+static const struct i915_power_well_desc chv_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -0

 		.always_on = 1,

@@ -2263,12 +2266,12 @@ bool

intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	bool ret;
 
 	power_well = lookup_power_well(dev_priv, power_well_id);
-	ret = power_well->ops->is_enabled(dev_priv, power_well);
+	ret = power_well->desc->ops->is_enabled(dev_priv,

power_well);

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -2

 	return ret;
 }
 
-static struct i915_power_well skl_power_wells[] = {
+static const struct i915_power_well_desc skl_power_wells[] = {
 	{
 		.name = "always-on",
 		.always_on = 1,

@@ -2336,7 +2339,7 @@ static struct i915_power_well skl_power_wells[]
 = {
 	},
 };
 
-static struct i915_power_well bxt_power_wells[] = {
+static const struct i915_power_well_desc bxt_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.always_on = 1,

@@ -2390,7 +2393,7 @@ static struct i915_power_well bxt_power_wells[]
 = {
 	},
 };
 
-static struct i915_power_well glk_power_wells[] = {
+static const struct i915_power_well_desc glk_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.always_on = 1,

@@ -2490,7 +2493,7 @@ static struct i915_power_well glk_power_wells[]
 = {
 	},
 };
 
-static struct i915_power_well cnl_power_wells[] = {
+static const struct i915_power_well_desc cnl_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.always_on = 1,

@@ -2594,7 +2597,7 @@ static const struct i915_power_well_ops
 icl_combo_phy_aux_power_well_ops = {
 	.is_enabled = hsw_power_well_enabled,
 };
 
-static struct i915_power_well icl_power_wells[] = {
+static const struct i915_power_well_desc icl_power_wells[] = {
 	{
 		.name = "always-on",

drivers/gpu/drm/i915/intel_runtime_pm.c +18 -7

 		.always_on = 1,

@@ -2805,26 +2808,37 @@ static uint32_t get_allowed_dc_mask(const
 struct drm_i915_private *dev_priv,
 	return mask;
 }
 
-static void assert_power_well_ids_unique(struct drm_i915_private
 *dev_priv)
+static int
+__set_power_wells(struct i915_power_domains *power_domains,
+		  const struct i915_power_well_desc
 *power_well_descs,
+		  int power_well_count)
 {
-	struct i915_power_domains *power_domains = &dev_priv-
 >power_domains;
-	u64 power_well_ids;
+	u64 power_well_ids = 0;
 	int i;
 
-	power_well_ids = 0;
-	for (i = 0; i < power_domains->power_well_count; i++) {
-		enum i915_power_well_id id = power_domains-
 >power_wells[i].id;
+	power_domains->power_well_count = power_well_count;
+	power_domains->power_wells = kcalloc(power_well_count,
+					    sizeof(*power_domains-
 >power_wells),
+					    GFP_KERNEL);
+	if (!power_domains->power_wells)
+		return -ENOMEM;
+
+	for (i = 0; i < power_well_count; i++) {
+		enum i915_power_well_id id = power_well_descs[i].id;
+
+		power_domains->power_wells[i].desc =
 &power_well_descs[i];
 
 		WARN_ON(id >= sizeof(power_well_ids) * 8);
 		WARN_ON(power_well_ids & BIT_ULL(id));
 		power_well_ids |= BIT_ULL(id);
 	}
+
+	return 0;
 }
 
-#define set_power_wells(power_domains, __power_wells) ({		

\

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -1

-	(power_domains)->power_wells = (__power_wells);		

	\

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -1

-	(power_domains)->power_well_count =

ARRAY_SIZE(__power_wells); \

drivers/gpu/drm/i915/intel_runtime_pm.c +3 -1

-})
+#define set_power_wells(power_domains, __power_well_descs) \
+	__set_power_wells(power_domains, __power_well_descs, \
+			  ARRAY_SIZE(__power_well_descs))
 
 /**
  * intel_power_domains_init - initializes the power domain

structures

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -0

@@ -2836,6 +2850,7 @@ static void assert_power_well_ids_unique(struct
 drm_i915_private *dev_priv)
 int intel_power_domains_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv-
 >power_domains;
+	int err;
 

drivers/gpu/drm/i915/intel_runtime_pm.c +4 -4

 	i915_modparams.disable_power_well =
 		sanitize_disable_power_well_option(dev_priv,

@@ -2852,15 +2867,15 @@ int intel_power_domains_init(struct
 drm_i915_private *dev_priv)
 	 * the disabling order is reversed.
 	 */
 	if (IS_ICELAKE(dev_priv)) {
-		set_power_wells(power_domains, icl_power_wells);
+		err = set_power_wells(power_domains,
 icl_power_wells);
 	} else if (IS_HASWELL(dev_priv)) {
-		set_power_wells(power_domains, hsw_power_wells);
+		err = set_power_wells(power_domains,
 hsw_power_wells);
 	} else if (IS_BROADWELL(dev_priv)) {
-		set_power_wells(power_domains, bdw_power_wells);
+		err = set_power_wells(power_domains,
 bdw_power_wells);
 	} else if (IS_GEN9_BC(dev_priv)) {
-		set_power_wells(power_domains, skl_power_wells);
+		err = set_power_wells(power_domains,
 skl_power_wells);

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 	} else if (IS_CANNONLAKE(dev_priv)) {
-		set_power_wells(power_domains, cnl_power_wells);
+		err = set_power_wells(power_domains,

cnl_power_wells);

drivers/gpu/drm/i915/intel_runtime_pm.c +17 -8

 		/*
 		 * DDI and Aux IO are getting enabled for all ports

@@ -2872,22 +2887,31 @@ int intel_power_domains_init(struct
 drm_i915_private *dev_priv)
 			power_domains->power_well_count -= 2;
 
 	} else if (IS_BROXTON(dev_priv)) {
-		set_power_wells(power_domains, bxt_power_wells);
+		err = set_power_wells(power_domains,
 bxt_power_wells);
 	} else if (IS_GEMINILAKE(dev_priv)) {
-		set_power_wells(power_domains, glk_power_wells);
+		err = set_power_wells(power_domains,
 glk_power_wells);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
-		set_power_wells(power_domains, chv_power_wells);
+		err = set_power_wells(power_domains,
 chv_power_wells);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
-		set_power_wells(power_domains, vlv_power_wells);
+		err = set_power_wells(power_domains,
 vlv_power_wells);
 	} else if (IS_I830(dev_priv)) {
-		set_power_wells(power_domains, i830_power_wells);
+		err = set_power_wells(power_domains,
 i830_power_wells);
 	} else {
-		set_power_wells(power_domains,
 i9xx_always_on_power_well);
+		err = set_power_wells(power_domains,
 i9xx_always_on_power_well);
 	}
 
-	assert_power_well_ids_unique(dev_priv);
+	return err;
+}
 
-	return 0;
+/**
+ * intel_power_domains_cleanup - clean up power domains resources
+ * @dev_priv: i915 device instance
+ *
+ * Release any resources acquired by intel_power_domains_init()
+ */
+void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
+{
+	kfree(dev_priv->power_domains.power_wells);
 }
 
 static void intel_power_domains_sync_hw(struct drm_i915_private

*dev_priv)

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -3

@@ -2897,9 +2921,9 @@ static void intel_power_domains_sync_hw(struct
 drm_i915_private *dev_priv)
 
 	mutex_lock(&power_domains->lock);
 	for_each_power_well(dev_priv, power_well) {
-		power_well->ops->sync_hw(dev_priv, power_well);
-		power_well->hw_enabled = power_well->ops-
 >is_enabled(dev_priv,
-								    
 power_well);
+		power_well->desc->ops->sync_hw(dev_priv,

power_well);

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -0

+		power_well->hw_enabled =
+			power_well->desc->ops->is_enabled(dev_priv,

power_well);

drivers/gpu/drm/i915/intel_runtime_pm.c +5 -5

 	}
 	mutex_unlock(&power_domains->lock);
 }

@@ -3398,7 +3422,7 @@ static void chv_phy_control_init(struct
 drm_i915_private *dev_priv)
 	 * override and set the lane powerdown bits accding to the
 	 * current lane status.
 	 */
-	if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
+	if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
 		uint32_t status = I915_READ(DPLL(PIPE_A));
 		unsigned int mask;

@@ -3429,7 +3453,7 @@ static void chv_phy_control_init(struct
 drm_i915_private *dev_priv)
 		dev_priv->chv_phy_assert[DPIO_PHY0] = true;
 	}
 
-	if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
+	if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
 		uint32_t status = I915_READ(DPIO_PHY_STATUS);
 		unsigned int mask;

@@ -3465,15 +3489,15 @@ static void vlv_cmnlane_wa(struct
 drm_i915_private *dev_priv)
 		lookup_power_well(dev_priv,
 PUNIT_POWER_WELL_DISP2D);
 
 	/* If the display might be already active skip this */
-	if (cmn->ops->is_enabled(dev_priv, cmn) &&
-	    disp2d->ops->is_enabled(dev_priv, disp2d) &&
+	if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
+	    disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
 	    I915_READ(DPIO_CTL) & DPIO_CMNRST)
 		return;
 
 	DRM_DEBUG_KMS("toggling display PHY side reset\n");
 
 	/* cmnlane needs DPLL registers */
-	disp2d->ops->enable(dev_priv, disp2d);
+	disp2d->desc->ops->enable(dev_priv, disp2d);
 

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -0

 	/*
 	 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:

@@ -3482,7 +3506,7 @@ static void vlv_cmnlane_wa(struct
 drm_i915_private *dev_priv)
 	 * Simply ungating isn't enough to reset the PHY enough to

get

drivers/gpu/drm/i915/intel_runtime_pm.c +3 -3

 	 * ports and lanes running.
 	 */
-	cmn->ops->disable(dev_priv, cmn);
+	cmn->desc->ops->disable(dev_priv, cmn);
 }
 
 /**

@@ -3598,9 +3622,9 @@ static void
 intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
 		enum intel_display_power_domain domain;
 
 		DRM_DEBUG_DRIVER("%-25s %d\n",
-				 power_well->name, power_well-
 >count);
+				 power_well->desc->name, power_well-
 >count);
 
-		for_each_power_domain(domain, power_well->domains)
+		for_each_power_domain(domain, power_well->desc-

Quoted 1 line

domains)

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -0

 			DRM_DEBUG_DRIVER("  %-23s %d\n",
 					 intel_display_power_domain_

str(domain),
power_domains-

Quoted 1 line

domain_use_count[domain]);

drivers/gpu/drm/i915/intel_runtime_pm.c +4 -3

@@ -3636,22 +3660,25 @@ void intel_power_domains_verify_state(struct
 drm_i915_private *dev_priv)
 		 * and PW1 power wells) are under FW control, so
 ignore them,
 		 * since their state can change asynchronously.
 		 */
-		if (!power_well->domains)
+		if (!power_well->desc->domains)
 			continue;
 
-		enabled = power_well->ops->is_enabled(dev_priv,
 power_well);
-		if ((power_well->count || power_well->always_on) !=
 enabled)
+		enabled = power_well->desc->ops-
 >is_enabled(dev_priv,
+							    power_we
 ll);
+		if ((power_well->count || power_well->desc-

Quoted 1 line

always_on) !=

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -0

+		    enabled)
 			DRM_ERROR("power well %s state mismatch

(refcount %d/enabled %d)",

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -1

-				  power_well->name, power_well-

Quoted 1 line

count, enabled);

drivers/gpu/drm/i915/intel_runtime_pm.c +3 -1

+				  power_well->desc->name,
+				  power_well->count, enabled);
 
 		domains_count = 0;
-		for_each_power_domain(domain, power_well->domains)
+		for_each_power_domain(domain, power_well->desc-

Quoted 1 line

domains)

domains_count += power_domains-

Quoted 1 line

domain_use_count[domain];

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -0

 		if (power_well->count != domains_count) {
 			DRM_ERROR("power well %s refcount/domain

refcount mismatch "
"(refcount %d/domains refcount
%d)\n",

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -1

-				  power_well->name, power_well-

Quoted 1 line

count,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -0

+				  power_well->desc->name,

power_well->count,

Now that we removed dependence on the power well IDs to determine the control register and request/status flag offsets the only purpose of power well IDs is to look up power wells directly bypassing the power domains framework. However this direct lookup isn't needed for most of
the exisiting power wells and hopefully won't be needed for any new power wells in the future. To make maintenance of the power well ID enum
easier, don't require a unique ID for each power well, only if it's necessary. Remove the IDs becoming redundant this way and assign to all
the corresponding power wells a new DISP_PW_ID_NONE ID.

After the previous two patches the IDs don't need to have a fixed value,
so remove the explicit initializers and adjust the enum's code comment
accordingly.

v2:
- Keep required ID assignments for HSW_DISP_PW_GLOBAL and ICL_DISP_PW_2.
(Paulo)

Cc Ville Syrjala <[email protected]>

Cc Paulo Zanoni <[email protected]>

Cc Jani Nikula <[email protected]>

Signed-off-by Imre Deak <[email protected]>

---
 drivers/gpu/drm/i915/i915_reg.h         | 118 ++++----------------
----------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 123 ++++++++++++++++----
------------
 2 files changed, 76 insertions(+), 165 deletions(-)

drivers/gpu/drm/i915/i915_reg.h +0 -1

index 4f5eb49934b4..4568adc8369a 100644
@@ -1029,117 +1029,25 @@ static inline bool
 i915_mmio_reg_valid(i915_reg_t reg)
 /*
  * i915_power_well_id:
  *
- * Platform specific IDs used to look up power wells and - except

for custom
- * power wells - to define request/status register flag bit positions. As such
- * the set of IDs on a given platform must be unique and except for custom
- * power wells their value must stay fixed.
+ * IDs used to look up power wells. Power wells accessed directly bypassing
+ * the power domains framework must be assigned a unique ID. The rest of power
+ * wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {

drivers/gpu/drm/i915/i915_reg.h +0 -28

-	/*
-	 * I830
-	 *  - custom power well
-	 */
-	I830_DISP_PW_PIPES = 0,
-
-	/*
-	 * VLV/CHV
-	 *  - PUNIT_REG_PWRGT_CTRL (bit: id*2),
-	 *    PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
-	 */
-	PUNIT_POWER_WELL_RENDER			= 0,
-	PUNIT_POWER_WELL_MEDIA			= 1,
-	PUNIT_POWER_WELL_DISP2D			= 3,
-	PUNIT_POWER_WELL_DPIO_CMN_BC		= 5,
-	PUNIT_POWER_WELL_DPIO_TX_B_LANES_01	= 6,
-	PUNIT_POWER_WELL_DPIO_TX_B_LANES_23	= 7,
-	PUNIT_POWER_WELL_DPIO_TX_C_LANES_01	= 8,
-	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
-	PUNIT_POWER_WELL_DPIO_RX0		= 10,
-	PUNIT_POWER_WELL_DPIO_RX1		= 11,
-	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
-	/*  - custom power well */
-	CHV_DISP_PW_PIPE_A,			/* 13 */
-
-	/*
-	 * HSW/BDW
-	 *  - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit:

id*2+1)

drivers/gpu/drm/i915/i915_reg.h +0 -6

-	 */
-	HSW_DISP_PW_GLOBAL = 15,
-
-	/*
-	 * GEN9+
-	 *  - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit:

id*2+1)

drivers/gpu/drm/i915/i915_reg.h +10 -67

-	 */
-	SKL_DISP_PW_MISC_IO = 0,
-	SKL_DISP_PW_DDI_A_E,
-	GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
-	CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
-	SKL_DISP_PW_DDI_B,
-	SKL_DISP_PW_DDI_C,
-	SKL_DISP_PW_DDI_D,
-	CNL_DISP_PW_DDI_F = 6,
-
-	GLK_DISP_PW_AUX_A = 8,
-	GLK_DISP_PW_AUX_B,
-	GLK_DISP_PW_AUX_C,
-	CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
-	CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
-	CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
-	CNL_DISP_PW_AUX_D,
-	CNL_DISP_PW_AUX_F,
-
-	SKL_DISP_PW_1 = 14,
+	DISP_PW_ID_NONE,
+
+	PUNIT_POWER_WELL_DISP2D,
+	PUNIT_POWER_WELL_DPIO_CMN_BC,
+	PUNIT_POWER_WELL_DPIO_CMN_D,
+	HSW_DISP_PW_GLOBAL,
+	SKL_DISP_PW_MISC_IO,
+	SKL_DISP_PW_1,
 	SKL_DISP_PW_2,
-
-	/* - custom power wells */
 	BXT_DPIO_CMN_A,
 	BXT_DPIO_CMN_BC,
-	GLK_DPIO_CMN_C,			/* 18 */
-
-	/*
-	 * GEN11+
-	 *  - _HSW_PWR_WELL_CTL1-4
-	 *    (status bit: (id&15)*2, req bit:(id&15)*2+1)
-	 */
-	ICL_DISP_PW_1 = 0,
+	GLK_DPIO_CMN_C,
+	ICL_DISP_PW_1,
 	ICL_DISP_PW_2,
-	ICL_DISP_PW_3,
-	ICL_DISP_PW_4,
-
-	/*
-	 *  - _HSW_PWR_WELL_CTL_AUX1/2/4
-	 *    (status bit: (id&15)*2, req bit:(id&15)*2+1)
-	 */
-	ICL_DISP_PW_AUX_A = 16,
-	ICL_DISP_PW_AUX_B,
-	ICL_DISP_PW_AUX_C,
-	ICL_DISP_PW_AUX_D,
-	ICL_DISP_PW_AUX_E,
-	ICL_DISP_PW_AUX_F,
-
-	ICL_DISP_PW_AUX_TBT1 = 24,
-	ICL_DISP_PW_AUX_TBT2,
-	ICL_DISP_PW_AUX_TBT3,
-	ICL_DISP_PW_AUX_TBT4,
-
-	/*
-	 *  - _HSW_PWR_WELL_CTL_DDI1/2/4
-	 *    (status bit: (id&15)*2, req bit:(id&15)*2+1)
-	 */
-	ICL_DISP_PW_DDI_A = 32,
-	ICL_DISP_PW_DDI_B,
-	ICL_DISP_PW_DDI_C,
-	ICL_DISP_PW_DDI_D,
-	ICL_DISP_PW_DDI_E,
-	ICL_DISP_PW_DDI_F,                      /* 37 */
-
-	/*
-	 * Multiple platforms.
-	 * Must start following the highest ID of any platform.
-	 * - custom power wells
-	 */
-	SKL_DISP_PW_DC_OFF = 38,
-	I915_DISP_PW_ALWAYS_ON,
 };
 
 #define PUNIT_REG_PWRGT_CTRL			0x60

drivers/gpu/drm/i915/intel_runtime_pm.c +4 -4

index 626774f86cd2..6aec980cea07 100644
@@ -2067,7 +2067,7 @@ static const struct i915_power_well_desc
 i9xx_always_on_power_well[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 };

@@ -2084,13 +2084,13 @@ static const struct i915_power_well_desc
 i830_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{
 		.name = "pipes",
 		.domains = I830_PIPES_POWER_DOMAINS,
 		.ops = &i830_pipes_power_well_ops,
-		.id = I830_DISP_PW_PIPES,
+		.id = DISP_PW_ID_NONE,
 	},
 };

@@ -2128,7 +2128,7 @@ static const struct i915_power_well_desc
 hsw_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "display",

@@ -2149,7 +2149,7 @@ static const struct i915_power_well_desc
 bdw_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "display",

@@ -2192,7 +2192,7 @@ static const struct i915_power_well_desc
 vlv_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "display",

@@ -2210,7 +2210,7 @@ static const struct i915_power_well_desc
 vlv_power_wells[] = {
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
-		.id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
+		.id = DISP_PW_ID_NONE,
 		{
 			.vlv.idx =

PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		},

@@ -2222,7 +2222,7 @@ static const struct i915_power_well_desc
 vlv_power_wells[] = {
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
-		.id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
+		.id = DISP_PW_ID_NONE,
 		{
 			.vlv.idx =

PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		},

@@ -2234,7 +2234,7 @@ static const struct i915_power_well_desc
 vlv_power_wells[] = {
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
-		.id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
+		.id = DISP_PW_ID_NONE,
 		{
 			.vlv.idx =

PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		},

@@ -2246,7 +2246,7 @@ static const struct i915_power_well_desc
 vlv_power_wells[] = {
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
-		.id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
+		.id = DISP_PW_ID_NONE,
 		{
 			.vlv.idx =

PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		},

@@ -2268,7 +2268,7 @@ static const struct i915_power_well_desc
 chv_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "display",

@@ -2279,7 +2279,7 @@ static const struct i915_power_well_desc
 chv_power_wells[] = {
 		 */
 		.domains = CHV_DISPLAY_POWER_DOMAINS,
 		.ops = &chv_pipe_power_well_ops,
-		.id = CHV_DISP_PW_PIPE_A,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "dpio-common-bc",

@@ -2319,7 +2319,7 @@ static const struct i915_power_well_desc
 skl_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "power well 1",

@@ -2348,7 +2348,7 @@ static const struct i915_power_well_desc
 skl_power_wells[] = {
 		.name = "DC off",
 		.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
-		.id = SKL_DISP_PW_DC_OFF,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "power well 2",

@@ -2367,7 +2367,7 @@ static const struct i915_power_well_desc
 skl_power_wells[] = {
 		.name = "DDI A/E IO power well",
 		.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_A_E,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,

@@ -2377,7 +2377,7 @@ static const struct i915_power_well_desc
 skl_power_wells[] = {
 		.name = "DDI B IO power well",
 		.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_B,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_B,

@@ -2387,7 +2387,7 @@ static const struct i915_power_well_desc
 skl_power_wells[] = {
 		.name = "DDI C IO power well",
 		.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_C,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_C,

@@ -2397,7 +2397,7 @@ static const struct i915_power_well_desc
 skl_power_wells[] = {
 		.name = "DDI D IO power well",
 		.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_D,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_D,

@@ -2411,7 +2411,7 @@ static const struct i915_power_well_desc
 bxt_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "power well 1",

@@ -2428,7 +2428,7 @@ static const struct i915_power_well_desc
 bxt_power_wells[] = {
 		.name = "DC off",
 		.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
-		.id = SKL_DISP_PW_DC_OFF,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "power well 2",

@@ -2469,7 +2469,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "power well 1",

@@ -2487,7 +2487,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.name = "DC off",
 		.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
-		.id = SKL_DISP_PW_DC_OFF,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "power well 2",

@@ -2533,7 +2533,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.name = "AUX A",
 		.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = GLK_DISP_PW_AUX_A,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = GLK_PW_CTL_IDX_AUX_A,

@@ -2543,7 +2543,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.name = "AUX B",
 		.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = GLK_DISP_PW_AUX_B,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = GLK_PW_CTL_IDX_AUX_B,

@@ -2553,7 +2553,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.name = "AUX C",
 		.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = GLK_DISP_PW_AUX_C,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = GLK_PW_CTL_IDX_AUX_C,

@@ -2563,7 +2563,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.name = "DDI A IO power well",
 		.domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = GLK_DISP_PW_DDI_A,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = GLK_PW_CTL_IDX_DDI_A,

@@ -2573,7 +2573,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.name = "DDI B IO power well",
 		.domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_B,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_B,

@@ -2583,7 +2583,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.name = "DDI C IO power well",
 		.domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_C,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_C,

@@ -2597,7 +2597,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "power well 1",

@@ -2615,7 +2615,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "AUX A",
 		.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_AUX_A,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = GLK_PW_CTL_IDX_AUX_A,

@@ -2625,7 +2625,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "AUX B",
 		.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_AUX_B,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = GLK_PW_CTL_IDX_AUX_B,

@@ -2635,7 +2635,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "AUX C",
 		.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_AUX_C,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = GLK_PW_CTL_IDX_AUX_C,

@@ -2645,7 +2645,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "AUX D",
 		.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_AUX_D,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = CNL_PW_CTL_IDX_AUX_D,

@@ -2655,7 +2655,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "DC off",
 		.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
-		.id = SKL_DISP_PW_DC_OFF,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		.name = "power well 2",

@@ -2674,7 +2674,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "DDI A IO power well",
 		.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_DDI_A,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = GLK_PW_CTL_IDX_DDI_A,

@@ -2684,7 +2684,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "DDI B IO power well",
 		.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_B,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_B,

@@ -2694,7 +2694,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "DDI C IO power well",
 		.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_C,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_C,

@@ -2704,7 +2704,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "DDI D IO power well",
 		.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_DDI_D,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = SKL_PW_CTL_IDX_DDI_D,

@@ -2714,7 +2714,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "DDI F IO power well",
 		.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_DDI_F,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = CNL_PW_CTL_IDX_DDI_F,

@@ -2724,7 +2724,7 @@ static const struct i915_power_well_desc
 cnl_power_wells[] = {
 		.name = "AUX F",
 		.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_AUX_F,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = CNL_PW_CTL_IDX_AUX_F,

@@ -2757,7 +2757,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.id = I915_DISP_PW_ALWAYS_ON,
+		.id = DISP_PW_ID_NONE,
 	},
 	{

drivers/gpu/drm/i915/intel_runtime_pm.c +2 -2

 		.name = "power well 1",

@@ -2786,13 +2786,13 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "DC off",
 		.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
-		.id = SKL_DISP_PW_DC_OFF,
+		.id = DISP_PW_ID_NONE,
 	},
 	{
 		.name = "power well 3",
 		.domains = ICL_PW_3_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_3,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_PW_3,

@@ -2805,7 +2805,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "DDI A IO",
 		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_DDI_A,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_ddi_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,

@@ -2815,7 +2815,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "DDI B IO",
 		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_DDI_B,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_ddi_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,

@@ -2825,7 +2825,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "DDI C IO",
 		.domains = ICL_DDI_IO_C_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_DDI_C,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_ddi_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,

@@ -2835,7 +2835,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "DDI D IO",
 		.domains = ICL_DDI_IO_D_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_DDI_D,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_ddi_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_DDI_D,

@@ -2845,7 +2845,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "DDI E IO",
 		.domains = ICL_DDI_IO_E_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_DDI_E,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_ddi_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_DDI_E,

@@ -2855,7 +2855,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "DDI F IO",
 		.domains = ICL_DDI_IO_F_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_DDI_F,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_ddi_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_DDI_F,

@@ -2865,7 +2865,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX A",
 		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
 		.ops = &icl_combo_phy_aux_power_well_ops,
-		.id = ICL_DISP_PW_AUX_A,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,

@@ -2875,7 +2875,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX B",
 		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
 		.ops = &icl_combo_phy_aux_power_well_ops,
-		.id = ICL_DISP_PW_AUX_B,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,

@@ -2885,7 +2885,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX C",
 		.domains = ICL_AUX_C_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_AUX_C,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,

@@ -2895,7 +2895,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX D",
 		.domains = ICL_AUX_D_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_AUX_D,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_D,

@@ -2905,7 +2905,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX E",
 		.domains = ICL_AUX_E_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_AUX_E,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_E,

@@ -2915,7 +2915,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX F",
 		.domains = ICL_AUX_F_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_AUX_F,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_F,

@@ -2925,7 +2925,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX TBT1",
 		.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_AUX_TBT1,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,

@@ -2935,7 +2935,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX TBT2",
 		.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_AUX_TBT2,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,

@@ -2945,7 +2945,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX TBT3",
 		.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_AUX_TBT3,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,

@@ -2955,7 +2955,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "AUX TBT4",
 		.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_AUX_TBT4,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,

@@ -2965,7 +2965,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "power well 4",
 		.domains = ICL_PW_4_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_4,
+		.id = DISP_PW_ID_NONE,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +3 -0

 			.hsw.idx = ICL_PW_CTL_IDX_PW_4,

@@ -3054,6 +3054,9 @@ __set_power_wells(struct i915_power_domains
 *power_domains,
 
 		power_domains->power_wells[i].desc =
 &power_well_descs[i];
 
+		if (id == DISP_PW_ID_NONE)
+			continue;
+
 		WARN_ON(id >= sizeof(power_well_ids) * 8);

There is no need for separate IDs for power wells on a new platform with
the same functionality as an other power well on a previous platform, we
can just reuse the ID from the previous platform. This is only possible
after the previous patches where we removed dependence on the actual enum values.

v2:
- Keep an ID assigned for the ICL PW#2 power well too. (Paulo)

Cc Ville Syrjala <[email protected]>

Cc Paulo Zanoni <[email protected]>

Cc Jani Nikula <[email protected]>

Signed-off-by Imre Deak <[email protected]>

---
 drivers/gpu/drm/i915/i915_reg.h         |  3 ---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++-------
 2 files changed, 7 insertions(+), 10 deletions(-)

drivers/gpu/drm/i915/i915_reg.h +0 -3

index ef1fa5054e88..77b031874ee3 100644
@@ -1045,9 +1045,6 @@ enum i915_power_well_id {
 	SKL_DISP_PW_MISC_IO,
 	SKL_DISP_PW_1,
 	SKL_DISP_PW_2,
-	BXT_DPIO_CMN_BC,
-	ICL_DISP_PW_1,
-	ICL_DISP_PW_2,
 };
 
 #define PUNIT_REG_PWRGT_CTRL			0x60

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

index ae08f7824204..810695a71cc8 100644
@@ -772,7 +772,7 @@ static void bxt_verify_ddi_phy_power_wells(struct
 drm_i915_private *dev_priv)
 	if (power_well->count > 0)
 		bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
 >bxt.phy);
 
-	power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
+	power_well = lookup_power_well(dev_priv,
 VLV_DISP_PW_DPIO_CMN_BC);

drivers/gpu/drm/i915/intel_runtime_pm.c +0 -0

 	if (power_well->count > 0)
 		bxt_ddi_phy_verify_state(dev_priv, power_well->desc-

Quoted 1 line

bxt.phy);

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

@@ -2457,7 +2457,7 @@ static const struct i915_power_well_desc
 bxt_power_wells[] = {
 		.name = "dpio-common-bc",
 		.domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
 		.ops = &bxt_dpio_cmn_power_well_ops,
-		.id = BXT_DPIO_CMN_BC,
+		.id = VLV_DISP_PW_DPIO_CMN_BC,
 		{
 			.bxt.phy = DPIO_PHY0,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		},

@@ -2516,7 +2516,7 @@ static const struct i915_power_well_desc
 glk_power_wells[] = {
 		.name = "dpio-common-b",
 		.domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
 		.ops = &bxt_dpio_cmn_power_well_ops,
-		.id = BXT_DPIO_CMN_BC,
+		.id = VLV_DISP_PW_DPIO_CMN_BC,
 		{
 			.bxt.phy = DPIO_PHY0,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 		},

@@ -2765,7 +2765,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		/* Handled by the DMC firmware */
 		.domains = 0,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_1,
+		.id = SKL_DISP_PW_1,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_PW_1,

@@ -2776,7 +2776,7 @@ static const struct i915_power_well_desc
 icl_power_wells[] = {
 		.name = "power well 2",
 		.domains = ICL_PW_2_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = ICL_DISP_PW_2,
+		.id = SKL_DISP_PW_2,
 		{
 			.hsw.regs = &hsw_power_well_regs,

drivers/gpu/drm/i915/intel_runtime_pm.c +1 -1

 			.hsw.idx = ICL_PW_CTL_IDX_PW_2,

@@ -3575,7 +3575,7 @@ static void icl_display_core_init(struct
 drm_i915_private *dev_priv,
 	 *    The AUX IO power wells will be enabled on demand.
 	 */
 	mutex_lock(&power_domains->lock);
-	well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
 	intel_power_well_enable(dev_priv, well);
 	mutex_unlock(&power_domains->lock);

This is v2 of [1], fixing the issues Paulo noticed.

[1] https://patchwork.freedesktop.org/series/46952/

Cc Chris Wilson <[email protected]>

Cc Ville Syrjala <[email protected]>

Cc Paulo Zanoni <[email protected]>

Cc Jani Nikula <[email protected]>

Cc Rodrigo Vivi <[email protected]>

Imre Deak (10):
drm/i915/icl: Fix power well anonymous union initializers drm/i915: Rename intel_power_domains_fini() to
intel_power_domains_fini_hw()
drm/i915/vlv: Remove redundant power well ID asserts drm/i915: Constify power well descriptors drm/i915/vlv: Use power well CTL IDX instead of ID drm/i915/ddi: Use power well CTL IDX instead of ID drm/i915: Remove redundant power well IDs drm/i915: Make power well ID names more uniform drm/i915: Use existing power well IDs where possible drm/i915/icl: Add missing power gate enums

 drivers/gpu/drm/i915/gvt/handlers.c     |  31 +-
 drivers/gpu/drm/i915/i915_debugfs.c     |   4 +-
 drivers/gpu/drm/i915/i915_drv.c         |  12 +-
 drivers/gpu/drm/i915/i915_drv.h         |  34 +-
 drivers/gpu/drm/i915/i915_reg.h         | 271 +++++------
 drivers/gpu/drm/i915/intel_display.c    |   5 +-
 drivers/gpu/drm/i915/intel_display.h    |   4 +-
 drivers/gpu/drm/i915/intel_drv.h        |   3 +-
 drivers/gpu/drm/i915/intel_hdcp.c       |   6 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 788 +++++++++++++++++++++-----------
 10 files changed, 694 insertions(+), 464 deletions(-)

Signature · 6 lines

2.13.2

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