spi: Add SPI driver for MT76xx SoCs
Subsystems (2)
PATCH 1/1 spi: Add SPI driver for MT76xx SoCs
This patch adds the SPI driver for the MediaTek MT7688 SoC (and derivates). Its been tested on the LinkIt Smart 7688 and the Gardena Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart Gateway additionally with an SPI NAND on CS1.
Note that the SPI controller only supports a max transfer size of 32 bytes. This driver implementes a workaround to enable bigger xfer sizes to speed up the transfer especially for the SPI NAND support.
Signed-off-by Stefan Roese <[email protected]>
Cc Jagan Teki <[email protected]>
--- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/mt76xx_spi.c | 314 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 323 insertions(+) create mode 100644 drivers/spi/mt76xx_spi.c
drivers/spi/Kconfig +8 -0
@@ -109,6 +109,14 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MT76XX_SPI + bool "MediaTek MT76XX SPI driver" + depends on ARCH_MT7620 + help + Enable the MT76XX SPI driver. This driver can be used to access + the SPI NOR flash on platforms embedding these MediaTek + SPI cores. + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" select CLK_ARMADA_3720
drivers/spi/Makefile +1 -0
@@ -32,6 +32,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o
drivers/spi/mt76xx_spi.c new file +314 -0
314 lines not on this page · raw message
Signature · 1 line
2.18.0
PATCH 1/1 spi: Add SPI driver for MT76xx SoCs
Quoted 91 lines · Stefan Roese
This patch adds the SPI driver for the MediaTek MT7688 SoC (and derivates). Its been tested on the LinkIt Smart 7688 and the Gardena Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart Gateway additionally with an SPI NAND on CS1.
Note that the SPI controller only supports a max transfer size of 32 bytes. This driver implementes a workaround to enable bigger xfer sizes to speed up the transfer especially for the SPI NAND support.
Signed-off-by Stefan Roese <[email protected]>Cc Jagan Teki <[email protected]>--- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/mt76xx_spi.c | 314 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 323 insertions(+) create mode 100644 drivers/spi/mt76xx_spi.cdrivers/spi/Kconfig +8
-0@@ -109,6 +109,14 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MT76XX_SPI + bool "MediaTek MT76XX SPI driver" + depends on ARCH_MT7620 + help + Enable the MT76XX SPI driver. This driver can be used to access + the SPI NOR flash on platforms embedding these MediaTek + SPI cores. + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" select CLK_ARMADA_3720drivers/spi/Makefile +1
-0@@ -32,6 +32,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.odrivers/spi/mt76xx_spi.c new file +36
-0@@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright (C) 2018 Stefan Roese <[email protected]> +* +* Derived from the Linux driver version drivers/spi/spi-mt7621.c +* Copyright (C) 2011 Sergiy <[email protected]> +* Copyright (C) 2011-2013 Gabor Juhos <[email protected]> +* Copyright (C) 2014-2015 Felix Fietkau <[email protected]> +*/ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <wait_bit.h> +#include <linux/io.h> + +#define SPI_MSG_SIZE_MAX 32/* SPI message chunk size */ +/* Enough for SPI NAND page read / write with page size 2048 bytes */ +#define SPI_MSG_SIZE_OVERALL (2048 + 16) + +#define MT7621_SPI_TRANS 0x00 +#define MT7621_SPI_TRANS_START BIT(8) +#define MT7621_SPI_TRANS_BUSY BIT(16) + +#define MT7621_SPI_OPCODE 0x04 +#define MT7621_SPI_DATA0 0x08 +#define MT7621_SPI_DATA4 0x18 +#define MT7621_SPI_MASTER 0x28 +#define MT7621_SPI_MOREBUF 0x2c +#define MT7621_SPI_POLAR 0x38 + +#define MT7621_LSB_FIRST BIT(3) +#define MT7621_CPOL BIT(4) +#define MT7621_CPHA BIT(5) + +struct mt7621_spi {
drivers/spi/mt76xx_spi.c line 46
Quoted 10 lines
drivers/spi/mt76xx_spi.c new file +10
-0+void __iomem *base; +unsigned int sys_freq; +u32 data[(SPI_MSG_SIZE_OVERALL /4 ) +1 ]; +int tx_len; +}; + +static const struct udevice_id mt76xx_spi_ids[] = { + { .compatible ="ralink,mt7621-spi" }, + { } +};
This need to move down above U_BOOT_DRIVER
Quoted 7 lines
drivers/spi/mt76xx_spi.c new file +7
-0+ +static inline u32 mt7621_spi_read (struct mt7621_spi *rs,u32 reg) +{ +return ioread32 (rs->base + reg); +} + +static inline void mt7621_spi_write (struct mt7621_spi *rs,u32 reg,u32 val)
drivers/spi/mt76xx_spi.c line 63
Quoted 10 lines
drivers/spi/mt76xx_spi.c new file +10
-0+{ +iowrite32 (val, rs->base + reg); +} + +static void mt7621_spi_reset (struct mt7621_spi *rs,int duplex) +{ +u32 master =mt7621_spi_read (rs,MT7621_SPI_MASTER ); + + master |=7 <<29 ;/* CS control */ + master |=1 <<2 ;/* more_buf_mode */
Proper macros with these numericals?
Quoted 54 lines
drivers/spi/mt76xx_spi.c new file +54
-0+ +mt7621_spi_write (rs,MT7621_SPI_MASTER , master); +} + +static void mt7621_spi_set_cs (struct mt7621_spi *rs,int cs,int enable) +{ +u32 val =0 ; + +debug ("%s: cs#%d -> %s\n" , __func__, cs, enable ?"enable" :"disable" ); +if (enable) + val =BIT (cs); +mt7621_spi_write (rs,MT7621_SPI_POLAR , val); +} + +static int mt7621_spi_set_mode (struct udevice *bus,uint mode) +{ +struct mt7621_spi *rs =dev_get_priv (bus); +u32 reg; + +debug ("%s: mode=0x%08x\n" , __func__, mode); + reg =mt7621_spi_read (rs,MT7621_SPI_MASTER ); + + reg &= ~MT7621_LSB_FIRST ; +if (mode &SPI_LSB_FIRST ) + reg |=MT7621_LSB_FIRST ; + + reg &= ~(MT7621_CPHA |MT7621_CPOL ); +switch (mode & (SPI_CPOL |SPI_CPHA )) { +case SPI_MODE_0 : +break ; +case SPI_MODE_1 : + reg |=MT7621_CPHA ; +break ; +case SPI_MODE_2 : + reg |=MT7621_CPOL ; +break ; +case SPI_MODE_3 : + reg |=MT7621_CPOL |MT7621_CPHA ; +break ; + } +mt7621_spi_write (rs,MT7621_SPI_MASTER , reg); + +return 0 ; +} + +static int mt7621_spi_set_speed (struct udevice *bus,uint speed) +{ +struct mt7621_spi *rs =dev_get_priv (bus); +u32 rate; +u32 reg; + +debug ("%s: speed=%d\n" , __func__, speed); + rate =DIV_ROUND_UP (rs->sys_freq, speed); +debug ("rate:%u\n" , rate);
drivers/spi/mt76xx_spi.c line 127
Quoted 10 lines
drivers/spi/mt76xx_spi.c new file +10
-0+ +if (rate >4097 ) +return -EINVAL ; + +if (rate <2 ) + rate =2 ; + + reg =mt7621_spi_read (rs,MT7621_SPI_MASTER ); + reg &= ~(0xfff <<16 ); + reg |= (rate -2 ) <<16 ;
same here?
Quoted 40 lines
drivers/spi/mt76xx_spi.c new file +40
-0+mt7621_spi_write (rs,MT7621_SPI_MASTER , reg); + +return 0 ; +} + +static inline int mt7621_spi_wait_till_ready (struct mt7621_spi *rs) +{ +int ret; + + ret =wait_for_bit_le32 (rs->base +MT7621_SPI_TRANS , +MT7621_SPI_TRANS_BUSY ,0 ,10 ,0 ); +if (ret) +pr_err ("Timeout in %s!\n" , __func__); + +return ret; +} + +static int mt7621_spi_xfer (struct udevice *dev,unsigned int bitlen, +const void *dout,void *din,unsigned long flags) +{ +struct udevice *bus = dev->parent; +struct mt7621_spi *rs =dev_get_priv (bus); +const u8 *tx_buf = dout; +u8 *ptr = (u8 *)dout; +u8 *rx_buf = din; +int total_size = bitlen >>3 ; +int chunk_size; +int rx_len =0 ; +u32 data[(SPI_MSG_SIZE_MAX /4 ) +1 ] = {0 }; +u32 val; +int i; + +debug ("%s: dout=%p, din=%p, len=%x, flags=%lx\n" , __func__, dout, din, + total_size, flags); + +/* +* This driver only supports half-duplex, so complain and bail out +* upon full-duplex messages +*/ +if (dout && din) {
drivers/spi/mt76xx_spi.c line 177
Quoted 10 lines
drivers/spi/mt76xx_spi.c new file +10
-0+printf ("Only half-duplex SPI transfer supported\n" ); +return -EIO ; + } + +if (dout) { +debug ("TX-DATA: " ); +for (i =0 ; i < total_size; i++) +debug ("%02x " , *ptr++); +debug ("\n" ); + }
Look like it has only debug, no functionality change here or after wards. any reason?
Quoted 103 lines
drivers/spi/mt76xx_spi.c new file +103
-0+ +mt7621_spi_wait_till_ready (rs); + +/* +* Set CS active upon start of SPI message. This message can +* be split upon multiple calls to this xfer function +*/ +if (flags &SPI_XFER_BEGIN ) +mt7621_spi_set_cs (rs,spi_chip_select (dev),1 ); + +while (total_size >0 ) { +/* Don't exceed the max xfer size */ + chunk_size =min_t (int, total_size,SPI_MSG_SIZE_MAX ); + +/* +* We might have some TX data buffered from the last xfer +* message. Make sure, that this does not exceed the max +* xfer size +*/ +if (rs->tx_len >4 ) + chunk_size -= rs->tx_len; +if (din) + rx_len = chunk_size; + +if (tx_buf) { +/* Check if this message does not exceed the buffer */ +if ((chunk_size + rs->tx_len) >SPI_MSG_SIZE_OVERALL ) { +printf ("TX message size too big (%d)\n" , + chunk_size + rs->tx_len); +return -EMSGSIZE ; + } + +/* +* Write all TX data into internal buffer to collect +* all TX messages into one buffer (might be split into +* multiple calls to this function) +*/ +for (i =0 ; i < chunk_size; i++, rs->tx_len++) { + rs->data[rs->tx_len /4 ] |= + tx_buf[i] << (8 * (rs->tx_len &3 )); + } + } + +if (flags &SPI_XFER_END ) { +/* Write TX data into controller */ +if (rs->tx_len) { + rs->data[0 ] =swab32 (rs->data[0 ]); +if (rs->tx_len <4 ) + rs->data[0 ] >>= (4 - rs->tx_len) *8 ; + +for (i =0 ; i < rs->tx_len; i +=4 ) { +mt7621_spi_write (rs, +MT7621_SPI_OPCODE + i, + rs->data[i /4 ]); + } + } + +/* Write length into controller */ + val = (min_t (int, rs->tx_len,4 ) *8 ) <<24 ; +if (rs->tx_len >4 ) + val |= (rs->tx_len -4 ) *8 ; + val |= (rx_len *8 ) <<12 ; +mt7621_spi_write (rs,MT7621_SPI_MOREBUF , val); + +/* Start the xfer */ + val =mt7621_spi_read (rs,MT7621_SPI_TRANS ); + val |=MT7621_SPI_TRANS_START ; +mt7621_spi_write (rs,MT7621_SPI_TRANS , val); + +/* Wait until xfer is finished on bus */ +mt7621_spi_wait_till_ready (rs); + +/* Reset TX length and TX buffer for next xfer */ + rs->tx_len =0 ; +memset (rs->data,0 ,sizeof (rs->data)); + } + +for (i =0 ; i < rx_len; i +=4 ) + data[i /4 ] =mt7621_spi_read (rs,MT7621_SPI_DATA0 + i); + +if (rx_len) { +debug ("RX-DATA: " ); +for (i =0 ; i < rx_len; i++) { + rx_buf[i] = data[i /4 ] >> (8 * (i &3 )); +debug ("%02x " , rx_buf[i]); + } +debug ("\n" ); + } + +if (tx_buf) + tx_buf += chunk_size; +if (rx_buf) + rx_buf += chunk_size; + total_size -= chunk_size; + } + +/* Wait until xfer is finished on bus and de-assert CS */ +mt7621_spi_wait_till_ready (rs); +if (flags &SPI_XFER_END ) +mt7621_spi_set_cs (rs,spi_chip_select (dev),0 ); + +return 0 ; +}
drivers/spi/mt76xx_spi.c line 290
Quoted 10 lines
drivers/spi/mt76xx_spi.c new file +10
-0+ +static int mt76xx_spi_probe (struct udevice *dev) +{ +struct mt7621_spi *rs =dev_get_priv (dev); + + rs->base =dev_remap_addr (dev); +if (!rs->base) +return -EINVAL ; + + rs->sys_freq =CONFIG_SYS_MIPS_TIMER_FREQ ;
Is this generic timer freq or specific to SPI? can't we get this via DT "spi-max-frequency" ?
PATCH 1/1 spi: Add SPI driver for MT76xx SoCs
Hi Jagan,
Quoted 96 lines · Jagan Teki
Quoted 95 lines · Stefan Roese
This patch adds the SPI driver for the MediaTek MT7688 SoC (and derivates). Its been tested on the LinkIt Smart 7688 and the Gardena Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart Gateway additionally with an SPI NAND on CS1.
Note that the SPI controller only supports a max transfer size of 32 bytes. This driver implementes a workaround to enable bigger xfer sizes to speed up the transfer especially for the SPI NAND support.
Signed-off-by Stefan Roese <[email protected]>Cc Jagan Teki <[email protected]>--- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/mt76xx_spi.c | 314 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 323 insertions(+)create mode 100644
drivers/spi/mt76xx_spi.cdrivers/spi/Kconfig +8
-0@@ -109,6 +109,14 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MT76XX_SPI + bool "MediaTek MT76XX SPI driver" + depends on ARCH_MT7620 + help + Enable the MT76XX SPI driver. This driver can be used to access + the SPI NOR flash on platforms embedding these MediaTek + SPI cores. + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" select CLK_ARMADA_3720drivers/spi/Makefile +1
-0@@ -32,6 +32,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.odrivers/spi/mt76xx_spi.c new file +40
-0@@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright (C) 2018 Stefan Roese <[email protected]> +* +* Derived from the Linux driver version drivers/spi/spi-mt7621.c +* Copyright (C) 2011 Sergiy <[email protected]> +* Copyright (C) 2011-2013 Gabor Juhos <[email protected]> +* Copyright (C) 2014-2015 Felix Fietkau <[email protected]> +*/ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <wait_bit.h> +#include <linux/io.h> + +#define SPI_MSG_SIZE_MAX 32/* SPI message chunk size */ +/* Enough for SPI NAND page read / write with page size 2048 bytes */ +#define SPI_MSG_SIZE_OVERALL (2048 + 16) + +#define MT7621_SPI_TRANS 0x00 +#define MT7621_SPI_TRANS_START BIT(8) +#define MT7621_SPI_TRANS_BUSY BIT(16) + +#define MT7621_SPI_OPCODE 0x04 +#define MT7621_SPI_DATA0 0x08 +#define MT7621_SPI_DATA4 0x18 +#define MT7621_SPI_MASTER 0x28 +#define MT7621_SPI_MOREBUF 0x2c +#define MT7621_SPI_POLAR 0x38 + +#define MT7621_LSB_FIRST BIT(3) +#define MT7621_CPOL BIT(4) +#define MT7621_CPHA BIT(5) + +struct mt7621_spi { +void __iomem *base; +unsigned int sys_freq; +u32 data[(SPI_MSG_SIZE_OVERALL /4 ) +1 ]; +int tx_len;
Quoted 8 lines
drivers/spi/mt76xx_spi.c line 46
Quoted 6 lines
drivers/spi/mt76xx_spi.c new file +6
-0+}; + +static const struct udevice_id mt76xx_spi_ids[] = { + { .compatible ="ralink,mt7621-spi" }, + { } +};This need to move down above
U_BOOT_DRIVER
"Need" is a bit strong here. But if you prefer it this way, I can move it down in v2.
Quoted 11 lines
Quoted 11 lines
drivers/spi/mt76xx_spi.c new file +11
-0+ +static inline u32 mt7621_spi_read (struct mt7621_spi *rs,u32 reg) +{ +return ioread32 (rs->base + reg); +} + +static inline void mt7621_spi_write (struct mt7621_spi *rs,u32 reg,u32 val) +{ +iowrite32 (val, rs->base + reg); +} +
Quoted 8 lines
drivers/spi/mt76xx_spi.c line 63
Quoted 6 lines
drivers/spi/mt76xx_spi.c new file +6
-0+static void mt7621_spi_reset (struct mt7621_spi *rs,int duplex) +{ +u32 master =mt7621_spi_read (rs,MT7621_SPI_MASTER ); + + master |=7 <<29 ;/* CS control */ + master |=1 <<2 ;/* more_buf_mode */ Proper macros with these numericals?
Its not easy with the non-optimal documentation available (at least to me) for this MediaTek SoC. Nevertheless, I will try to come up with some macros here.
Quoted 58 lines
Quoted 58 lines
drivers/spi/mt76xx_spi.c new file +58
-0+ +mt7621_spi_write (rs,MT7621_SPI_MASTER , master); +} + +static void mt7621_spi_set_cs (struct mt7621_spi *rs,int cs,int enable) +{ +u32 val =0 ; + +debug ("%s: cs#%d -> %s\n" , __func__, cs, enable ?"enable" :"disable" ); +if (enable) + val =BIT (cs); +mt7621_spi_write (rs,MT7621_SPI_POLAR , val); +} + +static int mt7621_spi_set_mode (struct udevice *bus,uint mode) +{ +struct mt7621_spi *rs =dev_get_priv (bus); +u32 reg; + +debug ("%s: mode=0x%08x\n" , __func__, mode); + reg =mt7621_spi_read (rs,MT7621_SPI_MASTER ); + + reg &= ~MT7621_LSB_FIRST ; +if (mode &SPI_LSB_FIRST ) + reg |=MT7621_LSB_FIRST ; + + reg &= ~(MT7621_CPHA |MT7621_CPOL ); +switch (mode & (SPI_CPOL |SPI_CPHA )) { +case SPI_MODE_0 : +break ; +case SPI_MODE_1 : + reg |=MT7621_CPHA ; +break ; +case SPI_MODE_2 : + reg |=MT7621_CPOL ; +break ; +case SPI_MODE_3 : + reg |=MT7621_CPOL |MT7621_CPHA ; +break ; + } +mt7621_spi_write (rs,MT7621_SPI_MASTER , reg); + +return 0 ; +} + +static int mt7621_spi_set_speed (struct udevice *bus,uint speed) +{ +struct mt7621_spi *rs =dev_get_priv (bus); +u32 rate; +u32 reg; + +debug ("%s: speed=%d\n" , __func__, speed); + rate =DIV_ROUND_UP (rs->sys_freq, speed); +debug ("rate:%u\n" , rate); + +if (rate >4097 ) +return -EINVAL ; +
Quoted 8 lines
drivers/spi/mt76xx_spi.c line 127
Quoted 6 lines
drivers/spi/mt76xx_spi.c new file +6
-0+if (rate <2 ) + rate =2 ; + + reg =mt7621_spi_read (rs,MT7621_SPI_MASTER ); + reg &= ~(0xfff <<16 ); + reg |= (rate -2 ) <<16 ;same here?
Will try.
Quoted 45 lines
Quoted 45 lines
drivers/spi/mt76xx_spi.c new file +45
-0+mt7621_spi_write (rs,MT7621_SPI_MASTER , reg); + +return 0 ; +} + +static inline int mt7621_spi_wait_till_ready (struct mt7621_spi *rs) +{ +int ret; + + ret =wait_for_bit_le32 (rs->base +MT7621_SPI_TRANS , +MT7621_SPI_TRANS_BUSY ,0 ,10 ,0 ); +if (ret) +pr_err ("Timeout in %s!\n" , __func__); + +return ret; +} + +static int mt7621_spi_xfer (struct udevice *dev,unsigned int bitlen, +const void *dout,void *din,unsigned long flags) +{ +struct udevice *bus = dev->parent; +struct mt7621_spi *rs =dev_get_priv (bus); +const u8 *tx_buf = dout; +u8 *ptr = (u8 *)dout; +u8 *rx_buf = din; +int total_size = bitlen >>3 ; +int chunk_size; +int rx_len =0 ; +u32 data[(SPI_MSG_SIZE_MAX /4 ) +1 ] = {0 }; +u32 val; +int i; + +debug ("%s: dout=%p, din=%p, len=%x, flags=%lx\n" , __func__, dout, din, + total_size, flags); + +/* +* This driver only supports half-duplex, so complain and bail out +* upon full-duplex messages +*/ +if (dout && din) { +printf ("Only half-duplex SPI transfer supported\n" ); +return -EIO ; + } + +if (dout) {
Quoted 8 lines
drivers/spi/mt76xx_spi.c line 177
Quoted 5 lines
drivers/spi/mt76xx_spi.c new file +5
-0+debug ("TX-DATA: " ); +for (i =0 ; i < total_size; i++) +debug ("%02x " , *ptr++); +debug ("\n" ); + }Look like it has only debug, no functionality change here or after wards. any reason?
Yes, its for debugging purpose only. It was very handy when debugging some issues with the SPI NAND support for example.
Quoted 108 lines
Quoted 108 lines
drivers/spi/mt76xx_spi.c new file +108
-0+ +mt7621_spi_wait_till_ready (rs); + +/* +* Set CS active upon start of SPI message. This message can +* be split upon multiple calls to this xfer function +*/ +if (flags &SPI_XFER_BEGIN ) +mt7621_spi_set_cs (rs,spi_chip_select (dev),1 ); + +while (total_size >0 ) { +/* Don't exceed the max xfer size */ + chunk_size =min_t (int, total_size,SPI_MSG_SIZE_MAX ); + +/* +* We might have some TX data buffered from the last xfer +* message. Make sure, that this does not exceed the max +* xfer size +*/ +if (rs->tx_len >4 ) + chunk_size -= rs->tx_len; +if (din) + rx_len = chunk_size; + +if (tx_buf) { +/* Check if this message does not exceed the buffer */ +if ((chunk_size + rs->tx_len) >SPI_MSG_SIZE_OVERALL ) { +printf ("TX message size too big (%d)\n" , + chunk_size + rs->tx_len); +return -EMSGSIZE ; + } + +/* +* Write all TX data into internal buffer to collect +* all TX messages into one buffer (might be split into +* multiple calls to this function) +*/ +for (i =0 ; i < chunk_size; i++, rs->tx_len++) { + rs->data[rs->tx_len /4 ] |= + tx_buf[i] << (8 * (rs->tx_len &3 )); + } + } + +if (flags &SPI_XFER_END ) { +/* Write TX data into controller */ +if (rs->tx_len) { + rs->data[0 ] =swab32 (rs->data[0 ]); +if (rs->tx_len <4 ) + rs->data[0 ] >>= (4 - rs->tx_len) *8 ; + +for (i =0 ; i < rs->tx_len; i +=4 ) { +mt7621_spi_write (rs, +MT7621_SPI_OPCODE + i, + rs->data[i /4 ]); + } + } + +/* Write length into controller */ + val = (min_t (int, rs->tx_len,4 ) *8 ) <<24 ; +if (rs->tx_len >4 ) + val |= (rs->tx_len -4 ) *8 ; + val |= (rx_len *8 ) <<12 ; +mt7621_spi_write (rs,MT7621_SPI_MOREBUF , val); + +/* Start the xfer */ + val =mt7621_spi_read (rs,MT7621_SPI_TRANS ); + val |=MT7621_SPI_TRANS_START ; +mt7621_spi_write (rs,MT7621_SPI_TRANS , val); + +/* Wait until xfer is finished on bus */ +mt7621_spi_wait_till_ready (rs); + +/* Reset TX length and TX buffer for next xfer */ + rs->tx_len =0 ; +memset (rs->data,0 ,sizeof (rs->data)); + } + +for (i =0 ; i < rx_len; i +=4 ) + data[i /4 ] =mt7621_spi_read (rs,MT7621_SPI_DATA0 + i); + +if (rx_len) { +debug ("RX-DATA: " ); +for (i =0 ; i < rx_len; i++) { + rx_buf[i] = data[i /4 ] >> (8 * (i &3 )); +debug ("%02x " , rx_buf[i]); + } +debug ("\n" ); + } + +if (tx_buf) + tx_buf += chunk_size; +if (rx_buf) + rx_buf += chunk_size; + total_size -= chunk_size; + } + +/* Wait until xfer is finished on bus and de-assert CS */ +mt7621_spi_wait_till_ready (rs); +if (flags &SPI_XFER_END ) +mt7621_spi_set_cs (rs,spi_chip_select (dev),0 ); + +return 0 ; +} + +static int mt76xx_spi_probe (struct udevice *dev) +{ +struct mt7621_spi *rs =dev_get_priv (dev); +
Quoted 8 lines
drivers/spi/mt76xx_spi.c line 290
Quoted 5 lines
drivers/spi/mt76xx_spi.c new file +5
-0+ rs->base =dev_remap_addr (dev); +if (!rs->base) +return -EINVAL ; + + rs->sys_freq =CONFIG_SYS_MIPS_TIMER_FREQ ;Is this generic timer freq or specific to SPI? can't we get this via DT "spi-max-frequency" ?
Its not specific to SPI. Its the MIPS base frequency which is an input to the SPI IP core.
Thanks,
Stefan