ARM: dts: socfpga: Add u-boot, dm-pre-reloc to necessary clock nodes

PATCH New Marek Vasut 2 participants 4 messages Aug 8, 2018 – Aug 9, 2018 Arm (32-bit)

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Marek Vasut

author

2018-08-08 20:11 UTC #0 lore raw

PATCH 1/1 ARM: dts: socfpga: Add u-boot, dm-pre-reloc to necessary clock nodes

Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC.

Signed-off-by Marek Vasut <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Ley Foon Tan <[email protected]>

---
 arch/arm/dts/socfpga_arria10.dtsi            |  9 +++++++++
 arch/arm/dts/socfpga_arria10_socdk.dtsi      | 25 +++++++++++++++++++++++++
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +++++++++++++++++
 3 files changed, 51 insertions(+)

arch/arm/dts/socfpga_arria10.dtsi +9 -0

index 2f935a21e9..a428922f8e 100644
@@ -55,6 +55,7 @@
 		device_type = "soc";
 		interrupt-parent = <&intc>;
 		ranges;
+		u-boot,dm-pre-reloc;
 
 		amba {
 			compatible = "simple-bus";

@@ -93,29 +94,35 @@
 		clkmgr at ffd04000 {
 				compatible = "altr,clk-mgr";
 				reg = <0xffd04000 0x1000>;
+				u-boot,dm-pre-reloc;
 
 				clocks {
 					#address-cells = <1>;
 					#size-cells = <0>;
+					u-boot,dm-pre-reloc;
 
 					cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 						#clock-cells = <0>;
 						compatible = "fixed-clock";
+						u-boot,dm-pre-reloc;
 					};
 
 					cb_intosc_ls_clk: cb_intosc_ls_clk {
 						#clock-cells = <0>;
 						compatible = "fixed-clock";
+						u-boot,dm-pre-reloc;
 					};
 
 					f2s_free_clk: f2s_free_clk {
 						#clock-cells = <0>;
 						compatible = "fixed-clock";
+						u-boot,dm-pre-reloc;
 					};
 
 					osc1: osc1 {
 						#clock-cells = <0>;
 						compatible = "fixed-clock";
+						u-boot,dm-pre-reloc;
 					};
 
 					main_pll: main_pll at 40 {

@@ -126,6 +133,7 @@
 						clocks = <&osc1>, <&cb_intosc_ls_clk>,
 							 <&f2s_free_clk>;
 						reg = <0x40>;
+						u-boot,dm-pre-reloc;
 
 						main_mpu_base_clk: main_mpu_base_clk {
 							#clock-cells = <0>;

@@ -214,6 +222,7 @@
 						clocks = <&osc1>, <&cb_intosc_ls_clk>,
 							 <&f2s_free_clk>, <&main_periph_ref_clk>;
 						reg = <0xC0>;
+						u-boot,dm-pre-reloc;
 
 						peri_mpu_base_clk: peri_mpu_base_clk {
 							#clock-cells = <0>;

arch/arm/dts/socfpga_arria10_socdk.dtsi +25 -0

index 3f59f02577..ae54de6990 100644
@@ -166,3 +166,28 @@
 &watchdog1 {
 	status = "okay";
 };
+
+/* Clock available early */
+&main_noc_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&l4_mp_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +17 -0

index 9c6070ded9..998d811210 100644
@@ -38,3 +38,20 @@
 			     <48 IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
+
+/* Clock available early */
+&main_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};

Signature · 1 line

2.16.2

Ley Foon Tan

2018-08-09 08:12 UTC #1 lore raw

PATCH 1/1 ARM: dts: socfpga: Add u-boot, dm-pre-reloc to necessary clock nodes

Quoted 118 lines · Marek Vasut

Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
---
arch/arm/dts/socfpga_arria10.dtsi | 9 +++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 25
+++++++++++++++++++++++++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +++++++++++++++++
 3 files changed, 51 insertions(+)
arch/arm/dts/socfpga_arria10.dtsi +1 -0
index 2f935a21e9..a428922f8e 100644
@@ -55,6 +55,7 @@
  		device_type = "soc";
  		interrupt-parent = <&intc>;
  		ranges;
+		u-boot,dm-pre-reloc;
amba {
compatible = "simple-bus";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
@@ -93,29 +94,35 @@
  		clkmgr at ffd04000 {
  				compatible = "altr,clk-mgr";
  				reg = <0xffd04000 0x1000>;
+				u-boot,dm-pre-reloc;
clocks { #address-cells = <1>; #size-cells = <0>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+					u-boot,dm-pre-reloc;
cb_intosc_hs_div2_clk:
cb_intosc_hs_div2_clk {
#clock-cells = <0>; compatible = "fixed- clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
};

cb_intosc_ls_clk:
cb_intosc_ls_clk {
#clock-cells = <0>; compatible = "fixed- clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
};

f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed- clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
};

osc1: osc1 { #clock-cells = <0>; compatible = "fixed- clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
};

main_pll: main_pll at 40 {
arch/arm/dts/socfpga_arria10.dtsi +0 -0
@@ -126,6 +133,7 @@
  						clocks = <&osc1>,
 <&cb_intosc_ls_clk>,
<&f2s_free_ clk>;
reg = <0x40>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
main_mpu_base_clk:
main_mpu_base_clk {
#clock-cells = <0>;
arch/arm/dts/socfpga_arria10.dtsi +0 -0
@@ -214,6 +222,7 @@
  						clocks = <&osc1>,
 <&cb_intosc_ls_clk>,
<&f2s_free_ clk>, <&main_periph_ref_clk>;
reg = <0xC0>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
peri_mpu_base_clk:
peri_mpu_base_clk {
#clock-cells = <0>;
arch/arm/dts/socfpga_arria10_socdk.dtsi +15 -0
index 3f59f02577..ae54de6990 100644
@@ -166,3 +166,28 @@
  &watchdog1 {
  	status = "okay";
  };
+
+/* Clock available early */
+&main_noc_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {

arch/arm/dts/socfpga_arria10_socdk.dtsi line 193

Quoted 10 lines

arch/arm/dts/socfpga_arria10_socdk.dtsi +10 -0

+	u-boot,dm-pre-reloc;
+};
+
+&l4_mp_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+	u-boot,dm-pre-reloc;
+};

Why don't add these to socfpga_arria10.dtsi?

Quoted 16 lines

arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +7 -0

index 9c6070ded9..998d811210 100644
@@ -38,3 +38,20 @@
  			     <48 IRQ_TYPE_LEVEL_HIGH>;
  	};
  };
+
+/* Clock available early */
+&main_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {

arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts line 57

Quoted 10 lines

arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +10 -0

+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};

Same these too.

Regards
Ley Foon

Marek Vasut

author

2018-08-09 08:14 UTC #2 lore raw

PATCH 1/1 ARM: dts: socfpga: Add u-boot, dm-pre-reloc to necessary clock nodes

Quoted 122 lines · Ley Foon Tan

Quoted 121 lines · Marek Vasut
Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
---
arch/arm/dts/socfpga_arria10.dtsi | 9 +++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 25
+++++++++++++++++++++++++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +++++++++++++++++
 3 files changed, 51 insertions(+)
arch/arm/dts/socfpga_arria10.dtsi +1 -0
index 2f935a21e9..a428922f8e 100644
@@ -55,6 +55,7 @@
  		device_type = "soc";
  		interrupt-parent = <&intc>;
  		ranges;
+		u-boot,dm-pre-reloc;
amba {
compatible = "simple-bus";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
@@ -93,29 +94,35 @@
  		clkmgr at ffd04000 {
  				compatible = "altr,clk-mgr";
  				reg = <0xffd04000 0x1000>;
+				u-boot,dm-pre-reloc;
clocks { #address-cells = <1>; #size-cells = <0>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+					u-boot,dm-pre-reloc;
cb_intosc_hs_div2_clk:
cb_intosc_hs_div2_clk {
#clock-cells = <0>; compatible = "fixed- clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
};

cb_intosc_ls_clk:
cb_intosc_ls_clk {
#clock-cells = <0>; compatible = "fixed- clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
};

f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed- clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
};

osc1: osc1 { #clock-cells = <0>; compatible = "fixed- clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
};

main_pll: main_pll at 40 {
arch/arm/dts/socfpga_arria10.dtsi +0 -0
@@ -126,6 +133,7 @@
  						clocks = <&osc1>,
 <&cb_intosc_ls_clk>,
<&f2s_free_ clk>;
reg = <0x40>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
main_mpu_base_clk:
main_mpu_base_clk {
#clock-cells = <0>;
arch/arm/dts/socfpga_arria10.dtsi +0 -0
@@ -214,6 +222,7 @@
  						clocks = <&osc1>,
 <&cb_intosc_ls_clk>,
<&f2s_free_ clk>, <&main_periph_ref_clk>;
reg = <0xC0>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-reloc;
peri_mpu_base_clk:
peri_mpu_base_clk {
#clock-cells = <0>;
arch/arm/dts/socfpga_arria10_socdk.dtsi +18 -0
index 3f59f02577..ae54de6990 100644
@@ -166,3 +166,28 @@
  &watchdog1 {
  	status = "okay";
  };
+
+/* Clock available early */
+&main_noc_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {
+	u-boot,dm-pre-reloc;
+};
+

Quoted 8 lines

arch/arm/dts/socfpga_arria10_socdk.dtsi line 193
Quoted 7 lines
arch/arm/dts/socfpga_arria10_socdk.dtsi +7 -0
+&l4_mp_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+	u-boot,dm-pre-reloc;
+};
Why don't add these to socfpga_arria10.dtsi?

They're SoCDK specific and may not be needed on other platforms.

Quoted 19 lines

arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +10 -0

index 9c6070ded9..998d811210 100644
@@ -38,3 +38,20 @@
  			     <48 IRQ_TYPE_LEVEL_HIGH>;
  	};
  };
+
+/* Clock available early */
+&main_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+

Quoted 8 lines

arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts line 57
Quoted 7 lines
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +7 -0
+&sdmmc_free_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
Same these too.

They are specific to the setup booting from SDMMC.

Signature · 2 lines

Best regards,
Marek Vasut

Ley Foon Tan

2018-08-09 09:13 UTC #3 lore raw

PATCH 1/1 ARM: dts: socfpga: Add u-boot, dm-pre-reloc to necessary clock nodes

Quoted 159 lines · Marek Vasut

Quoted 150 lines · Ley Foon Tan
Quoted 148 lines · Marek Vasut
Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
---
arch/arm/dts/socfpga_arria10.dtsi | 9 +++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 25
+++++++++++++++++++++++++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17
+++++++++++++++++
 3 files changed, 51 insertions(+)
arch/arm/dts/socfpga_arria10.dtsi +1 -0
index 2f935a21e9..a428922f8e 100644
@@ -55,6 +55,7 @@
  		device_type = "soc";
  		interrupt-parent = <&intc>;
  		ranges;
+		u-boot,dm-pre-reloc;
amba {
compatible = "simple-bus";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
@@ -93,29 +94,35 @@
  		clkmgr at ffd04000 {
  				compatible = "altr,clk-mgr";
  				reg = <0xffd04000 0x1000>;
+				u-boot,dm-pre-reloc;
clocks { #address-cells = <1>; #size-cells = <0>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+					u-boot,dm-pre-reloc;
cb_intosc_hs_div2_clk:
cb_intosc_hs_div2_clk {
#clock-cells = <0>;
compatible = "fixed-
clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-
reloc;
};

cb_intosc_ls_clk:
cb_intosc_ls_clk {
#clock-cells = <0>;
compatible = "fixed-
clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-
reloc;
};

f2s_free_clk:
f2s_free_clk {
#clock-cells = <0>;
compatible = "fixed-
clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-
reloc;
};

osc1: osc1 { #clock-cells = <0>;
compatible = "fixed-
clock";
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-
reloc;
};

main_pll: main_pll at 40 {
arch/arm/dts/socfpga_arria10.dtsi +0 -0
@@ -126,6 +133,7 @@
clocks = <&osc1>,
<&cb_intosc_ls_clk>,
<&f2s_f ree_
clk>;
reg = <0x40>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-
reloc;

main_mpu_base_cl k:
main_mpu_base_clk {
#clock- cells
= <0>;
arch/arm/dts/socfpga_arria10.dtsi +0 -0
@@ -214,6 +222,7 @@
clocks = <&osc1>,
<&cb_intosc_ls_clk>,
<&f2s_f ree_
clk>, <&main_periph_ref_clk>;
reg = <0xC0>;
arch/arm/dts/socfpga_arria10.dtsi +1 -0
+						u-boot,dm-pre-
reloc;

peri_mpu_base_cl k:
peri_mpu_base_clk {
#clock- cells
= <0>;
arch/arm/dts/socfpga_arria10_socdk.dtsi +18 -0
index 3f59f02577..ae54de6990 100644
@@ -166,3 +166,28 @@
  &watchdog1 {
  	status = "okay";
  };
+
+/* Clock available early */
+&main_noc_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {
+	u-boot,dm-pre-reloc;
+};
+
Quoted 8 lines
arch/arm/dts/socfpga_arria10_socdk.dtsi line 193
Quoted 7 lines
arch/arm/dts/socfpga_arria10_socdk.dtsi +7 -0
+&l4_mp_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+	u-boot,dm-pre-reloc;
+};
Why don't add these to socfpga_arria10.dtsi?

Quoted 1 line

They're SoCDK specific and may not be needed on other platforms.

Okay.

Quoted 30 lines

Quoted 22 lines
Quoted 22 lines
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +10 -0
index 9c6070ded9..998d811210 100644
@@ -38,3 +38,20 @@
  			     <48 IRQ_TYPE_LEVEL_HIGH>;
  	};
  };
+
+/* Clock available early */
+&main_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
Quoted 8 lines
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts line 57
Quoted 7 lines
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +7 -0
+&sdmmc_free_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
Same these too.

Quoted 1 line

They are specific to the setup booting from SDMMC.

Okay.

Regards
Ley Foon