timer: dw-apb: Add Designware APB timer driver
Subsystems (3)
PATCH 1/3 timer: dw-apb: Add Designware APB timer driver
Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
--- drivers/timer/Kconfig | 7 ++++ drivers/timer/Makefile | 1 + drivers/timer/dw-apb-timer.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+) create mode 100644 drivers/timer/dw-apb-timer.c
drivers/timer/Kconfig +7 -0
@@ -59,6 +59,13 @@ config CADENCE_TTC_TIMER Enables support for the cadence ttc driver. This driver is present on Xilinx Zynq and ZynqMP SoCs. +config DESIGNWARE_APB_TIMER + bool "Designware APB Timer" + depends on TIMER + help + Enables support for the Designware APB Timer driver. This timer is + present on Altera SoCFPGA SoCs. + config SANDBOX_TIMER bool "Sandbox timer support" depends on SANDBOX && TIMER
drivers/timer/Makefile +1 -0
@@ -5,6 +5,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o +obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
drivers/timer/dw-apb-timer.c new file +90 -0
90 lines not on this page · raw message
Signature · 1 line
2.16.2
PATCH 2/3 ARM: dts: socfpga: Flag timer clock as pre-reloc
Flag timer clock as DM pre-reloc, so that a timer driver can be used and it can extract information about it's clock rate using the clock framework. This patch also moves some of the pre-reloc flags into the core dtsi file, this is because the timer is not board specific, but rather is used on all boards.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
--- arch/arm/dts/socfpga_arria10.dtsi | 10 ++++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 12 ------------ 2 files changed, 10 insertions(+), 12 deletions(-)
arch/arm/dts/socfpga_arria10.dtsi +10 -0
@@ -21,6 +21,11 @@ #address-cells = <1>; #size-cells = <1>; + chosen { + tick-timer = &timer2; + u-boot,dm-pre-reloc; + }; + cpus { #address-cells = <1>; #size-cells = <0>;
@@ -147,6 +152,7 @@ compatible = "altr,socfpga-a10-perip-clk"; clocks = <&main_pll>; div-reg = <0x144 0 11>; + u-boot,dm-pre-reloc; }; main_emaca_clk: main_emaca_clk at 68 {
@@ -236,6 +242,7 @@ compatible = "altr,socfpga-a10-perip-clk"; clocks = <&periph_pll>; div-reg = <0x144 16 11>; + u-boot,dm-pre-reloc; }; peri_emaca_clk: peri_emaca_clk at e8 {
@@ -311,6 +318,7 @@ <&osc1>, <&cb_intosc_hs_div2_clk>, <&f2s_free_clk>; reg = <0x64>; + u-boot,dm-pre-reloc; }; s2f_user1_free_clk: s2f_user1_free_clk at 104 {
@@ -337,6 +345,7 @@ compatible = "altr,socfpga-a10-perip-clk"; clocks = <&noc_free_clk>; fixed-divider = <4>; + u-boot,dm-pre-reloc; }; l4_main_clk: l4_main_clk {
@@ -800,6 +809,7 @@ reg = <0xffd00000 0x100>; clocks = <&l4_sys_free_clk>; clock-names = "timer"; + u-boot,dm-pre-reloc; }; timer3: timer3 at ffd00100 {
arch/arm/dts/socfpga_arria10_socdk.dtsi +0 -12
@@ -169,22 +169,10 @@ }; /* Clock available early */ -&main_noc_base_clk { - u-boot,dm-pre-reloc; -}; - &main_periph_ref_clk { u-boot,dm-pre-reloc; }; -&peri_noc_base_clk { - u-boot,dm-pre-reloc; -}; - -&noc_free_clk { - u-boot,dm-pre-reloc; -}; - &l4_mp_clk { u-boot,dm-pre-reloc; };
Signature · 1 line
2.16.2
PATCH 3/3 ARM: socfpga: Convert Arria10 to timer framework
In reply to Marek VasutSwitch the Arria10 from ad-hoc hardcoded timer to timer framework and the DW APB timer driver. This allows the A10 to extract timer information, like timer rate, from clock framework and thus DT instead of having it hardcoded in U-Boot configuration files.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Ley Foon Tan <[email protected]>
--- arch/arm/mach-socfpga/Makefile | 1 - configs/socfpga_arria10_defconfig | 3 +++ include/configs/socfpga_common.h | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-)
arch/arm/mach-socfpga/Makefile +0 -1
@@ -26,7 +26,6 @@ obj-y += clock_manager_arria10.o obj-y += misc_arria10.o obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o -obj-y += timer.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
configs/socfpga_arria10_defconfig +3 -0
@@ -39,4 +39,7 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y CONFIG_USE_TINY_PRINTF=y
include/configs/socfpga_common.h +2 -0
@@ -86,11 +86,13 @@/* * L4 OSC1 Timer 0 */ +#ifndef CONFIG_TIMER /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)#define CONFIG_SYS_TIMER_RATE 25000000 +#endif /* * L4 Watchdog
Signature · 1 line
2.16.2